blob: 5ba2b6d64348803c770d46e7c06298149fabe067 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
wdenk42d1f032003-10-15 23:53:47 +00002/*
Kumar Gala7c57f3e2011-01-11 00:52:35 -06003 * Copyright 2004, 2011 Freescale Semiconductor.
wdenk42d1f032003-10-15 23:53:47 +00004 * (C) Copyright 2002,2003 Motorola,Inc.
5 * Xianghua Xiao <X.Xiao@motorola.com>
wdenk42d1f032003-10-15 23:53:47 +00006 */
7
wdenk0ac6f8b2004-07-09 23:27:13 +00008/*
9 * mpc8560ads board configuration file
10 *
11 * Please refer to doc/README.mpc85xx for more info.
12 *
13 * Make sure you change the MAC address and other network params first,
Joe Hershberger92ac5202015-05-04 14:55:14 -050014 * search for CONFIG_SERVERIP, etc. in this file.
wdenk42d1f032003-10-15 23:53:47 +000015 */
16
17#ifndef __CONFIG_H
18#define __CONFIG_H
19
20/* High Level Configuration Options */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050021#define CONFIG_CPM2 1 /* has CPM2 */
wdenk42d1f032003-10-15 23:53:47 +000022
Wolfgang Denk2ae18242010-10-06 09:05:45 +020023/*
24 * default CCARBAR is at 0xff700000
25 * assume U-Boot is less than 0.5MB
26 */
Wolfgang Denk2ae18242010-10-06 09:05:45 +020027
Gabor Juhos842033e2013-05-30 07:06:12 +000028#define CONFIG_PCI_INDIRECT_BRIDGE
Kumar Gala0151cba2008-10-21 11:33:58 -050029#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Andy Flemingccc091a2007-05-08 17:27:43 -050030#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
wdenk42d1f032003-10-15 23:53:47 +000031#define CONFIG_ENV_OVERWRITE
Peter Tyser004eca02009-09-16 22:03:08 -050032#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
wdenk42d1f032003-10-15 23:53:47 +000033
wdenk0ac6f8b2004-07-09 23:27:13 +000034/*
35 * sysclk for MPC85xx
36 *
37 * Two valid values are:
38 * 33000000
39 * 66000000
40 *
41 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
wdenk9aea9532004-08-01 23:02:45 +000042 * is likely the desired value here, so that is now the default.
43 * The board, however, can run at 66MHz. In any event, this value
44 * must match the settings of some switches. Details can be found
45 * in the README.mpc85xxads.
wdenk0ac6f8b2004-07-09 23:27:13 +000046 */
47
wdenk9aea9532004-08-01 23:02:45 +000048#ifndef CONFIG_SYS_CLK_FREQ
49#define CONFIG_SYS_CLK_FREQ 33000000
wdenk42d1f032003-10-15 23:53:47 +000050#endif
51
wdenk0ac6f8b2004-07-09 23:27:13 +000052/*
53 * These can be toggled for performance analysis, otherwise use default.
54 */
55#define CONFIG_L2_CACHE /* toggle L2 cache */
56#define CONFIG_BTB /* toggle branch predition */
wdenk42d1f032003-10-15 23:53:47 +000057
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020058#define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
wdenk42d1f032003-10-15 23:53:47 +000059
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020060#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
61#define CONFIG_SYS_MEMTEST_END 0x00400000
wdenk42d1f032003-10-15 23:53:47 +000062
Timur Tabie46fedf2011-08-04 18:03:41 -050063#define CONFIG_SYS_CCSRBAR 0xe0000000
64#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
wdenk42d1f032003-10-15 23:53:47 +000065
Jon Loeliger8b625112008-03-18 11:12:44 -050066/* DDR Setup */
Jon Loeliger8b625112008-03-18 11:12:44 -050067#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
68#define CONFIG_DDR_SPD
wdenk9aea9532004-08-01 23:02:45 +000069
Jon Loeliger8b625112008-03-18 11:12:44 -050070#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
71
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
73#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
wdenk9aea9532004-08-01 23:02:45 +000074
Jon Loeliger8b625112008-03-18 11:12:44 -050075#define CONFIG_DIMM_SLOTS_PER_CTLR 1
76#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
wdenk9aea9532004-08-01 23:02:45 +000077
Jon Loeliger8b625112008-03-18 11:12:44 -050078/* I2C addresses of SPD EEPROMs */
79#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
wdenk9aea9532004-08-01 23:02:45 +000080
Jon Loeliger8b625112008-03-18 11:12:44 -050081/* These are used when DDR doesn't use SPD. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020082#define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */
83#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
84#define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002
85#define CONFIG_SYS_DDR_TIMING_1 0x37344321
86#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
87#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
88#define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
89#define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
wdenk42d1f032003-10-15 23:53:47 +000090
wdenk0ac6f8b2004-07-09 23:27:13 +000091/*
92 * SDRAM on the Local Bus
93 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020094#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
95#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
wdenk42d1f032003-10-15 23:53:47 +000096
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
98#define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */
wdenk42d1f032003-10-15 23:53:47 +000099
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200100#define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
101#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
102#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
103#undef CONFIG_SYS_FLASH_CHECKSUM
104#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
105#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
wdenk42d1f032003-10-15 23:53:47 +0000106
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200107#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
wdenk0ac6f8b2004-07-09 23:27:13 +0000108
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
110#define CONFIG_SYS_RAMBOOT
wdenk42d1f032003-10-15 23:53:47 +0000111#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112#undef CONFIG_SYS_RAMBOOT
wdenk42d1f032003-10-15 23:53:47 +0000113#endif
114
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115#define CONFIG_SYS_FLASH_EMPTY_INFO
wdenk0ac6f8b2004-07-09 23:27:13 +0000116
117#undef CONFIG_CLOCKS_IN_MHZ
wdenk42d1f032003-10-15 23:53:47 +0000118
wdenk0ac6f8b2004-07-09 23:27:13 +0000119/*
120 * Local Bus Definitions
121 */
122
123/*
124 * Base Register 2 and Option Register 2 configure SDRAM.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
wdenk0ac6f8b2004-07-09 23:27:13 +0000126 *
127 * For BR2, need:
128 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
129 * port-size = 32-bits = BR2[19:20] = 11
130 * no parity checking = BR2[21:22] = 00
131 * SDRAM for MSEL = BR2[24:26] = 011
132 * Valid = BR[31] = 1
133 *
134 * 0 4 8 12 16 20 24 28
135 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
136 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
wdenk0ac6f8b2004-07-09 23:27:13 +0000138 * FIXME: the top 17 bits of BR2.
139 */
140
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_BR2_PRELIM 0xf0001861
wdenk0ac6f8b2004-07-09 23:27:13 +0000142
143/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
wdenk0ac6f8b2004-07-09 23:27:13 +0000145 *
146 * For OR2, need:
147 * 64MB mask for AM, OR2[0:7] = 1111 1100
148 * XAM, OR2[17:18] = 11
149 * 9 columns OR2[19-21] = 010
150 * 13 rows OR2[23-25] = 100
151 * EAD set for extra time OR[31] = 1
152 *
153 * 0 4 8 12 16 20 24 28
154 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
155 */
156
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_OR2_PRELIM 0xfc006901
wdenk0ac6f8b2004-07-09 23:27:13 +0000158
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
160#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
161#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
162#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
wdenk0ac6f8b2004-07-09 23:27:13 +0000163
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500164#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \
165 | LSDMR_RFCR5 \
166 | LSDMR_PRETOACT3 \
167 | LSDMR_ACTTORW3 \
168 | LSDMR_BL8 \
169 | LSDMR_WRC2 \
170 | LSDMR_CL3 \
171 | LSDMR_RFEN \
wdenk0ac6f8b2004-07-09 23:27:13 +0000172 )
173
174/*
175 * SDRAM Controller configuration sequence.
176 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500177#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
178#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
179#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
180#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
181#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
wdenk0ac6f8b2004-07-09 23:27:13 +0000182
wdenk9aea9532004-08-01 23:02:45 +0000183/*
184 * 32KB, 8-bit wide for ADS config reg
185 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_BR4_PRELIM 0xf8000801
187#define CONFIG_SYS_OR4_PRELIM 0xffffe1f1
188#define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
wdenk42d1f032003-10-15 23:53:47 +0000189
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_SYS_INIT_RAM_LOCK 1
191#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200192#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
wdenk42d1f032003-10-15 23:53:47 +0000193
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200194#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk42d1f032003-10-15 23:53:47 +0000196
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
198#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
wdenk42d1f032003-10-15 23:53:47 +0000199
200/* Serial Port */
wdenk0ac6f8b2004-07-09 23:27:13 +0000201#define CONFIG_CONS_ON_SCC /* define if console on SCC */
202#undef CONFIG_CONS_NONE /* define if console on something else */
wdenk42d1f032003-10-15 23:53:47 +0000203
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_BAUDRATE_TABLE \
wdenk42d1f032003-10-15 23:53:47 +0000205 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
206
Jon Loeliger20476722006-10-20 15:50:15 -0500207/*
208 * I2C
209 */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200210#define CONFIG_SYS_I2C
211#define CONFIG_SYS_I2C_FSL
212#define CONFIG_SYS_FSL_I2C_SPEED 400000
213#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
214#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
215#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
wdenk42d1f032003-10-15 23:53:47 +0000216
wdenk0ac6f8b2004-07-09 23:27:13 +0000217/* RapidIO MMU */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600218#define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */
Kumar Gala10795f42008-12-02 16:08:36 -0600219#define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600220#define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
wdenk42d1f032003-10-15 23:53:47 +0000222
wdenk0ac6f8b2004-07-09 23:27:13 +0000223/*
224 * General PCI
Sergei Shtylyov362dd832006-12-27 22:07:15 +0300225 * Memory space is mapped 1-1, but I/O space must start from 0.
wdenk0ac6f8b2004-07-09 23:27:13 +0000226 */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600227#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
Kumar Gala10795f42008-12-02 16:08:36 -0600228#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600229#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600231#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600232#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
234#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
wdenk0ac6f8b2004-07-09 23:27:13 +0000235
236#if defined(CONFIG_PCI)
wdenk0ac6f8b2004-07-09 23:27:13 +0000237#undef CONFIG_EEPRO100
wdenk42d1f032003-10-15 23:53:47 +0000238#undef CONFIG_TULIP
wdenk0ac6f8b2004-07-09 23:27:13 +0000239
240#if !defined(CONFIG_PCI_PNP)
241 #define PCI_ENET0_IOADDR 0xe0000000
242 #define PCI_ENET0_MEMADDR 0xe0000000
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200243 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
wdenk42d1f032003-10-15 23:53:47 +0000244#endif
wdenk0ac6f8b2004-07-09 23:27:13 +0000245
246#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200247#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
wdenk0ac6f8b2004-07-09 23:27:13 +0000248
249#endif /* CONFIG_PCI */
250
Andy Flemingccc091a2007-05-08 17:27:43 -0500251#ifdef CONFIG_TSEC_ENET
wdenk0ac6f8b2004-07-09 23:27:13 +0000252
Kim Phillips255a35772007-05-16 16:52:19 -0500253#define CONFIG_TSEC1 1
254#define CONFIG_TSEC1_NAME "TSEC0"
255#define CONFIG_TSEC2 1
256#define CONFIG_TSEC2_NAME "TSEC1"
wdenk0ac6f8b2004-07-09 23:27:13 +0000257#define TSEC1_PHY_ADDR 0
258#define TSEC2_PHY_ADDR 1
259#define TSEC1_PHYIDX 0
260#define TSEC2_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500261#define TSEC1_FLAGS TSEC_GIGABIT
262#define TSEC2_FLAGS TSEC_GIGABIT
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500263
264/* Options are: TSEC[0-1] */
265#define CONFIG_ETHPRIME "TSEC0"
wdenk0ac6f8b2004-07-09 23:27:13 +0000266
Andy Flemingccc091a2007-05-08 17:27:43 -0500267#endif /* CONFIG_TSEC_ENET */
wdenk0ac6f8b2004-07-09 23:27:13 +0000268
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200269#ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */
Andy Flemingccc091a2007-05-08 17:27:43 -0500270
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200271#undef CONFIG_ETHER_NONE /* define if ether on something else */
wdenk0ac6f8b2004-07-09 23:27:13 +0000272#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
273
274#if (CONFIG_ETHER_INDEX == 2)
wdenk42d1f032003-10-15 23:53:47 +0000275 /*
276 * - Rx-CLK is CLK13
277 * - Tx-CLK is CLK14
278 * - Select bus for bd/buffers
279 * - Full duplex
280 */
Mike Frysingerd4590da2011-10-17 05:38:58 +0000281 #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
282 #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283 #define CONFIG_SYS_CPMFCR_RAMTYPE 0
284 #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE)
wdenk42d1f032003-10-15 23:53:47 +0000285 #define FETH2_RST 0x01
wdenk0ac6f8b2004-07-09 23:27:13 +0000286#elif (CONFIG_ETHER_INDEX == 3)
wdenk42d1f032003-10-15 23:53:47 +0000287 /* need more definitions here for FE3 */
288 #define FETH3_RST 0x80
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200289#endif /* CONFIG_ETHER_INDEX */
wdenk0ac6f8b2004-07-09 23:27:13 +0000290
wdenk0ac6f8b2004-07-09 23:27:13 +0000291#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
292
wdenk42d1f032003-10-15 23:53:47 +0000293/*
294 * GPIO pins used for bit-banged MII communications
295 */
296#define MDIO_PORT 2 /* Port C */
Luigi 'Comio' Mantellinibe225442009-10-10 12:42:22 +0200297#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
298 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
299#define MDC_DECLARE MDIO_DECLARE
300
wdenk42d1f032003-10-15 23:53:47 +0000301#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
302#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
303#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
304
305#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
306 else iop->pdat &= ~0x00400000
307
308#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
309 else iop->pdat &= ~0x00200000
310
311#define MIIDELAY udelay(1)
wdenk0ac6f8b2004-07-09 23:27:13 +0000312
wdenk42d1f032003-10-15 23:53:47 +0000313#endif
314
wdenk0ac6f8b2004-07-09 23:27:13 +0000315/*
316 * Environment
317 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200318#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200319 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200320 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
321 #define CONFIG_ENV_SIZE 0x2000
wdenk42d1f032003-10-15 23:53:47 +0000322#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200323 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200324 #define CONFIG_ENV_SIZE 0x2000
wdenk42d1f032003-10-15 23:53:47 +0000325#endif
326
wdenk0ac6f8b2004-07-09 23:27:13 +0000327#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200328#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenk42d1f032003-10-15 23:53:47 +0000329
Jon Loeliger2835e512007-06-13 13:22:08 -0500330/*
Jon Loeliger659e2f62007-07-10 09:10:49 -0500331 * BOOTP options
332 */
333#define CONFIG_BOOTP_BOOTFILESIZE
Jon Loeliger659e2f62007-07-10 09:10:49 -0500334
wdenk0ac6f8b2004-07-09 23:27:13 +0000335#undef CONFIG_WATCHDOG /* watchdog disabled */
wdenk42d1f032003-10-15 23:53:47 +0000336
337/*
338 * Miscellaneous configurable options
339 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200340#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
wdenk0ac6f8b2004-07-09 23:27:13 +0000341
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200342#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk42d1f032003-10-15 23:53:47 +0000343
344/*
345 * For booting Linux, the board info and command line data
Kumar Galaa832ac42011-04-28 10:13:41 -0500346 * have to be in the first 64 MB of memory, since this is
wdenk42d1f032003-10-15 23:53:47 +0000347 * the maximum mapped by the Linux kernel during initialization.
348 */
Kumar Galaa832ac42011-04-28 10:13:41 -0500349#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
350#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
wdenk42d1f032003-10-15 23:53:47 +0000351
Jon Loeliger2835e512007-06-13 13:22:08 -0500352#if defined(CONFIG_CMD_KGDB)
wdenk42d1f032003-10-15 23:53:47 +0000353#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
wdenk42d1f032003-10-15 23:53:47 +0000354#endif
355
wdenk9aea9532004-08-01 23:02:45 +0000356/*
357 * Environment Configuration
358 */
wdenk42d1f032003-10-15 23:53:47 +0000359#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
Andy Fleming10327dc2007-08-16 16:35:02 -0500360#define CONFIG_HAS_ETH0
wdenke2ffd592004-12-31 09:32:47 +0000361#define CONFIG_HAS_ETH1
wdenke2ffd592004-12-31 09:32:47 +0000362#define CONFIG_HAS_ETH2
Kumar Gala5ce71582007-11-28 22:40:31 -0600363#define CONFIG_HAS_ETH3
wdenk42d1f032003-10-15 23:53:47 +0000364#endif
365
wdenk0ac6f8b2004-07-09 23:27:13 +0000366#define CONFIG_IPADDR 192.168.1.253
367
Mario Six5bc05432018-03-28 14:38:20 +0200368#define CONFIG_HOSTNAME "unknown"
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000369#define CONFIG_ROOTPATH "/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000370#define CONFIG_BOOTFILE "your.uImage"
wdenk0ac6f8b2004-07-09 23:27:13 +0000371
372#define CONFIG_SERVERIP 192.168.1.1
373#define CONFIG_GATEWAYIP 192.168.1.1
374#define CONFIG_NETMASK 255.255.255.0
375
376#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
377
wdenk9aea9532004-08-01 23:02:45 +0000378#define CONFIG_EXTRA_ENV_SETTINGS \
Andy Fleming6b44a442008-07-14 20:04:40 -0500379 "netdev=eth0\0" \
380 "consoledev=ttyCPM\0" \
381 "ramdiskaddr=1000000\0" \
382 "ramdiskfile=your.ramdisk.u-boot\0" \
383 "fdtaddr=400000\0" \
384 "fdtfile=mpc8560ads.dtb\0"
wdenk0ac6f8b2004-07-09 23:27:13 +0000385
wdenk9aea9532004-08-01 23:02:45 +0000386#define CONFIG_NFSBOOTCOMMAND \
Andy Fleming6b44a442008-07-14 20:04:40 -0500387 "setenv bootargs root=/dev/nfs rw " \
388 "nfsroot=$serverip:$rootpath " \
389 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
390 "console=$consoledev,$baudrate $othbootargs;" \
391 "tftp $loadaddr $bootfile;" \
392 "tftp $fdtaddr $fdtfile;" \
393 "bootm $loadaddr - $fdtaddr"
wdenk0ac6f8b2004-07-09 23:27:13 +0000394
395#define CONFIG_RAMBOOTCOMMAND \
Andy Fleming6b44a442008-07-14 20:04:40 -0500396 "setenv bootargs root=/dev/ram rw " \
397 "console=$consoledev,$baudrate $othbootargs;" \
398 "tftp $ramdiskaddr $ramdiskfile;" \
399 "tftp $loadaddr $bootfile;" \
400 "tftp $fdtaddr $fdtfile;" \
401 "bootm $loadaddr $ramdiskaddr $fdtaddr"
wdenk0ac6f8b2004-07-09 23:27:13 +0000402
403#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
wdenk42d1f032003-10-15 23:53:47 +0000404
405#endif /* __CONFIG_H */