| Joseph Chen | 695693b | 2021-06-02 16:13:46 +0800 | [diff] [blame] | 1 | CONFIG_ARM=y |
| Tom Rini | a2ac2b9 | 2021-08-27 21:18:30 -0400 | [diff] [blame] | 2 | CONFIG_SKIP_LOWLEVEL_INIT=y |
| Joseph Chen | 695693b | 2021-06-02 16:13:46 +0800 | [diff] [blame] | 3 | CONFIG_ARCH_ROCKCHIP=y |
| 4 | CONFIG_SYS_TEXT_BASE=0x00a00000 |
| 5 | CONFIG_NR_DRAM_BANKS=2 |
| Tom Rini | fd075f7 | 2021-07-08 07:54:35 -0400 | [diff] [blame] | 6 | CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb" |
| Joseph Chen | 695693b | 2021-06-02 16:13:46 +0800 | [diff] [blame] | 7 | CONFIG_ROCKCHIP_RK3568=y |
| 8 | CONFIG_TARGET_EVB_RK3568=y |
| 9 | CONFIG_DEBUG_UART_BASE=0xFE660000 |
| 10 | CONFIG_DEBUG_UART_CLOCK=24000000 |
| Joseph Chen | 695693b | 2021-06-02 16:13:46 +0800 | [diff] [blame] | 11 | CONFIG_DEBUG_UART=y |
| Tom Rini | 49c8ef0 | 2021-08-23 10:25:31 -0400 | [diff] [blame] | 12 | CONFIG_SYS_LOAD_ADDR=0xc00800 |
| Joseph Chen | 695693b | 2021-06-02 16:13:46 +0800 | [diff] [blame] | 13 | CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb.dtb" |
| 14 | # CONFIG_DISPLAY_CPUINFO is not set |
| 15 | CONFIG_DISPLAY_BOARDINFO_LATE=y |
| 16 | CONFIG_CMD_GPT=y |
| 17 | CONFIG_CMD_MMC=y |
| 18 | # CONFIG_CMD_SETEXPR is not set |
| 19 | CONFIG_NET_RANDOM_ETHADDR=y |
| 20 | CONFIG_ROCKCHIP_GPIO=y |
| 21 | CONFIG_SYS_I2C_ROCKCHIP=y |
| 22 | CONFIG_MISC=y |
| Tom Rini | d5bfef2 | 2021-12-11 14:55:53 -0500 | [diff] [blame^] | 23 | CONFIG_SUPPORT_EMMC_RPMB=y |
| Joseph Chen | 695693b | 2021-06-02 16:13:46 +0800 | [diff] [blame] | 24 | CONFIG_MMC_DW=y |
| 25 | CONFIG_MMC_DW_ROCKCHIP=y |
| 26 | CONFIG_MMC_SDHCI=y |
| 27 | CONFIG_MMC_SDHCI_SDMA=y |
| 28 | CONFIG_MMC_SDHCI_ROCKCHIP=y |
| 29 | CONFIG_DM_ETH=y |
| 30 | CONFIG_ETH_DESIGNWARE=y |
| 31 | CONFIG_GMAC_ROCKCHIP=y |
| 32 | CONFIG_REGULATOR_PWM=y |
| 33 | CONFIG_PWM_ROCKCHIP=y |
| 34 | CONFIG_DM_RESET=y |
| 35 | CONFIG_BAUDRATE=1500000 |
| 36 | CONFIG_DEBUG_UART_SHIFT=2 |
| 37 | CONFIG_SYSRESET=y |
| 38 | CONFIG_ERRNO_STR=y |