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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Tom Rix8966eb42009-06-28 12:52:28 -05002/*
3 * Copyright (c) 2009 Wind River Systems, Inc.
4 * Tom Rix <Tom.Rix at windriver.com>
5 *
Tom Rix8966eb42009-06-28 12:52:28 -05006 * Derived from code on omapzoom, git://git.omapzoom.com/repo/u-boot.git
7 *
8 * Copyright (C) 2007-2009 Texas Instruments, Inc.
9 */
10
11#ifndef TWL4030_H
12#define TWL4030_H
13
14#include <common.h>
15#include <i2c.h>
16
17/* I2C chip addresses */
18
19/* USB */
20#define TWL4030_CHIP_USB 0x48
21/* AUD */
22#define TWL4030_CHIP_AUDIO_VOICE 0x49
23#define TWL4030_CHIP_GPIO 0x49
24#define TWL4030_CHIP_INTBR 0x49
25#define TWL4030_CHIP_PIH 0x49
26#define TWL4030_CHIP_TEST 0x49
27/* AUX */
28#define TWL4030_CHIP_KEYPAD 0x4a
29#define TWL4030_CHIP_MADC 0x4a
30#define TWL4030_CHIP_INTERRUPTS 0x4a
31#define TWL4030_CHIP_LED 0x4a
32#define TWL4030_CHIP_MAIN_CHARGE 0x4a
33#define TWL4030_CHIP_PRECHARGE 0x4a
34#define TWL4030_CHIP_PWM0 0x4a
35#define TWL4030_CHIP_PWM1 0x4a
36#define TWL4030_CHIP_PWMA 0x4a
37#define TWL4030_CHIP_PWMB 0x4a
38/* POWER */
39#define TWL4030_CHIP_BACKUP 0x4b
40#define TWL4030_CHIP_INT 0x4b
41#define TWL4030_CHIP_PM_MASTER 0x4b
42#define TWL4030_CHIP_PM_RECEIVER 0x4b
43#define TWL4030_CHIP_RTC 0x4b
44#define TWL4030_CHIP_SECURED_REG 0x4b
45
46/* Register base addresses */
47
48/* USB */
49#define TWL4030_BASEADD_USB 0x0000
50/* AUD */
51#define TWL4030_BASEADD_AUDIO_VOICE 0x0000
52#define TWL4030_BASEADD_GPIO 0x0098
53#define TWL4030_BASEADD_INTBR 0x0085
54#define TWL4030_BASEADD_PIH 0x0080
55#define TWL4030_BASEADD_TEST 0x004C
56/* AUX */
57#define TWL4030_BASEADD_INTERRUPTS 0x00B9
58#define TWL4030_BASEADD_LED 0x00EE
59#define TWL4030_BASEADD_MADC 0x0000
60#define TWL4030_BASEADD_MAIN_CHARGE 0x0074
61#define TWL4030_BASEADD_PRECHARGE 0x00AA
62#define TWL4030_BASEADD_PWM0 0x00F8
63#define TWL4030_BASEADD_PWM1 0x00FB
64#define TWL4030_BASEADD_PWMA 0x00EF
65#define TWL4030_BASEADD_PWMB 0x00F1
66#define TWL4030_BASEADD_KEYPAD 0x00D2
67/* POWER */
68#define TWL4030_BASEADD_BACKUP 0x0014
69#define TWL4030_BASEADD_INT 0x002E
70#define TWL4030_BASEADD_PM_MASTER 0x0036
71#define TWL4030_BASEADD_PM_RECIEVER 0x005B
72#define TWL4030_BASEADD_RTC 0x001C
73#define TWL4030_BASEADD_SECURED_REG 0x0000
74
75/*
76 * Power Management Master
77 */
78#define TWL4030_PM_MASTER_CFG_P1_TRANSITION 0x36
79#define TWL4030_PM_MASTER_CFG_P2_TRANSITION 0x37
80#define TWL4030_PM_MASTER_CFG_P3_TRANSITION 0x38
81#define TWL4030_PM_MASTER_CFG_P123_TRANSITION 0x39
82#define TWL4030_PM_MASTER_STS_BOOT 0x3A
83#define TWL4030_PM_MASTER_CFG_BOOT 0x3B
84#define TWL4030_PM_MASTER_SHUNDAN 0x3C
85#define TWL4030_PM_MASTER_BOOT_BCI 0x3D
86#define TWL4030_PM_MASTER_CFG_PWRANA1 0x3E
87#define TWL4030_PM_MASTER_CFG_PWRANA2 0x3F
88#define TWL4030_PM_MASTER_BGAP_TRIM 0x40
89#define TWL4030_PM_MASTER_BACKUP_MISC_STS 0x41
90#define TWL4030_PM_MASTER_BACKUP_MISC_CFG 0x42
91#define TWL4030_PM_MASTER_BACKUP_MISC_TST 0x43
92#define TWL4030_PM_MASTER_PROTECT_KEY 0x44
93#define TWL4030_PM_MASTER_STS_HW_CONDITIONS 0x45
94#define TWL4030_PM_MASTER_P1_SW_EVENTS 0x46
95#define TWL4030_PM_MASTER_P2_SW_EVENTS 0x47
96#define TWL4030_PM_MASTER_P3_SW_EVENTS 0x48
97#define TWL4030_PM_MASTER_STS_P123_STATE 0x49
98#define TWL4030_PM_MASTER_PB_CFG 0x4A
99#define TWL4030_PM_MASTER_PB_WORD_MSB 0x4B
100#define TWL4030_PM_MASTER_PB_WORD_LSB 0x4C
101#define TWL4030_PM_MASTER_SEQ_ADD_W2P 0x52
102#define TWL4030_PM_MASTER_SEQ_ADD_P2A 0x53
103#define TWL4030_PM_MASTER_SEQ_ADD_A2W 0x54
104#define TWL4030_PM_MASTER_SEQ_ADD_A2S 0x55
105#define TWL4030_PM_MASTER_SEQ_ADD_S2A12 0x56
106#define TWL4030_PM_MASTER_SEQ_ADD_S2A3 0x57
107#define TWL4030_PM_MASTER_SEQ_ADD_WARM 0x58
108#define TWL4030_PM_MASTER_MEMORY_ADDRESS 0x59
109#define TWL4030_PM_MASTER_MEMORY_DATA 0x5A
110#define TWL4030_PM_MASTER_SC_CONFIG 0x5B
111#define TWL4030_PM_MASTER_SC_DETECT1 0x5C
112#define TWL4030_PM_MASTER_SC_DETECT2 0x5D
113#define TWL4030_PM_MASTER_WATCHDOG_CFG 0x5E
114#define TWL4030_PM_MASTER_IT_CHECK_CFG 0x5F
115#define TWL4030_PM_MASTER_VIBRATOR_CFG 0x60
116#define TWL4030_PM_MASTER_DCDC_GLOBAL_CFG 0x61
117#define TWL4030_PM_MASTER_VDD1_TRIM1 0x62
118#define TWL4030_PM_MASTER_VDD1_TRIM2 0x63
119#define TWL4030_PM_MASTER_VDD2_TRIM1 0x64
120#define TWL4030_PM_MASTER_VDD2_TRIM2 0x65
121#define TWL4030_PM_MASTER_VIO_TRIM1 0x66
122#define TWL4030_PM_MASTER_VIO_TRIM2 0x67
123#define TWL4030_PM_MASTER_MISC_CFG 0x68
124#define TWL4030_PM_MASTER_LS_TST_A 0x69
125#define TWL4030_PM_MASTER_LS_TST_B 0x6A
126#define TWL4030_PM_MASTER_LS_TST_C 0x6B
127#define TWL4030_PM_MASTER_LS_TST_D 0x6C
128#define TWL4030_PM_MASTER_BB_CFG 0x6D
129#define TWL4030_PM_MASTER_MISC_TST 0x6E
130#define TWL4030_PM_MASTER_TRIM1 0x6F
Tom Rix8966eb42009-06-28 12:52:28 -0500131
Pali Rohár318e70e2012-10-19 02:00:06 +0000132/* Power bus message definitions */
133
134/* The TWL4030/5030 splits its power-management resources (the various
135 * regulators, clock and reset lines) into 3 processor groups - P1, P2 and
136 * P3. These groups can then be configured to transition between sleep, wait-on
137 * and active states by sending messages to the power bus. See Section 5.4.2
138 * Power Resources of TWL4030 TRM
139 */
140
141/* Processor groups */
142#define DEV_GRP_NULL 0x0
143#define DEV_GRP_P1 0x1 /* P1: all OMAP devices */
144#define DEV_GRP_P2 0x2 /* P2: all Modem devices */
145#define DEV_GRP_P3 0x4 /* P3: all peripheral devices */
146
147/* Resource groups */
148#define RES_GRP_RES 0x0 /* Reserved */
149#define RES_GRP_PP 0x1 /* Power providers */
150#define RES_GRP_RC 0x2 /* Reset and control */
151#define RES_GRP_PP_RC 0x3
152#define RES_GRP_PR 0x4 /* Power references */
153#define RES_GRP_PP_PR 0x5
154#define RES_GRP_RC_PR 0x6
155#define RES_GRP_ALL 0x7 /* All resource groups */
156
157#define RES_TYPE2_R0 0x0
158
159#define RES_TYPE_ALL 0x7
160
161/* Resource states */
162#define RES_STATE_WRST 0xF
163#define RES_STATE_ACTIVE 0xE
164#define RES_STATE_SLEEP 0x8
165#define RES_STATE_OFF 0x0
166
167/* Power resources */
168
169/* Power providers */
170#define RES_VAUX1 1
171#define RES_VAUX2 2
172#define RES_VAUX3 3
173#define RES_VAUX4 4
174#define RES_VMMC1 5
175#define RES_VMMC2 6
176#define RES_VPLL1 7
177#define RES_VPLL2 8
178#define RES_VSIM 9
179#define RES_VDAC 10
180#define RES_VINTANA1 11
181#define RES_VINTANA2 12
182#define RES_VINTDIG 13
183#define RES_VIO 14
184#define RES_VDD1 15
185#define RES_VDD2 16
186#define RES_VUSB_1V5 17
187#define RES_VUSB_1V8 18
188#define RES_VUSB_3V1 19
189#define RES_VUSBCP 20
190#define RES_REGEN 21
191/* Reset and control */
192#define RES_NRES_PWRON 22
193#define RES_CLKEN 23
194#define RES_SYSEN 24
195#define RES_HFCLKOUT 25
196#define RES_32KCLKOUT 26
197#define RES_RESET 27
198/* Power Reference */
199#define RES_Main_Ref 28
200
Paul Kocialkowski6dc443e2015-07-20 15:17:07 +0200201/* P[1-3]_SW_EVENTS */
202#define TWL4030_PM_MASTER_SW_EVENTS_STOPON_PWRON (1 << 6)
203#define TWL4030_PM_MASTER_SW_EVENTS_STOPON_SYSEN (1 << 5)
204#define TWL4030_PM_MASTER_SW_EVENTS_ENABLE_WARMRESET (1 << 4)
205#define TWL4030_PM_MASTER_SW_EVENTS_LVL_WAKEUP (1 << 3)
206#define TWL4030_PM_MASTER_SW_EVENTS_DEVACT (1 << 2)
207#define TWL4030_PM_MASTER_SW_EVENTS_DEVSLP (1 << 1)
208#define TWL4030_PM_MASTER_SW_EVENTS_DEVOFF (1 << 0)
209
Paul Kocialkowski7d5ac912015-07-20 15:17:08 +0200210/* HW conditions */
211#define TWL4030_PM_MASTER_STS_HW_CONDITIONS_PWON (1 << 0)
212#define TWL4030_PM_MASTER_STS_HW_CONDITIONS_CHG (1 << 1)
213#define TWL4030_PM_MASTER_STS_HW_CONDITIONS_USB (1 << 2)
214#define TWL4030_PM_MASTER_STS_HW_CONDITIONS_VBUS (1 << 7)
215
Paul Kocialkowski6dc443e2015-07-20 15:17:07 +0200216/* Power transition */
217#define TWL4030_PM_MASTER_CFG_TRANSITION_STARTON_PWON (1 << 0)
218#define TWL4030_PM_MASTER_CFG_TRANSITION_STARTON_CHG (1 << 1)
219#define TWL4030_PM_MASTER_CFG_TRANSITION_STARTON_USB (1 << 2)
220#define TWL4030_PM_MASTER_CFG_TRANSITION_STARTON_RTC (1 << 3)
221#define TWL4030_PM_MASTER_CFG_TRANSITION_STARTON_VBAT (1 << 4)
222#define TWL4030_PM_MASTER_CFG_TRANSITION_STARTON_VBUS (1 << 5)
223#define TWL4030_PM_MASTER_CFG_TRANSITION_STARTON_SWBUG (1 << 7)
224
225/* PWRANA2 */
226#define TWL4030_PM_MASTER_CFG_PWRANA2_LOJIT0_LOWV (1 << 1)
227#define TWL4030_PM_MASTER_CFG_PWRANA2_LOJIT1_LOWV (1 << 2)
228
Pali Rohár318e70e2012-10-19 02:00:06 +0000229#define TOTAL_RESOURCES 28
230/*
231 * Power Bus Message Format ... these can be sent individually by Linux,
232 * but are usually part of downloaded scripts that are run when various
233 * power events are triggered.
234 *
235 * Broadcast Message (16 Bits):
236 * DEV_GRP[15:13] MT[12] RES_GRP[11:9] RES_TYPE2[8:7] RES_TYPE[6:4]
237 * RES_STATE[3:0]
238 *
239 * Singular Message (16 Bits):
240 * DEV_GRP[15:13] MT[12] RES_ID[11:4] RES_STATE[3:0]
241 */
242
243#define MSG_BROADCAST(devgrp, grp, type, type2, state) \
244 ((devgrp) << 13 | 1 << 12 | (grp) << 9 | (type2) << 7 \
245 | (type) << 4 | (state))
246
247#define MSG_SINGULAR(devgrp, id, state) \
248 ((devgrp) << 13 | 0 << 12 | (id) << 4 | (state))
249
250#define MSG_BROADCAST_ALL(devgrp, state) \
251 ((devgrp) << 5 | (state))
252
253#define MSG_BROADCAST_REF MSG_BROADCAST_ALL
254#define MSG_BROADCAST_PROV MSG_BROADCAST_ALL
255#define MSG_BROADCAST__CLK_RST MSG_BROADCAST_ALL
256
Tom Rix8966eb42009-06-28 12:52:28 -0500257/* Power Managment Receiver */
Tom Rix2c155132009-06-28 12:52:30 -0500258#define TWL4030_PM_RECEIVER_SC_CONFIG 0x5B
259#define TWL4030_PM_RECEIVER_SC_DETECT1 0x5C
260#define TWL4030_PM_RECEIVER_SC_DETECT2 0x5D
261#define TWL4030_PM_RECEIVER_WATCHDOG_CFG 0x5E
262#define TWL4030_PM_RECEIVER_IT_CHECK_CFG 0x5F
263#define TWL4030_PM_RECEIVER_VIBRATOR_CFG 0x5F
264#define TWL4030_PM_RECEIVER_DC_TO_DC_CFG 0x61
265#define TWL4030_PM_RECEIVER_VDD1_TRIM1 0x62
266#define TWL4030_PM_RECEIVER_VDD1_TRIM2 0x63
267#define TWL4030_PM_RECEIVER_VDD2_TRIM1 0x64
268#define TWL4030_PM_RECEIVER_VDD2_TRIM2 0x65
269#define TWL4030_PM_RECEIVER_VIO_TRIM1 0x66
270#define TWL4030_PM_RECEIVER_VIO_TRIM2 0x67
271#define TWL4030_PM_RECEIVER_MISC_CFG 0x68
272#define TWL4030_PM_RECEIVER_LS_TST_A 0x69
273#define TWL4030_PM_RECEIVER_LS_TST_B 0x6A
274#define TWL4030_PM_RECEIVER_LS_TST_C 0x6B
275#define TWL4030_PM_RECEIVER_LS_TST_D 0x6C
276#define TWL4030_PM_RECEIVER_BB_CFG 0x6D
277#define TWL4030_PM_RECEIVER_MISC_TST 0x6E
278#define TWL4030_PM_RECEIVER_TRIM1 0x6F
279#define TWL4030_PM_RECEIVER_TRIM2 0x70
280#define TWL4030_PM_RECEIVER_DC_DC_TIMEOUT 0x71
281#define TWL4030_PM_RECEIVER_VAUX1_DEV_GRP 0x72
282#define TWL4030_PM_RECEIVER_VAUX1_TYPE 0x73
283#define TWL4030_PM_RECEIVER_VAUX1_REMAP 0x74
284#define TWL4030_PM_RECEIVER_VAUX1_DEDICATED 0x75
285#define TWL4030_PM_RECEIVER_VAUX2_DEV_GRP 0x76
286#define TWL4030_PM_RECEIVER_VAUX2_TYPE 0x77
287#define TWL4030_PM_RECEIVER_VAUX2_REMAP 0x78
288#define TWL4030_PM_RECEIVER_VAUX2_DEDICATED 0x79
289#define TWL4030_PM_RECEIVER_VAUX3_DEV_GRP 0x7A
290#define TWL4030_PM_RECEIVER_VAUX3_TYPE 0x7B
291#define TWL4030_PM_RECEIVER_VAUX3_REMAP 0x7C
292#define TWL4030_PM_RECEIVER_VAUX3_DEDICATED 0x7D
293#define TWL4030_PM_RECEIVER_VAUX4_DEV_GRP 0x7E
294#define TWL4030_PM_RECEIVER_VAUX4_TYPE 0x7F
295#define TWL4030_PM_RECEIVER_VAUX4_REMAP 0x80
296#define TWL4030_PM_RECEIVER_VAUX4_DEDICATED 0x81
297#define TWL4030_PM_RECEIVER_VMMC1_DEV_GRP 0x82
298#define TWL4030_PM_RECEIVER_VMMC1_TYPE 0x83
299#define TWL4030_PM_RECEIVER_VMMC1_REMAP 0x84
300#define TWL4030_PM_RECEIVER_VMMC1_DEDICATED 0x85
301#define TWL4030_PM_RECEIVER_VMMC2_DEV_GRP 0x86
302#define TWL4030_PM_RECEIVER_VMMC2_TYPE 0x87
303#define TWL4030_PM_RECEIVER_VMMC2_REMAP 0x88
304#define TWL4030_PM_RECEIVER_VMMC2_DEDICATED 0x89
305#define TWL4030_PM_RECEIVER_VPLL1_DEV_GRP 0x8A
306#define TWL4030_PM_RECEIVER_VPLL1_TYPE 0x8B
307#define TWL4030_PM_RECEIVER_VPLL1_REMAP 0x8C
308#define TWL4030_PM_RECEIVER_VPLL1_DEDICATED 0x8D
309#define TWL4030_PM_RECEIVER_VPLL2_DEV_GRP 0x8E
310#define TWL4030_PM_RECEIVER_VPLL2_TYPE 0x8F
311#define TWL4030_PM_RECEIVER_VPLL2_REMAP 0x90
312#define TWL4030_PM_RECEIVER_VPLL2_DEDICATED 0x91
313#define TWL4030_PM_RECEIVER_VSIM_DEV_GRP 0x92
314#define TWL4030_PM_RECEIVER_VSIM_TYPE 0x93
315#define TWL4030_PM_RECEIVER_VSIM_REMAP 0x94
316#define TWL4030_PM_RECEIVER_VSIM_DEDICATED 0x95
317#define TWL4030_PM_RECEIVER_VDAC_DEV_GRP 0x96
318#define TWL4030_PM_RECEIVER_VDAC_TYPE 0x97
319#define TWL4030_PM_RECEIVER_VDAC_REMAP 0x98
320#define TWL4030_PM_RECEIVER_VDAC_DEDICATED 0x99
321#define TWL4030_PM_RECEIVER_VINTANA1_DEV_GRP 0x9A
322#define TWL4030_PM_RECEIVER_VINTANA1_TYP 0x9B
323#define TWL4030_PM_RECEIVER_VINTANA1_REMAP 0x9C
324#define TWL4030_PM_RECEIVER_VINTANA1_DEDICATED 0x9D
325#define TWL4030_PM_RECEIVER_VINTANA2_DEV_GRP 0x9E
326#define TWL4030_PM_RECEIVER_VINTANA2_TYPE 0x9F
327#define TWL4030_PM_RECEIVER_VINTANA2_REMAP 0xA0
328#define TWL4030_PM_RECEIVER_VINTANA2_DEDICATED 0xA1
329#define TWL4030_PM_RECEIVER_VINTDIG_DEV_GRP 0xA2
330#define TWL4030_PM_RECEIVER_VINTDIG_TYPE 0xA3
331#define TWL4030_PM_RECEIVER_VINTDIG_REMAP 0xA4
332#define TWL4030_PM_RECEIVER_VINTDIG_DEDICATED 0xA5
333#define TWL4030_PM_RECEIVER_VIO_DEV_GRP 0xA6
334#define TWL4030_PM_RECEIVER_VIO_TYPE 0xA7
335#define TWL4030_PM_RECEIVER_VIO_REMAP 0xA8
336#define TWL4030_PM_RECEIVER_VIO_CFG 0xA9
337#define TWL4030_PM_RECEIVER_VIO_MISC_CFG 0xAA
338#define TWL4030_PM_RECEIVER_VIO_TEST1 0xAB
339#define TWL4030_PM_RECEIVER_VIO_TEST2 0xAC
340#define TWL4030_PM_RECEIVER_VIO_OSC 0xAD
341#define TWL4030_PM_RECEIVER_VIO_RESERVED 0xAE
342#define TWL4030_PM_RECEIVER_VIO_VSEL 0xAF
343#define TWL4030_PM_RECEIVER_VDD1_DEV_GRP 0xB0
344#define TWL4030_PM_RECEIVER_VDD1_TYPE 0xB1
345#define TWL4030_PM_RECEIVER_VDD1_REMAP 0xB2
346#define TWL4030_PM_RECEIVER_VDD1_CFG 0xB3
347#define TWL4030_PM_RECEIVER_VDD1_MISC_CFG 0xB4
348#define TWL4030_PM_RECEIVER_VDD1_TEST1 0xB5
349#define TWL4030_PM_RECEIVER_VDD1_TEST2 0xB6
350#define TWL4030_PM_RECEIVER_VDD1_OSC 0xB7
351#define TWL4030_PM_RECEIVER_VDD1_RESERVED 0xB8
352#define TWL4030_PM_RECEIVER_VDD1_VSEL 0xB9
353#define TWL4030_PM_RECEIVER_VDD1_VMODE_CFG 0xBA
354#define TWL4030_PM_RECEIVER_VDD1_VFLOOR 0xBB
355#define TWL4030_PM_RECEIVER_VDD1_VROOF 0xBC
356#define TWL4030_PM_RECEIVER_VDD1_STEP 0xBD
357#define TWL4030_PM_RECEIVER_VDD2_DEV_GRP 0xBE
358#define TWL4030_PM_RECEIVER_VDD2_TYPE 0xBF
359#define TWL4030_PM_RECEIVER_VDD2_REMAP 0xC0
360#define TWL4030_PM_RECEIVER_VDD2_CFG 0xC1
361#define TWL4030_PM_RECEIVER_VDD2_MISC_CFG 0xC2
362#define TWL4030_PM_RECEIVER_VDD2_TEST1 0xC3
363#define TWL4030_PM_RECEIVER_VDD2_TEST2 0xC4
364#define TWL4030_PM_RECEIVER_VDD2_OSC 0xC5
365#define TWL4030_PM_RECEIVER_VDD2_RESERVED 0xC6
366#define TWL4030_PM_RECEIVER_VDD2_VSEL 0xC7
367#define TWL4030_PM_RECEIVER_VDD2_VMODE_CFG 0xC8
368#define TWL4030_PM_RECEIVER_VDD2_VFLOOR 0xC9
369#define TWL4030_PM_RECEIVER_VDD2_VROOF 0xCA
370#define TWL4030_PM_RECEIVER_VDD2_STEP 0xCB
Tom Rix8966eb42009-06-28 12:52:28 -0500371#define TWL4030_PM_RECEIVER_VUSB1V5_DEV_GRP 0xCC
372#define TWL4030_PM_RECEIVER_VUSB1V5_TYPE 0xCD
373#define TWL4030_PM_RECEIVER_VUSB1V5_REMAP 0xCE
374#define TWL4030_PM_RECEIVER_VUSB1V8_DEV_GRP 0xCF
375#define TWL4030_PM_RECEIVER_VUSB1V8_TYPE 0xD0
376#define TWL4030_PM_RECEIVER_VUSB1V8_REMAP 0xD1
377#define TWL4030_PM_RECEIVER_VUSB3V1_DEV_GRP 0xD2
378#define TWL4030_PM_RECEIVER_VUSB3V1_TYPE 0xD3
379#define TWL4030_PM_RECEIVER_VUSB3V1_REMAP 0xD4
380#define TWL4030_PM_RECEIVER_VUSBCP_DEV_GRP 0xD5
Tom Rix2c155132009-06-28 12:52:30 -0500381#define TWL4030_PM_RECEIVER_VUSBCP_TYPE 0xD6
382#define TWL4030_PM_RECEIVER_VUSBCP_REMAP 0xD7
Tom Rix8966eb42009-06-28 12:52:28 -0500383#define TWL4030_PM_RECEIVER_VUSB_DEDICATED1 0xD8
384#define TWL4030_PM_RECEIVER_VUSB_DEDICATED2 0xD9
Tom Rix2c155132009-06-28 12:52:30 -0500385#define TWL4030_PM_RECEIVER_REGEN_DEV_GRP 0xDA
386#define TWL4030_PM_RECEIVER_REGEN_TYPE 0xDB
387#define TWL4030_PM_RECEIVER_REGEN_REMAP 0xDC
388#define TWL4030_PM_RECEIVER_NRESPWRON_DEV_GRP 0xDD
389#define TWL4030_PM_RECEIVER_NRESPWRON_TYPE 0xDE
390#define TWL4030_PM_RECEIVER_NRESPWRON_REMAP 0xDF
391#define TWL4030_PM_RECEIVER_CLKEN_DEV_GRP 0xE0
392#define TWL4030_PM_RECEIVER_CLKEN_TYPE 0xE1
393#define TWL4030_PM_RECEIVER_CLKEN_REMAP 0xE2
394#define TWL4030_PM_RECEIVER_SYSEN_DEV_GRP 0xE3
395#define TWL4030_PM_RECEIVER_SYSEN_TYPE 0xE4
396#define TWL4030_PM_RECEIVER_SYSEN_REMAP 0xE5
397#define TWL4030_PM_RECEIVER_HFCLKOUT_DEV_GRP 0xE6
398#define TWL4030_PM_RECEIVER_HFCLKOUT_TYPE 0xE7
399#define TWL4030_PM_RECEIVER_HFCLKOUT_REMAP 0xE8
400#define TWL4030_PM_RECEIVER_32KCLKOUT_DEV_GRP 0xE9
401#define TWL4030_PM_RECEIVER_32KCLKOUT_TYPE 0xEA
402#define TWL4030_PM_RECEIVER_32KCLKOUT_REMAP 0xEB
403#define TWL4030_PM_RECEIVER_TRITON_RESET_DEV_GRP 0xEC
404#define TWL4030_PM_RECEIVER_TRITON_RESET_TYPE 0xED
405#define TWL4030_PM_RECEIVER_TRITON_RESET_REMAP 0xEE
406#define TWL4030_PM_RECEIVER_MAINREF_DEV_GRP 0xEF
407#define TWL4030_PM_RECEIVER_MAINREF_TYPE 0xF0
408#define TWL4030_PM_RECEIVER_MAINREF_REMAP 0xF1
409
Steve Sakoman5a0a82f2010-08-10 12:58:39 -0700410/* Voltage Selection in PM Receiver Module */
411#define TWL4030_PM_RECEIVER_VAUX2_VSEL_18 0x05
Paul Kocialkowski71bfb0f2014-10-28 16:10:59 +0100412#define TWL4030_PM_RECEIVER_VAUX2_VSEL_28 0x09
413#define TWL4030_PM_RECEIVER_VAUX3_VSEL_18 0x01
Steve Sakoman5a0a82f2010-08-10 12:58:39 -0700414#define TWL4030_PM_RECEIVER_VAUX3_VSEL_28 0x03
415#define TWL4030_PM_RECEIVER_VPLL2_VSEL_18 0x05
416#define TWL4030_PM_RECEIVER_VDAC_VSEL_18 0x03
417#define TWL4030_PM_RECEIVER_VMMC1_VSEL_30 0x02
Ash Charles528cdca2011-09-28 06:47:16 +0000418#define TWL4030_PM_RECEIVER_VMMC1_VSEL_32 0x03
Paul Kocialkowski2ed8c872014-10-28 18:14:23 +0100419#define TWL4030_PM_RECEIVER_VMMC2_VSEL_30 0x0B
420#define TWL4030_PM_RECEIVER_VMMC2_VSEL_32 0x0C
Pali Rohár318e70e2012-10-19 02:00:06 +0000421#define TWL4030_PM_RECEIVER_VSIM_VSEL_18 0x03
Steve Sakoman5a0a82f2010-08-10 12:58:39 -0700422
423/* Device Selection in PM Receiver Module */
424#define TWL4030_PM_RECEIVER_DEV_GRP_P1 0x20
425#define TWL4030_PM_RECEIVER_DEV_GRP_ALL 0xE0
426
Tom Rix2c155132009-06-28 12:52:30 -0500427/* LED */
428#define TWL4030_LED_LEDEN 0xEE
Grazvydas Ignotasead39d72009-12-10 17:10:21 +0200429#define TWL4030_LED_LEDEN_LEDAON (1 << 0)
430#define TWL4030_LED_LEDEN_LEDBON (1 << 1)
431#define TWL4030_LED_LEDEN_LEDAPWM (1 << 4)
432#define TWL4030_LED_LEDEN_LEDBPWM (1 << 5)
Tom Rix8966eb42009-06-28 12:52:28 -0500433
434/* Keypad */
435#define TWL4030_KEYPAD_KEYP_CTRL_REG 0xD2
436#define TWL4030_KEYPAD_KEY_DEB_REG 0xD3
437#define TWL4030_KEYPAD_LONG_KEY_REG1 0xD4
438#define TWL4030_KEYPAD_LK_PTV_REG 0xD5
439#define TWL4030_KEYPAD_TIME_OUT_REG1 0xD6
440#define TWL4030_KEYPAD_TIME_OUT_REG2 0xD7
441#define TWL4030_KEYPAD_KBC_REG 0xD8
442#define TWL4030_KEYPAD_KBR_REG 0xD9
443#define TWL4030_KEYPAD_KEYP_SMS 0xDA
444#define TWL4030_KEYPAD_FULL_CODE_7_0 0xDB
445#define TWL4030_KEYPAD_FULL_CODE_15_8 0xDC
446#define TWL4030_KEYPAD_FULL_CODE_23_16 0xDD
447#define TWL4030_KEYPAD_FULL_CODE_31_24 0xDE
448#define TWL4030_KEYPAD_FULL_CODE_39_32 0xDF
449#define TWL4030_KEYPAD_FULL_CODE_47_40 0xE0
450#define TWL4030_KEYPAD_FULL_CODE_55_48 0xE1
451#define TWL4030_KEYPAD_FULL_CODE_63_56 0xE2
452#define TWL4030_KEYPAD_KEYP_ISR1 0xE3
453#define TWL4030_KEYPAD_KEYP_IMR1 0xE4
454#define TWL4030_KEYPAD_KEYP_ISR2 0xE5
455#define TWL4030_KEYPAD_KEYP_IMR2 0xE6
456#define TWL4030_KEYPAD_KEYP_SIR 0xE7
457#define TWL4030_KEYPAD_KEYP_EDR 0xE8
458#define TWL4030_KEYPAD_KEYP_SIH_CTRL 0xE9
459
460#define TWL4030_KEYPAD_CTRL_KBD_ON (1 << 6)
461#define TWL4030_KEYPAD_CTRL_RP_EN (1 << 5)
462#define TWL4030_KEYPAD_CTRL_TOLE_EN (1 << 4)
463#define TWL4030_KEYPAD_CTRL_TOE_EN (1 << 3)
464#define TWL4030_KEYPAD_CTRL_LK_EN (1 << 2)
465#define TWL4030_KEYPAD_CTRL_SOFTMODEN (1 << 1)
466#define TWL4030_KEYPAD_CTRL_SOFT_NRST (1 << 0)
467
468/* USB */
Tom Rixbffbb2a2009-10-31 12:37:40 -0500469#define TWL4030_USB_VENDOR_ID_LO 0x00
470#define TWL4030_USB_VENDOR_ID_HI 0x01
471#define TWL4030_USB_PRODUCT_ID_LO 0x02
472#define TWL4030_USB_PRODUCT_ID_HI 0x03
473#define TWL4030_USB_FUNC_CTRL 0x04
474#define TWL4030_USB_FUNC_CTRL_SET 0x05
475#define TWL4030_USB_FUNC_CTRL_CLR 0x06
476#define TWL4030_USB_IFC_CTRL 0x07
477#define TWL4030_USB_IFC_CTRL_SET 0x08
478#define TWL4030_USB_IFC_CTRL_CLR 0x09
479#define TWL4030_USB_OTG_CTRL 0x0A
480#define TWL4030_USB_OTG_CTRL_SET 0x0B
481#define TWL4030_USB_OTG_CTRL_CLR 0x0C
482#define TWL4030_USB_USB_INT_EN_RISE 0x0D
483#define TWL4030_USB_USB_INT_EN_RISE_SET 0x0E
484#define TWL4030_USB_USB_INT_EN_RISE_CLR 0x0F
485#define TWL4030_USB_USB_INT_EN_FALL 0x10
486#define TWL4030_USB_USB_INT_EN_FALL_SET 0x11
487#define TWL4030_USB_USB_INT_EN_FALL_CLR 0x12
488#define TWL4030_USB_USB_INT_STS 0x13
489#define TWL4030_USB_USB_INT_LATCH 0x14
490#define TWL4030_USB_DEBUG 0x15
491#define TWL4030_USB_SCRATCH_REG 0x16
492#define TWL4030_USB_SCRATCH_REG_SET 0x17
493#define TWL4030_USB_SCRATCH_REG_CLR 0x18
494#define TWL4030_USB_CARKIT_CTRL 0x19
495#define TWL4030_USB_CARKIT_CTRL_SET 0x1A
496#define TWL4030_USB_CARKIT_CTRL_CLR 0x1B
497#define TWL4030_USB_CARKIT_INT_DELAY 0x1C
498#define TWL4030_USB_CARKIT_INT_EN 0x1D
499#define TWL4030_USB_CARKIT_INT_EN_SET 0x1E
500#define TWL4030_USB_CARKIT_INT_EN_CLR 0x1F
501#define TWL4030_USB_CARKIT_INT_STS 0x20
502#define TWL4030_USB_CARKIT_INT_LATCH 0x21
503#define TWL4030_USB_CARKIT_PLS_CTRL 0x22
504#define TWL4030_USB_CARKIT_PLS_CTRL_SET 0x23
505#define TWL4030_USB_CARKIT_PLS_CTRL_CLR 0x24
506#define TWL4030_USB_TRANS_POS_WIDTH 0x25
507#define TWL4030_USB_TRANS_NEG_WIDTH 0x26
508#define TWL4030_USB_RCV_PLTY_RECOVERY 0x27
509#define TWL4030_USB_MCPC_CTRL 0x30
510#define TWL4030_USB_MCPC_CTRL_SET 0x31
511#define TWL4030_USB_MCPC_CTRL_CLR 0x32
512#define TWL4030_USB_MCPC_IO_CTRL 0x33
513#define TWL4030_USB_MCPC_IO_CTRL_SET 0x34
514#define TWL4030_USB_MCPC_IO_CTRL_CLR 0x35
515#define TWL4030_USB_MCPC_CTRL2 0x36
516#define TWL4030_USB_MCPC_CTRL2_SET 0x37
517#define TWL4030_USB_MCPC_CTRL2_CLR 0x38
518#define TWL4030_USB_OTHER_FUNC_CTRL 0x80
519#define TWL4030_USB_OTHER_FUNC_CTRL_SET 0x81
520#define TWL4030_USB_OTHER_FUNC_CTRL_CLR 0x82
521#define TWL4030_USB_OTHER_IFC_CTRL 0x83
522#define TWL4030_USB_OTHER_IFC_CTRL_SET 0x84
523#define TWL4030_USB_OTHER_IFC_CTRL_CLR 0x85
524#define TWL4030_USB_OTHER_INT_EN_RISE_SET 0x87
525#define TWL4030_USB_OTHER_INT_EN_RISE_CLR 0x88
526#define TWL4030_USB_OTHER_INT_EN_FALL 0x89
527#define TWL4030_USB_OTHER_INT_EN_FALL_SET 0x8A
528#define TWL4030_USB_OTHER_INT_EN_FALL_CLR 0x8B
529#define TWL4030_USB_OTHER_INT_STS 0x8C
530#define TWL4030_USB_OTHER_INT_LATCH 0x8D
531#define TWL4030_USB_ID_STATUS 0x96
532#define TWL4030_USB_CARKIT_SM_1_INT_EN 0x97
533#define TWL4030_USB_CARKIT_SM_1_INT_EN_SET 0x98
534#define TWL4030_USB_CARKIT_SM_1_INT_EN_CLR 0x99
535#define TWL4030_USB_CARKIT_SM_1_INT_STS 0x9A
536#define TWL4030_USB_CARKIT_SM_1_INT_LATCH 0x9B
537#define TWL4030_USB_CARKIT_SM_2_INT_EN 0x9C
538#define TWL4030_USB_CARKIT_SM_2_INT_EN_SET 0x9D
539#define TWL4030_USB_CARKIT_SM_2_INT_EN_CLR 0x9E
540#define TWL4030_USB_CARKIT_SM_2_INT_STS 0x9F
541#define TWL4030_USB_CARKIT_SM_2_INT_LATCH 0xA0
542#define TWL4030_USB_CARKIT_SM_CTRL 0xA1
543#define TWL4030_USB_CARKIT_SM_CTRL_SET 0xA2
544#define TWL4030_USB_CARKIT_SM_CTRL_CLR 0xA3
545#define TWL4030_USB_CARKIT_SM_CMD 0xA4
546#define TWL4030_USB_CARKIT_SM_CMD_SET 0xA5
547#define TWL4030_USB_CARKIT_SM_CMD_CLR 0xA6
548#define TWL4030_USB_CARKIT_SM_CMD_STS 0xA7
549#define TWL4030_USB_CARKIT_SM_STATUS 0xA8
550#define TWL4030_USB_CARKIT_SM_ERR_STATUS 0xAA
551#define TWL4030_USB_CARKIT_SM_CTRL_STATE 0xAB
552#define TWL4030_USB_POWER_CTRL 0xAC
553#define TWL4030_USB_POWER_CTRL_SET 0xAD
554#define TWL4030_USB_POWER_CTRL_CLR 0xAE
555#define TWL4030_USB_OTHER_IFC_CTRL2 0xAF
556#define TWL4030_USB_OTHER_IFC_CTRL2_SET 0xB0
557#define TWL4030_USB_OTHER_IFC_CTRL2_CLR 0xB1
558#define TWL4030_USB_REG_CTRL_EN 0xB2
559#define TWL4030_USB_REG_CTRL_EN_SET 0xB3
560#define TWL4030_USB_REG_CTRL_EN_CLR 0xB4
561#define TWL4030_USB_REG_CTRL_ERROR 0xB5
562#define TWL4030_USB_OTHER_FUNC_CTRL2 0xB8
563#define TWL4030_USB_OTHER_FUNC_CTRL2_SET 0xB9
564#define TWL4030_USB_OTHER_FUNC_CTRL2_CLR 0xBA
565#define TWL4030_USB_CARKIT_ANA_CTRL 0xBB
566#define TWL4030_USB_CARKIT_ANA_CTRL_SET 0xBC
567#define TWL4030_USB_CARKIT_ANA_CTRL_CLR 0xBD
568#define TWL4030_USB_VBUS_DEBOUNCE 0xC0
569#define TWL4030_USB_ID_DEBOUNCE 0xC1
570#define TWL4030_USB_TPH_DP_CON_MIN 0xC2
571#define TWL4030_USB_TPH_DP_CON_MAX 0xC3
572#define TWL4030_USB_TCR_DP_CON_MIN 0xC4
573#define TWL4030_USB_TCR_DP_CON_MAX 0xC5
574#define TWL4030_USB_TPH_DP_PD_SHORT 0xC6
575#define TWL4030_USB_TPH_CMD_DLY 0xC7
576#define TWL4030_USB_TPH_DET_RST 0xC8
577#define TWL4030_USB_TPH_AUD_BIAS 0xC9
578#define TWL4030_USB_TCR_UART_DET_MIN 0xCA
579#define TWL4030_USB_TCR_UART_DET_MAX 0xCB
580#define TWL4030_USB_TPH_ID_INT_PW 0xCD
581#define TWL4030_USB_TACC_ID_INT_WAIT 0xCE
582#define TWL4030_USB_TACC_ID_INT_PW 0xCF
583#define TWL4030_USB_TPH_CMD_WAIT 0xD0
584#define TWL4030_USB_TPH_ACK_WAIT 0xD1
585#define TWL4030_USB_TPH_DP_DISC_DET 0xD2
586#define TWL4030_USB_VBAT_TIMER 0xD3
587#define TWL4030_USB_CARKIT_4W_DEBUG 0xE0
588#define TWL4030_USB_CARKIT_5W_DEBUG 0xE1
589#define TWL4030_USB_PHY_PWR_CTRL 0xFD
590#define TWL4030_USB_PHY_CLK_CTRL 0xFE
591#define TWL4030_USB_PHY_CLK_CTRL_STS 0xFF
Tom Rix8966eb42009-06-28 12:52:28 -0500592
Nikita Kiryanov41b13bc2012-12-02 13:59:18 +0200593/* GPIO */
594#define TWL4030_GPIO_GPIODATAIN1 0x00
595#define TWL4030_GPIO_GPIODATAIN2 0x01
596#define TWL4030_GPIO_GPIODATAIN3 0x02
597#define TWL4030_GPIO_GPIODATADIR1 0x03
598#define TWL4030_GPIO_GPIODATADIR2 0x04
599#define TWL4030_GPIO_GPIODATADIR3 0x05
600#define TWL4030_GPIO_GPIODATAOUT1 0x06
601#define TWL4030_GPIO_GPIODATAOUT2 0x07
602#define TWL4030_GPIO_GPIODATAOUT3 0x08
603#define TWL4030_GPIO_CLEARGPIODATAOUT1 0x09
604#define TWL4030_GPIO_CLEARGPIODATAOUT2 0x0A
605#define TWL4030_GPIO_CLEARGPIODATAOUT3 0x0B
606#define TWL4030_GPIO_SETGPIODATAOUT1 0x0C
607#define TWL4030_GPIO_SETGPIODATAOUT2 0x0D
608#define TWL4030_GPIO_SETGPIODATAOUT3 0x0E
609#define TWL4030_GPIO_GPIO_DEBEN1 0x0F
610#define TWL4030_GPIO_GPIO_DEBEN2 0x10
611#define TWL4030_GPIO_GPIO_DEBEN3 0x11
612#define TWL4030_GPIO_GPIO_CTRL 0x12
613#define TWL4030_GPIO_GPIOPUPDCTR1 0x13
614#define TWL4030_GPIO_GPIOPUPDCTR2 0x14
615#define TWL4030_GPIO_GPIOPUPDCTR3 0x15
616#define TWL4030_GPIO_GPIOPUPDCTR4 0x16
617#define TWL4030_GPIO_GPIOPUPDCTR5 0x17
618#define TWL4030_GPIO_GPIO_ISR1A 0x19
619#define TWL4030_GPIO_GPIO_ISR2A 0x1A
620#define TWL4030_GPIO_GPIO_ISR3A 0x1B
621#define TWL4030_GPIO_GPIO_IMR1A 0x1C
622#define TWL4030_GPIO_GPIO_IMR2A 0x1D
623#define TWL4030_GPIO_GPIO_IMR3A 0x1E
624#define TWL4030_GPIO_GPIO_ISR1B 0x1F
625#define TWL4030_GPIO_GPIO_ISR2B 0x20
626#define TWL4030_GPIO_GPIO_ISR3B 0x21
627#define TWL4030_GPIO_GPIO_IMR1B 0x22
628#define TWL4030_GPIO_GPIO_IMR2B 0x23
629#define TWL4030_GPIO_GPIO_IMR3B 0x24
630#define TWL4030_GPIO_GPIO_EDR1 0x28
631#define TWL4030_GPIO_GPIO_EDR2 0x29
632#define TWL4030_GPIO_GPIO_EDR3 0x2A
633#define TWL4030_GPIO_GPIO_EDR4 0x2B
634#define TWL4030_GPIO_GPIO_EDR5 0x2C
635#define TWL4030_GPIO_GPIO_SIH_CTRL 0x2D
636
Tom Rix8966eb42009-06-28 12:52:28 -0500637/*
638 * Convience functions to read and write from TWL4030
639 *
640 * chip_no is the i2c address, it must be one of the chip addresses
641 * defined at the top of this file with the prefix TWL4030_CHIP_
642 * examples are TWL4030_CHIP_PM_RECEIVER and TWL4030_CHIP_KEYPAD
643 *
644 * val is the data either written to or read from the twl4030
645 *
646 * reg is the register to act on, it must be one of the defines
647 * above and with the format TWL4030_<chip suffix>_<register name>
648 * examples are TWL4030_PM_RECEIVER_VMMC1_DEV_GRP and
649 * TWL4030_LED_LEDEN.
650 */
Igor Opaniuk2147a162021-02-09 13:52:45 +0200651#if !CONFIG_IS_ENABLED(DM_I2C)
Nishanth Menon0208aaf2013-03-26 05:20:49 +0000652static inline int twl4030_i2c_write_u8(u8 chip_no, u8 reg, u8 val)
Tom Rix8966eb42009-06-28 12:52:28 -0500653{
654 return i2c_write(chip_no, reg, 1, &val, 1);
655}
656
Pali Rohár4fcc0842020-10-26 22:36:15 +0100657static inline int twl4030_i2c_read(u8 chip_no, u8 reg, u8 *val, int len)
Tom Rix8966eb42009-06-28 12:52:28 -0500658{
Pali Rohár4fcc0842020-10-26 22:36:15 +0100659 return i2c_read(chip_no, reg, 1, val, len);
Tom Rix8966eb42009-06-28 12:52:28 -0500660}
Jean-Jacques Hiblotfb1b7712018-12-07 14:50:46 +0100661#else
662int twl4030_i2c_write_u8(u8 chip_no, u8 reg, u8 val);
Pali Rohár4fcc0842020-10-26 22:36:15 +0100663int twl4030_i2c_read(u8 chip_no, u8 reg, u8 *val, int len);
Jean-Jacques Hiblotfb1b7712018-12-07 14:50:46 +0100664#endif
Pali Rohár4fcc0842020-10-26 22:36:15 +0100665
666static inline int twl4030_i2c_read_u8(u8 chip_no, u8 reg, u8 *val)
667{
668 return twl4030_i2c_read(chip_no, reg, val, 1);
669}
670
Tom Rix2c155132009-06-28 12:52:30 -0500671/*
672 * Power
673 */
674
Tom Rixcd782632009-06-28 12:52:29 -0500675/* For hardware resetting */
676void twl4030_power_reset_init(void);
Paul Kocialkowski6dc443e2015-07-20 15:17:07 +0200677/* For power off */
678void twl4030_power_off(void);
Steve Sakoman5a0a82f2010-08-10 12:58:39 -0700679/* For setting device group and voltage */
680void twl4030_pmrecv_vsel_cfg(u8 vsel_reg, u8 vsel_val,
681 u8 dev_grp, u8 dev_grp_sel);
Tom Rix2c155132009-06-28 12:52:30 -0500682/* For initializing power device */
683void twl4030_power_init(void);
Tom Rixfccc0fc2009-06-28 12:52:31 -0500684/* For initializing mmc power */
Paul Kocialkowskif3e85e42014-11-08 20:55:46 +0100685void twl4030_power_mmc_init(int dev_index);
Tom Rixfccc0fc2009-06-28 12:52:31 -0500686
Tom Rix2c155132009-06-28 12:52:30 -0500687/*
Paul Kocialkowski7d5ac912015-07-20 15:17:08 +0200688 * Input
689 */
690
691int twl4030_input_power_button(void);
692int twl4030_input_charger(void);
693int twl4030_input_usb(void);
694
Paul Kocialkowskia4c8bbb2015-07-20 15:17:09 +0200695int twl4030_keypad_scan(unsigned char *matrix);
696int twl4030_keypad_key(unsigned char *matrix, u8 c, u8 r);
697
Paul Kocialkowski7d5ac912015-07-20 15:17:08 +0200698/*
Tom Rix2c155132009-06-28 12:52:30 -0500699 * LED
700 */
Grazvydas Ignotasead39d72009-12-10 17:10:21 +0200701void twl4030_led_init(unsigned char ledon_mask);
Tom Rixcd782632009-06-28 12:52:29 -0500702
Tom Rixbffbb2a2009-10-31 12:37:40 -0500703/*
704 * USB
705 */
706int twl4030_usb_ulpi_init(void);
707
Tom Rix8966eb42009-06-28 12:52:28 -0500708#endif /* TWL4030_H */