blob: 20b2a70122394252b6f445c7e36c08e6fc1a4735 [file] [log] [blame]
Suman Anna900349b2022-05-25 13:38:47 +05301// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Board specific initialization for AM62x platforms
4 *
5 * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
6 * Suman Anna <s-anna@ti.com>
7 *
8 */
9
Nikhil M Jaind5f563c2023-01-31 15:35:19 +053010#include <env.h>
Suman Anna900349b2022-05-25 13:38:47 +053011#include <spl.h>
Nikhil M Jaind5f563c2023-01-31 15:35:19 +053012#include <video.h>
13#include <splash.h>
Georgi Vlaev4c092bb2022-06-14 17:45:33 +030014#include <k3-ddrss.h>
Suman Anna900349b2022-05-25 13:38:47 +053015#include <fdt_support.h>
Nikhil M Jaind5f563c2023-01-31 15:35:19 +053016#include <asm/io.h>
Suman Anna900349b2022-05-25 13:38:47 +053017#include <asm/arch/hardware.h>
18#include <asm/arch/sys_proto.h>
Nikhil M Jaind5f563c2023-01-31 15:35:19 +053019#include <dm/uclass.h>
Suman Anna900349b2022-05-25 13:38:47 +053020
21DECLARE_GLOBAL_DATA_PTR;
22
Nikhil M Jaind5f563c2023-01-31 15:35:19 +053023#ifdef CONFIG_SPLASH_SCREEN
24static struct splash_location default_splash_locations[] = {
25 {
26 .name = "mmc",
27 .storage = SPLASH_STORAGE_MMC,
28 .flags = SPLASH_STORAGE_FS,
29 .devpart = "1:1",
30 },
31};
32
33int splash_screen_prepare(void)
34{
35 return splash_source_load(default_splash_locations,
36 ARRAY_SIZE(default_splash_locations));
37}
38#endif
39
Suman Anna900349b2022-05-25 13:38:47 +053040int board_init(void)
41{
42 return 0;
43}
44
45int dram_init(void)
46{
Georgi Vlaev249e9f32022-06-14 17:45:32 +030047 return fdtdec_setup_mem_size_base();
Suman Anna900349b2022-05-25 13:38:47 +053048}
49
50int dram_init_banksize(void)
51{
Georgi Vlaev249e9f32022-06-14 17:45:32 +030052 return fdtdec_setup_memory_banksize();
Suman Anna900349b2022-05-25 13:38:47 +053053}
Georgi Vlaev4c092bb2022-06-14 17:45:33 +030054
55#if defined(CONFIG_SPL_BUILD)
56#if defined(CONFIG_K3_AM64_DDRSS)
57static void fixup_ddr_driver_for_ecc(struct spl_image_info *spl_image)
58{
59 struct udevice *dev;
60 int ret;
61
62 dram_init_banksize();
63
64 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
65 if (ret)
66 panic("Cannot get RAM device for ddr size fixup: %d\n", ret);
67
68 ret = k3_ddrss_ddr_fdt_fixup(dev, spl_image->fdt_addr, gd->bd);
69 if (ret)
70 printf("Error fixing up ddr node for ECC use! %d\n", ret);
71}
72#else
73static void fixup_memory_node(struct spl_image_info *spl_image)
74{
75 u64 start[CONFIG_NR_DRAM_BANKS];
76 u64 size[CONFIG_NR_DRAM_BANKS];
77 int bank;
78 int ret;
79
80 dram_init();
81 dram_init_banksize();
82
83 for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
84 start[bank] = gd->bd->bi_dram[bank].start;
85 size[bank] = gd->bd->bi_dram[bank].size;
86 }
87
88 /* dram_init functions use SPL fdt, and we must fixup u-boot fdt */
89 ret = fdt_fixup_memory_banks(spl_image->fdt_addr, start, size,
90 CONFIG_NR_DRAM_BANKS);
91 if (ret)
92 printf("Error fixing up memory node! %d\n", ret);
93}
94#endif
95
96void spl_perform_fixups(struct spl_image_info *spl_image)
97{
98#if defined(CONFIG_K3_AM64_DDRSS)
99 fixup_ddr_driver_for_ecc(spl_image);
100#else
101 fixup_memory_node(spl_image);
102#endif
103}
104#endif