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Srikanth Srinivasanfeb78382009-04-03 15:36:13 -05001/*
ramneek mehresh3d7506f2012-04-18 19:39:53 +00002 * Copyright 2007-2012 Freescale Semiconductor, Inc.
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -05003 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02004 * SPDX-License-Identifier: GPL-2.0+
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -05005 */
6
7#include <common.h>
8#include <command.h>
9#include <pci.h>
10#include <asm/processor.h>
11#include <asm/mmu.h>
12#include <asm/cache.h>
13#include <asm/immap_85xx.h>
14#include <asm/fsl_pci.h>
York Sun5614e712013-09-30 09:22:09 -070015#include <fsl_ddr_sdram.h>
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -050016#include <asm/io.h>
Kumar Gala5d27e022010-12-15 04:55:20 -060017#include <asm/fsl_serdes.h>
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -050018#include <miiphy.h>
19#include <libfdt.h>
20#include <fdt_support.h>
Andy Fleming063c1262011-04-08 02:10:54 -050021#include <fsl_mdio.h>
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -050022#include <tsec.h>
23#include <asm/fsl_law.h>
Roy Zang29c35182009-06-30 13:56:23 +080024#include <netdev.h>
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -050025
Timur Tabi5a469602010-04-01 10:49:42 -050026#include "../common/ngpixis.h"
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -050027#include "../common/sgmii_riser.h"
28
29DECLARE_GLOBAL_DATA_PTR;
30
Jerry Huang9c4d8762011-01-24 17:09:53 +000031int board_early_init_f(void)
32{
33#ifdef CONFIG_MMC
34 ccsr_gur_t *gur = (ccsr_gur_t *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
35
36 setbits_be32(&gur->pmuxcr,
37 (MPC85xx_PMUXCR_SDHC_CD |
38 MPC85xx_PMUXCR_SDHC_WP));
39#endif
40
41 return 0;
42}
43
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -050044int checkboard(void)
45{
Timur Tabi5a469602010-04-01 10:49:42 -050046 u8 sw;
Kumar Gala6bb5b412009-07-14 22:42:01 -050047
Timur Tabi5d065c32012-03-15 11:42:27 +000048 printf("Board: P2020DS Sys ID: 0x%02x, "
49 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
Timur Tabi5a469602010-04-01 10:49:42 -050050 in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
Kumar Gala6bb5b412009-07-14 22:42:01 -050051
Timur Tabi5a469602010-04-01 10:49:42 -050052 sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
53 sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT;
54
55 if (sw < 0x8)
56 /* The lower two bits are the actual vbank number */
57 printf("vBank: %d\n", sw & 3);
58 else
59 puts("Promjet\n");
Kumar Gala6bb5b412009-07-14 22:42:01 -050060
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -050061 return 0;
62}
63
york394c46c2010-07-02 22:25:58 +000064#if !defined(CONFIG_DDR_SPD)
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -050065/*
66 * Fixed sdram init -- doesn't use serial presence detect.
67 */
68
69phys_size_t fixed_sdram(void)
70{
York Sun9a17eb52013-11-18 10:29:32 -080071 struct ccsr_ddr __iomem *ddr =
72 (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -050073 uint d_init;
74
75 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
76 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
77 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
78 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
79 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
80 ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTRL;
81 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
82 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
83 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
84 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
85 ddr->ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL;
86 ddr->ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL;
87 ddr->ddr_cdr1 = CONFIG_SYS_DDR_CDR1;
88 ddr->timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4;
89 ddr->timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5;
90
91 if (!strcmp("performance", getenv("perf_mode"))) {
92 /* Performance Mode Values */
93
94 ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG_PERF;
95 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS_PERF;
96 ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS_PERF;
97 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_PERF;
98 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_PERF;
99
100 asm("sync;isync");
101
102 udelay(500);
103
104 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL_PERF;
105 } else {
106 /* Stable Mode Values */
107
108 ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
109 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
110 ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
111 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
112 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
113
114 /* ECC will be assumed in stable mode */
115 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
116 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
117 ddr->err_sbe = CONFIG_SYS_DDR_SBE;
118
119 asm("sync;isync");
120
121 udelay(500);
122
123 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
124 }
125
126#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
127 d_init = 1;
128 debug("DDR - 1st controller: memory initializing\n");
129 /*
130 * Poll until memory is initialized.
131 * 512 Meg at 400 might hit this 200 times or so.
132 */
133 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
134 udelay(1000);
135 debug("DDR: memory initialized\n\n");
136 asm("sync; isync");
137 udelay(500);
138#endif
139
Becky Bruce38dba0c2010-12-17 17:17:56 -0600140 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
141 CONFIG_SYS_SDRAM_SIZE * 1024 * 1024,
142 LAW_TRGT_IF_DDR) < 0) {
143 printf("ERROR setting Local Access Windows for DDR\n");
144 return 0;
145 };
146
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500147 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
148}
149
150#endif
151
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500152#ifdef CONFIG_PCI
153void pci_init_board(void)
154{
Kumar Gala4d5723d2010-12-17 07:01:00 -0600155 fsl_pcie_init_board(0);
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500156}
157#endif
158
159int board_early_init_r(void)
160{
161 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
York Sun9d045682014-06-24 21:16:20 -0700162 int flash_esel = find_tlb_idx((void *)flashbase, 1);
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500163
164 /*
165 * Remap Boot flash + PROMJET region to caching-inhibited
166 * so that flash can be erased properly.
167 */
168
169 /* Flush d-cache and invalidate i-cache of any FLASH data */
170 flush_dcache();
171 invalidate_icache();
172
York Sun9d045682014-06-24 21:16:20 -0700173 if (flash_esel == -1) {
174 /* very unlikely unless something is messed up */
175 puts("Error: Could not find TLB for FLASH BASE\n");
176 flash_esel = 2; /* give our best effort to continue */
177 } else {
178 /* invalidate existing TLB entry for flash + promjet */
179 disable_tlb(flash_esel);
180 }
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500181
182 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
183 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
184 0, flash_esel, BOOKE_PAGESZ_256M, 1);
185
186 return 0;
187}
188
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500189#ifdef CONFIG_TSEC_ENET
190int board_eth_init(bd_t *bis)
191{
Andy Fleming063c1262011-04-08 02:10:54 -0500192 struct fsl_pq_mdio_info mdio_info;
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500193 struct tsec_info_struct tsec_info[4];
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500194 int num = 0;
195
196#ifdef CONFIG_TSEC1
197 SET_STD_TSEC_INFO(tsec_info[num], 1);
198 num++;
199#endif
200#ifdef CONFIG_TSEC2
201 SET_STD_TSEC_INFO(tsec_info[num], 2);
Kumar Gala058d7dc2010-12-16 14:28:06 -0600202 if (is_serdes_configured(SGMII_TSEC2)) {
203 puts("eTSEC2 is in sgmii mode.\n");
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500204 tsec_info[num].flags |= TSEC_SGMII;
Kumar Gala058d7dc2010-12-16 14:28:06 -0600205 }
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500206 num++;
207#endif
208#ifdef CONFIG_TSEC3
209 SET_STD_TSEC_INFO(tsec_info[num], 3);
Kumar Gala058d7dc2010-12-16 14:28:06 -0600210 if (is_serdes_configured(SGMII_TSEC3)) {
211 puts("eTSEC3 is in sgmii mode.\n");
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500212 tsec_info[num].flags |= TSEC_SGMII;
Kumar Gala058d7dc2010-12-16 14:28:06 -0600213}
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500214 num++;
215#endif
216
217 if (!num) {
218 printf("No TSECs initialized\n");
219
220 return 0;
221 }
222
223#ifdef CONFIG_FSL_SGMII_RISER
224 fsl_sgmii_riser_init(tsec_info, num);
225#endif
226
Andy Fleming063c1262011-04-08 02:10:54 -0500227 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
228 mdio_info.name = DEFAULT_MII_NAME;
229
230 fsl_pq_mdio_init(bis, &mdio_info);
231
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500232 tsec_eth_init(bis, tsec_info, num);
233
Roy Zang29c35182009-06-30 13:56:23 +0800234 return pci_eth_init(bis);
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500235}
236#endif
237
238#if defined(CONFIG_OF_BOARD_SETUP)
239void ft_board_setup(void *blob, bd_t *bd)
240{
241 phys_addr_t base;
242 phys_size_t size;
243
244 ft_cpu_setup(blob, bd);
245
246 base = getenv_bootm_low();
247 size = getenv_bootm_size();
248
249 fdt_fixup_memory(blob, (u64)base, (u64)size);
250
ramneek mehresh3d7506f2012-04-18 19:39:53 +0000251#ifdef CONFIG_HAS_FSL_DR_USB
252 fdt_fixup_dr_usb(blob, bd);
253#endif
254
Kumar Gala6525d512010-07-08 22:37:44 -0500255 FT_FSL_PCI_SETUP;
256
Srikanth Srinivasanfeb78382009-04-03 15:36:13 -0500257#ifdef CONFIG_FSL_SGMII_RISER
258 fsl_sgmii_riser_fdt_fixup(blob);
259#endif
260}
261#endif