blob: 24933473fa059e9279f8189bfb212c43bf7e7e75 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Stefan Roese19fc2ea2014-10-22 12:13:14 +02002/*
3 * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs.
4 *
5 * U-Boot version:
Stefan Roesee3b9c982015-11-19 07:46:15 +01006 * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
Stefan Roese19fc2ea2014-10-22 12:13:14 +02007 *
8 * Based on the Linux version which is:
9 * Copyright (C) 2012 Marvell
10 *
11 * Rami Rosen <rosenr@marvell.com>
12 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Stefan Roese19fc2ea2014-10-22 12:13:14 +020013 */
14
15#include <common.h>
Simon Glass1eb69ae2019-11-14 12:57:39 -070016#include <cpu_func.h>
Stefan Roesee3b9c982015-11-19 07:46:15 +010017#include <dm.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060018#include <log.h>
Stefan Roese19fc2ea2014-10-22 12:13:14 +020019#include <net.h>
20#include <netdev.h>
21#include <config.h>
22#include <malloc.h>
Simon Glass90526e92020-05-10 11:39:56 -060023#include <asm/cache.h>
Simon Glass401d1c42020-10-30 21:38:53 -060024#include <asm/global_data.h>
Stefan Roese19fc2ea2014-10-22 12:13:14 +020025#include <asm/io.h>
Simon Glass336d4612020-02-03 07:36:16 -070026#include <dm/device_compat.h>
Simon Glass61b29b82020-02-03 07:36:15 -070027#include <dm/devres.h>
Simon Glasscd93d622020-05-10 11:40:13 -060028#include <linux/bitops.h>
Simon Glasseb41d8a2020-05-10 11:40:08 -060029#include <linux/bug.h>
Simon Glassc05ed002020-05-10 11:40:11 -060030#include <linux/delay.h>
Masahiro Yamada1221ce42016-09-21 11:28:55 +090031#include <linux/errno.h>
Stefan Roese19fc2ea2014-10-22 12:13:14 +020032#include <phy.h>
33#include <miiphy.h>
34#include <watchdog.h>
35#include <asm/arch/cpu.h>
36#include <asm/arch/soc.h>
37#include <linux/compat.h>
38#include <linux/mbus.h>
Aditya Prayoga18bfc8f2018-12-05 00:39:23 +080039#include <asm-generic/gpio.h>
Stefan Roese19fc2ea2014-10-22 12:13:14 +020040
Stefan Roesee3b9c982015-11-19 07:46:15 +010041DECLARE_GLOBAL_DATA_PTR;
42
Marek Behún31f4ccc2022-04-27 12:41:57 +020043#define MVNETA_NR_CPUS 1
Stefan Roese19fc2ea2014-10-22 12:13:14 +020044#define ETH_HLEN 14 /* Total octets in header */
45
46/* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch) */
47#define WRAP (2 + ETH_HLEN + 4 + 32)
48#define MTU 1500
49#define RX_BUFFER_SIZE (ALIGN(MTU + WRAP, ARCH_DMA_MINALIGN))
50
51#define MVNETA_SMI_TIMEOUT 10000
52
53/* Registers */
54#define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2))
55#define MVNETA_RXQ_HW_BUF_ALLOC BIT(1)
56#define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8)
57#define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8)
58#define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2))
59#define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16)
60#define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2))
61#define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2))
62#define MVNETA_RXQ_BUF_SIZE_SHIFT 19
63#define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19)
64#define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2))
65#define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff
66#define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2))
67#define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16
68#define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255
69#define MVNETA_PORT_RX_RESET 0x1cc0
70#define MVNETA_PORT_RX_DMA_RESET BIT(0)
71#define MVNETA_PHY_ADDR 0x2000
72#define MVNETA_PHY_ADDR_MASK 0x1f
73#define MVNETA_SMI 0x2004
74#define MVNETA_PHY_REG_MASK 0x1f
75/* SMI register fields */
76#define MVNETA_SMI_DATA_OFFS 0 /* Data */
77#define MVNETA_SMI_DATA_MASK (0xffff << MVNETA_SMI_DATA_OFFS)
78#define MVNETA_SMI_DEV_ADDR_OFFS 16 /* PHY device address */
79#define MVNETA_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr*/
80#define MVNETA_SMI_OPCODE_OFFS 26 /* Write/Read opcode */
81#define MVNETA_SMI_OPCODE_READ (1 << MVNETA_SMI_OPCODE_OFFS)
82#define MVNETA_SMI_READ_VALID (1 << 27) /* Read Valid */
83#define MVNETA_SMI_BUSY (1 << 28) /* Busy */
84#define MVNETA_MBUS_RETRY 0x2010
85#define MVNETA_UNIT_INTR_CAUSE 0x2080
86#define MVNETA_UNIT_CONTROL 0x20B0
87#define MVNETA_PHY_POLLING_ENABLE BIT(1)
88#define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3))
89#define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3))
90#define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2))
Stefan Roese544eefe2016-05-19 17:46:36 +020091#define MVNETA_WIN_SIZE_MASK (0xffff0000)
Stefan Roese19fc2ea2014-10-22 12:13:14 +020092#define MVNETA_BASE_ADDR_ENABLE 0x2290
Stefan Roese544eefe2016-05-19 17:46:36 +020093#define MVNETA_BASE_ADDR_ENABLE_BIT 0x1
Chris Packhamaaee5722022-11-05 17:23:56 +130094#define MVNETA_AC5_CNM_DDR_TARGET 0x2
95#define MVNETA_AC5_CNM_DDR_ATTR 0xb
Stefan Roese544eefe2016-05-19 17:46:36 +020096#define MVNETA_PORT_ACCESS_PROTECT 0x2294
97#define MVNETA_PORT_ACCESS_PROTECT_WIN0_RW 0x3
Stefan Roese19fc2ea2014-10-22 12:13:14 +020098#define MVNETA_PORT_CONFIG 0x2400
99#define MVNETA_UNI_PROMISC_MODE BIT(0)
100#define MVNETA_DEF_RXQ(q) ((q) << 1)
101#define MVNETA_DEF_RXQ_ARP(q) ((q) << 4)
102#define MVNETA_TX_UNSET_ERR_SUM BIT(12)
103#define MVNETA_DEF_RXQ_TCP(q) ((q) << 16)
104#define MVNETA_DEF_RXQ_UDP(q) ((q) << 19)
105#define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22)
106#define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25)
107#define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \
108 MVNETA_DEF_RXQ_ARP(q) | \
109 MVNETA_DEF_RXQ_TCP(q) | \
110 MVNETA_DEF_RXQ_UDP(q) | \
111 MVNETA_DEF_RXQ_BPDU(q) | \
112 MVNETA_TX_UNSET_ERR_SUM | \
113 MVNETA_RX_CSUM_WITH_PSEUDO_HDR)
114#define MVNETA_PORT_CONFIG_EXTEND 0x2404
115#define MVNETA_MAC_ADDR_LOW 0x2414
116#define MVNETA_MAC_ADDR_HIGH 0x2418
117#define MVNETA_SDMA_CONFIG 0x241c
118#define MVNETA_SDMA_BRST_SIZE_16 4
119#define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1)
120#define MVNETA_RX_NO_DATA_SWAP BIT(4)
121#define MVNETA_TX_NO_DATA_SWAP BIT(5)
122#define MVNETA_DESC_SWAP BIT(6)
123#define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22)
124#define MVNETA_PORT_STATUS 0x2444
125#define MVNETA_TX_IN_PRGRS BIT(1)
126#define MVNETA_TX_FIFO_EMPTY BIT(8)
127#define MVNETA_RX_MIN_FRAME_SIZE 0x247c
128#define MVNETA_SERDES_CFG 0x24A0
129#define MVNETA_SGMII_SERDES_PROTO 0x0cc7
130#define MVNETA_QSGMII_SERDES_PROTO 0x0667
131#define MVNETA_TYPE_PRIO 0x24bc
132#define MVNETA_FORCE_UNI BIT(21)
133#define MVNETA_TXQ_CMD_1 0x24e4
134#define MVNETA_TXQ_CMD 0x2448
135#define MVNETA_TXQ_DISABLE_SHIFT 8
136#define MVNETA_TXQ_ENABLE_MASK 0x000000ff
137#define MVNETA_ACC_MODE 0x2500
138#define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2))
139#define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff
140#define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00
141#define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2))
142
143/* Exception Interrupt Port/Queue Cause register */
144
145#define MVNETA_INTR_NEW_CAUSE 0x25a0
146#define MVNETA_INTR_NEW_MASK 0x25a4
147
148/* bits 0..7 = TXQ SENT, one bit per queue.
149 * bits 8..15 = RXQ OCCUP, one bit per queue.
150 * bits 16..23 = RXQ FREE, one bit per queue.
151 * bit 29 = OLD_REG_SUM, see old reg ?
152 * bit 30 = TX_ERR_SUM, one bit for 4 ports
153 * bit 31 = MISC_SUM, one bit for 4 ports
154 */
155#define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0)
156#define MVNETA_TX_INTR_MASK_ALL (0xff << 0)
157#define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8)
158#define MVNETA_RX_INTR_MASK_ALL (0xff << 8)
159
160#define MVNETA_INTR_OLD_CAUSE 0x25a8
161#define MVNETA_INTR_OLD_MASK 0x25ac
162
163/* Data Path Port/Queue Cause Register */
164#define MVNETA_INTR_MISC_CAUSE 0x25b0
165#define MVNETA_INTR_MISC_MASK 0x25b4
166#define MVNETA_INTR_ENABLE 0x25b8
167
168#define MVNETA_RXQ_CMD 0x2680
169#define MVNETA_RXQ_DISABLE_SHIFT 8
170#define MVNETA_RXQ_ENABLE_MASK 0x000000ff
171#define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4))
172#define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4))
173#define MVNETA_GMAC_CTRL_0 0x2c00
174#define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2
175#define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc
176#define MVNETA_GMAC0_PORT_ENABLE BIT(0)
177#define MVNETA_GMAC_CTRL_2 0x2c08
178#define MVNETA_GMAC2_PCS_ENABLE BIT(3)
179#define MVNETA_GMAC2_PORT_RGMII BIT(4)
180#define MVNETA_GMAC2_PORT_RESET BIT(6)
181#define MVNETA_GMAC_STATUS 0x2c10
182#define MVNETA_GMAC_LINK_UP BIT(0)
183#define MVNETA_GMAC_SPEED_1000 BIT(1)
184#define MVNETA_GMAC_SPEED_100 BIT(2)
185#define MVNETA_GMAC_FULL_DUPLEX BIT(3)
186#define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4)
187#define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5)
188#define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6)
189#define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7)
190#define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c
191#define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0)
192#define MVNETA_GMAC_FORCE_LINK_PASS BIT(1)
Konstantin Porotchkin278d30c2017-02-16 13:52:28 +0200193#define MVNETA_GMAC_IB_BYPASS_AN_EN BIT(3)
Stefan Roese19fc2ea2014-10-22 12:13:14 +0200194#define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5)
195#define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6)
196#define MVNETA_GMAC_AN_SPEED_EN BIT(7)
Konstantin Porotchkin278d30c2017-02-16 13:52:28 +0200197#define MVNETA_GMAC_SET_FC_EN BIT(8)
198#define MVNETA_GMAC_ADVERT_FC_EN BIT(9)
Stefan Roese19fc2ea2014-10-22 12:13:14 +0200199#define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12)
200#define MVNETA_GMAC_AN_DUPLEX_EN BIT(13)
Konstantin Porotchkin278d30c2017-02-16 13:52:28 +0200201#define MVNETA_GMAC_SAMPLE_TX_CFG_EN BIT(15)
Stefan Roese19fc2ea2014-10-22 12:13:14 +0200202#define MVNETA_MIB_COUNTERS_BASE 0x3080
203#define MVNETA_MIB_LATE_COLLISION 0x7c
204#define MVNETA_DA_FILT_SPEC_MCAST 0x3400
205#define MVNETA_DA_FILT_OTH_MCAST 0x3500
206#define MVNETA_DA_FILT_UCAST_BASE 0x3600
207#define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2))
208#define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2))
209#define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000
210#define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16)
211#define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2))
212#define MVNETA_TXQ_DEC_SENT_SHIFT 16
213#define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2))
214#define MVNETA_TXQ_SENT_DESC_SHIFT 16
215#define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000
216#define MVNETA_PORT_TX_RESET 0x3cf0
217#define MVNETA_PORT_TX_DMA_RESET BIT(0)
218#define MVNETA_TX_MTU 0x3e0c
219#define MVNETA_TX_TOKEN_SIZE 0x3e14
220#define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff
221#define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2))
222#define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff
223
224/* Descriptor ring Macros */
225#define MVNETA_QUEUE_NEXT_DESC(q, index) \
226 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
227
228/* Various constants */
229
230/* Coalescing */
231#define MVNETA_TXDONE_COAL_PKTS 16
232#define MVNETA_RX_COAL_PKTS 32
233#define MVNETA_RX_COAL_USEC 100
234
235/* The two bytes Marvell header. Either contains a special value used
236 * by Marvell switches when a specific hardware mode is enabled (not
237 * supported by this driver) or is filled automatically by zeroes on
238 * the RX side. Those two bytes being at the front of the Ethernet
239 * header, they allow to have the IP header aligned on a 4 bytes
240 * boundary automatically: the hardware skips those two bytes on its
241 * own.
242 */
243#define MVNETA_MH_SIZE 2
244
245#define MVNETA_VLAN_TAG_LEN 4
246
247#define MVNETA_CPU_D_CACHE_LINE_SIZE 32
248#define MVNETA_TX_CSUM_MAX_SIZE 9800
249#define MVNETA_ACC_MODE_EXT 1
250
251/* Timeout constants */
252#define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000
253#define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000
254#define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000
255
256#define MVNETA_TX_MTU_MAX 0x3ffff
257
258/* Max number of Rx descriptors */
259#define MVNETA_MAX_RXD 16
260
261/* Max number of Tx descriptors */
262#define MVNETA_MAX_TXD 16
263
264/* descriptor aligned size */
265#define MVNETA_DESC_ALIGNED_SIZE 32
266
267struct mvneta_port {
268 void __iomem *base;
269 struct mvneta_rx_queue *rxqs;
270 struct mvneta_tx_queue *txqs;
271
272 u8 mcast_count[256];
273 u16 tx_ring_size;
274 u16 rx_ring_size;
275
276 phy_interface_t phy_interface;
277 unsigned int link;
278 unsigned int duplex;
279 unsigned int speed;
280
281 int init;
Stefan Roese19fc2ea2014-10-22 12:13:14 +0200282 struct phy_device *phydev;
Simon Glassbcee8d62019-12-06 21:41:35 -0700283#if CONFIG_IS_ENABLED(DM_GPIO)
Aditya Prayoga18bfc8f2018-12-05 00:39:23 +0800284 struct gpio_desc phy_reset_gpio;
Robert Marko2b7beb92022-03-24 10:57:37 +0100285 struct gpio_desc sfp_tx_disable_gpio;
Aditya Prayoga18bfc8f2018-12-05 00:39:23 +0800286#endif
Chris Packhamaaee5722022-11-05 17:23:56 +1300287
288 uintptr_t dma_base; /* base address for DMA address decoding */
Stefan Roese19fc2ea2014-10-22 12:13:14 +0200289};
290
291/* The mvneta_tx_desc and mvneta_rx_desc structures describe the
292 * layout of the transmit and reception DMA descriptors, and their
293 * layout is therefore defined by the hardware design
294 */
295
296#define MVNETA_TX_L3_OFF_SHIFT 0
297#define MVNETA_TX_IP_HLEN_SHIFT 8
298#define MVNETA_TX_L4_UDP BIT(16)
299#define MVNETA_TX_L3_IP6 BIT(17)
300#define MVNETA_TXD_IP_CSUM BIT(18)
301#define MVNETA_TXD_Z_PAD BIT(19)
302#define MVNETA_TXD_L_DESC BIT(20)
303#define MVNETA_TXD_F_DESC BIT(21)
304#define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \
305 MVNETA_TXD_L_DESC | \
306 MVNETA_TXD_F_DESC)
307#define MVNETA_TX_L4_CSUM_FULL BIT(30)
308#define MVNETA_TX_L4_CSUM_NOT BIT(31)
309
310#define MVNETA_RXD_ERR_CRC 0x0
311#define MVNETA_RXD_ERR_SUMMARY BIT(16)
312#define MVNETA_RXD_ERR_OVERRUN BIT(17)
313#define MVNETA_RXD_ERR_LEN BIT(18)
314#define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18))
315#define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18))
316#define MVNETA_RXD_L3_IP4 BIT(25)
317#define MVNETA_RXD_FIRST_LAST_DESC (BIT(26) | BIT(27))
318#define MVNETA_RXD_L4_CSUM_OK BIT(30)
319
320struct mvneta_tx_desc {
321 u32 command; /* Options used by HW for packet transmitting.*/
322 u16 reserverd1; /* csum_l4 (for future use) */
323 u16 data_size; /* Data size of transmitted packet in bytes */
324 u32 buf_phys_addr; /* Physical addr of transmitted buffer */
325 u32 reserved2; /* hw_cmd - (for future use, PMT) */
326 u32 reserved3[4]; /* Reserved - (for future use) */
327};
328
329struct mvneta_rx_desc {
330 u32 status; /* Info about received packet */
331 u16 reserved1; /* pnc_info - (for future use, PnC) */
332 u16 data_size; /* Size of received packet in bytes */
333
334 u32 buf_phys_addr; /* Physical address of the buffer */
335 u32 reserved2; /* pnc_flow_id (for future use, PnC) */
336
337 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
338 u16 reserved3; /* prefetch_cmd, for future use */
339 u16 reserved4; /* csum_l4 - (for future use, PnC) */
340
341 u32 reserved5; /* pnc_extra PnC (for future use, PnC) */
342 u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */
343};
344
345struct mvneta_tx_queue {
346 /* Number of this TX queue, in the range 0-7 */
347 u8 id;
348
349 /* Number of TX DMA descriptors in the descriptor ring */
350 int size;
351
352 /* Index of last TX DMA descriptor that was inserted */
353 int txq_put_index;
354
355 /* Index of the TX DMA descriptor to be cleaned up */
356 int txq_get_index;
357
358 /* Virtual address of the TX DMA descriptors array */
359 struct mvneta_tx_desc *descs;
360
361 /* DMA address of the TX DMA descriptors array */
362 dma_addr_t descs_phys;
363
364 /* Index of the last TX DMA descriptor */
365 int last_desc;
366
367 /* Index of the next TX DMA descriptor to process */
368 int next_desc_to_proc;
369};
370
371struct mvneta_rx_queue {
372 /* rx queue number, in the range 0-7 */
373 u8 id;
374
375 /* num of rx descriptors in the rx descriptor ring */
376 int size;
377
378 /* Virtual address of the RX DMA descriptors array */
379 struct mvneta_rx_desc *descs;
380
381 /* DMA address of the RX DMA descriptors array */
382 dma_addr_t descs_phys;
383
384 /* Index of the last RX DMA descriptor */
385 int last_desc;
386
387 /* Index of the next RX DMA descriptor to process */
388 int next_desc_to_proc;
389};
390
391/* U-Boot doesn't use the queues, so set the number to 1 */
392static int rxq_number = 1;
393static int txq_number = 1;
394static int rxq_def;
395
396struct buffer_location {
397 struct mvneta_tx_desc *tx_descs;
398 struct mvneta_rx_desc *rx_descs;
399 u32 rx_buffers;
400};
401
402/*
403 * All 4 interfaces use the same global buffer, since only one interface
404 * can be enabled at once
405 */
406static struct buffer_location buffer_loc;
407
408/*
409 * Page table entries are set to 1MB, or multiples of 1MB
410 * (not < 1MB). driver uses less bd's so use 1MB bdspace.
411 */
412#define BD_SPACE (1 << 20)
413
414/* Utility/helper methods */
415
416/* Write helper method */
417static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data)
418{
419 writel(data, pp->base + offset);
420}
421
422/* Read helper method */
423static u32 mvreg_read(struct mvneta_port *pp, u32 offset)
424{
425 return readl(pp->base + offset);
426}
427
428/* Clear all MIB counters */
429static void mvneta_mib_counters_clear(struct mvneta_port *pp)
430{
431 int i;
432
433 /* Perform dummy reads from MIB counters */
434 for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4)
435 mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i));
436}
437
438/* Rx descriptors helper methods */
439
440/* Checks whether the RX descriptor having this status is both the first
441 * and the last descriptor for the RX packet. Each RX packet is currently
442 * received through a single RX descriptor, so not having each RX
443 * descriptor with its first and last bits set is an error
444 */
445static int mvneta_rxq_desc_is_first_last(u32 status)
446{
447 return (status & MVNETA_RXD_FIRST_LAST_DESC) ==
448 MVNETA_RXD_FIRST_LAST_DESC;
449}
450
451/* Add number of descriptors ready to receive new packets */
452static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp,
453 struct mvneta_rx_queue *rxq,
454 int ndescs)
455{
456 /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can
457 * be added at once
458 */
459 while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) {
460 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
461 (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX <<
462 MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
463 ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX;
464 }
465
466 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
467 (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
468}
469
470/* Get number of RX descriptors occupied by received packets */
471static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp,
472 struct mvneta_rx_queue *rxq)
473{
474 u32 val;
475
476 val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id));
477 return val & MVNETA_RXQ_OCCUPIED_ALL_MASK;
478}
479
480/* Update num of rx desc called upon return from rx path or
481 * from mvneta_rxq_drop_pkts().
482 */
483static void mvneta_rxq_desc_num_update(struct mvneta_port *pp,
484 struct mvneta_rx_queue *rxq,
485 int rx_done, int rx_filled)
486{
487 u32 val;
488
489 if ((rx_done <= 0xff) && (rx_filled <= 0xff)) {
490 val = rx_done |
491 (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT);
492 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
493 return;
494 }
495
496 /* Only 255 descriptors can be added at once */
497 while ((rx_done > 0) || (rx_filled > 0)) {
498 if (rx_done <= 0xff) {
499 val = rx_done;
500 rx_done = 0;
501 } else {
502 val = 0xff;
503 rx_done -= 0xff;
504 }
505 if (rx_filled <= 0xff) {
506 val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
507 rx_filled = 0;
508 } else {
509 val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
510 rx_filled -= 0xff;
511 }
512 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
513 }
514}
515
516/* Get pointer to next RX descriptor to be processed by SW */
517static struct mvneta_rx_desc *
518mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq)
519{
520 int rx_desc = rxq->next_desc_to_proc;
521
522 rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc);
523 return rxq->descs + rx_desc;
524}
525
526/* Tx descriptors helper methods */
527
528/* Update HW with number of TX descriptors to be sent */
529static void mvneta_txq_pend_desc_add(struct mvneta_port *pp,
530 struct mvneta_tx_queue *txq,
531 int pend_desc)
532{
533 u32 val;
534
535 /* Only 255 descriptors can be added at once ; Assume caller
Heinrich Schuchardte4691562017-08-29 18:44:37 +0200536 * process TX descriptors in quanta less than 256
Stefan Roese19fc2ea2014-10-22 12:13:14 +0200537 */
538 val = pend_desc;
539 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
540}
541
542/* Get pointer to next TX descriptor to be processed (send) by HW */
543static struct mvneta_tx_desc *
544mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq)
545{
546 int tx_desc = txq->next_desc_to_proc;
547
548 txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc);
549 return txq->descs + tx_desc;
550}
551
552/* Set rxq buf size */
553static void mvneta_rxq_buf_size_set(struct mvneta_port *pp,
554 struct mvneta_rx_queue *rxq,
555 int buf_size)
556{
557 u32 val;
558
559 val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id));
560
561 val &= ~MVNETA_RXQ_BUF_SIZE_MASK;
562 val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT);
563
564 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val);
565}
566
567/* Start the Ethernet port RX and TX activity */
568static void mvneta_port_up(struct mvneta_port *pp)
569{
570 int queue;
571 u32 q_map;
572
573 /* Enable all initialized TXs. */
574 mvneta_mib_counters_clear(pp);
575 q_map = 0;
576 for (queue = 0; queue < txq_number; queue++) {
577 struct mvneta_tx_queue *txq = &pp->txqs[queue];
578 if (txq->descs != NULL)
579 q_map |= (1 << queue);
580 }
581 mvreg_write(pp, MVNETA_TXQ_CMD, q_map);
582
583 /* Enable all initialized RXQs. */
584 q_map = 0;
585 for (queue = 0; queue < rxq_number; queue++) {
586 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
587 if (rxq->descs != NULL)
588 q_map |= (1 << queue);
589 }
590 mvreg_write(pp, MVNETA_RXQ_CMD, q_map);
591}
592
593/* Stop the Ethernet port activity */
594static void mvneta_port_down(struct mvneta_port *pp)
595{
596 u32 val;
597 int count;
598
599 /* Stop Rx port activity. Check port Rx activity. */
600 val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK;
601
602 /* Issue stop command for active channels only */
603 if (val != 0)
604 mvreg_write(pp, MVNETA_RXQ_CMD,
605 val << MVNETA_RXQ_DISABLE_SHIFT);
606
607 /* Wait for all Rx activity to terminate. */
608 count = 0;
609 do {
610 if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) {
Sean Andersonc519cbf2020-09-15 10:44:55 -0400611 dev_warn(pp->phydev->dev,
612 "TIMEOUT for RX stopped ! rx_queue_cmd: 0x08%x\n",
613 val);
Stefan Roese19fc2ea2014-10-22 12:13:14 +0200614 break;
615 }
616 mdelay(1);
617
618 val = mvreg_read(pp, MVNETA_RXQ_CMD);
619 } while (val & 0xff);
620
621 /* Stop Tx port activity. Check port Tx activity. Issue stop
622 * command for active channels only
623 */
624 val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK;
625
626 if (val != 0)
627 mvreg_write(pp, MVNETA_TXQ_CMD,
628 (val << MVNETA_TXQ_DISABLE_SHIFT));
629
630 /* Wait for all Tx activity to terminate. */
631 count = 0;
632 do {
633 if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) {
Sean Andersonc519cbf2020-09-15 10:44:55 -0400634 dev_warn(pp->phydev->dev,
635 "TIMEOUT for TX stopped status=0x%08x\n",
636 val);
Stefan Roese19fc2ea2014-10-22 12:13:14 +0200637 break;
638 }
639 mdelay(1);
640
641 /* Check TX Command reg that all Txqs are stopped */
642 val = mvreg_read(pp, MVNETA_TXQ_CMD);
643
644 } while (val & 0xff);
645
646 /* Double check to verify that TX FIFO is empty */
647 count = 0;
648 do {
649 if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) {
Sean Andersonc519cbf2020-09-15 10:44:55 -0400650 dev_warn(pp->phydev->dev,
651 "TX FIFO empty timeout status=0x08%x\n",
652 val);
Stefan Roese19fc2ea2014-10-22 12:13:14 +0200653 break;
654 }
655 mdelay(1);
656
657 val = mvreg_read(pp, MVNETA_PORT_STATUS);
658 } while (!(val & MVNETA_TX_FIFO_EMPTY) &&
659 (val & MVNETA_TX_IN_PRGRS));
660
661 udelay(200);
662}
663
664/* Enable the port by setting the port enable bit of the MAC control register */
665static void mvneta_port_enable(struct mvneta_port *pp)
666{
667 u32 val;
668
669 /* Enable port */
670 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
671 val |= MVNETA_GMAC0_PORT_ENABLE;
672 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
673}
674
675/* Disable the port and wait for about 200 usec before retuning */
676static void mvneta_port_disable(struct mvneta_port *pp)
677{
678 u32 val;
679
680 /* Reset the Enable bit in the Serial Control Register */
681 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
682 val &= ~MVNETA_GMAC0_PORT_ENABLE;
683 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
684
685 udelay(200);
686}
687
688/* Multicast tables methods */
689
690/* Set all entries in Unicast MAC Table; queue==-1 means reject all */
691static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue)
692{
693 int offset;
694 u32 val;
695
696 if (queue == -1) {
697 val = 0;
698 } else {
699 val = 0x1 | (queue << 1);
700 val |= (val << 24) | (val << 16) | (val << 8);
701 }
702
703 for (offset = 0; offset <= 0xc; offset += 4)
704 mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val);
705}
706
707/* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */
708static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue)
709{
710 int offset;
711 u32 val;
712
713 if (queue == -1) {
714 val = 0;
715 } else {
716 val = 0x1 | (queue << 1);
717 val |= (val << 24) | (val << 16) | (val << 8);
718 }
719
720 for (offset = 0; offset <= 0xfc; offset += 4)
721 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val);
722}
723
724/* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */
725static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue)
726{
727 int offset;
728 u32 val;
729
730 if (queue == -1) {
731 memset(pp->mcast_count, 0, sizeof(pp->mcast_count));
732 val = 0;
733 } else {
734 memset(pp->mcast_count, 1, sizeof(pp->mcast_count));
735 val = 0x1 | (queue << 1);
736 val |= (val << 24) | (val << 16) | (val << 8);
737 }
738
739 for (offset = 0; offset <= 0xfc; offset += 4)
740 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val);
741}
742
743/* This method sets defaults to the NETA port:
744 * Clears interrupt Cause and Mask registers.
745 * Clears all MAC tables.
746 * Sets defaults to all registers.
747 * Resets RX and TX descriptor rings.
748 * Resets PHY.
749 * This method can be called after mvneta_port_down() to return the port
750 * settings to defaults.
751 */
752static void mvneta_defaults_set(struct mvneta_port *pp)
753{
754 int cpu;
755 int queue;
756 u32 val;
757
758 /* Clear all Cause registers */
759 mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0);
760 mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
761 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
762
763 /* Mask all interrupts */
764 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
765 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
766 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
767 mvreg_write(pp, MVNETA_INTR_ENABLE, 0);
768
769 /* Enable MBUS Retry bit16 */
770 mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20);
771
772 /* Set CPU queue access map - all CPUs have access to all RX
773 * queues and to all TX queues
774 */
Marek Behún31f4ccc2022-04-27 12:41:57 +0200775 for (cpu = 0; cpu < MVNETA_NR_CPUS; cpu++)
Stefan Roese19fc2ea2014-10-22 12:13:14 +0200776 mvreg_write(pp, MVNETA_CPU_MAP(cpu),
777 (MVNETA_CPU_RXQ_ACCESS_ALL_MASK |
778 MVNETA_CPU_TXQ_ACCESS_ALL_MASK));
779
780 /* Reset RX and TX DMAs */
781 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
782 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
783
784 /* Disable Legacy WRR, Disable EJP, Release from reset */
785 mvreg_write(pp, MVNETA_TXQ_CMD_1, 0);
786 for (queue = 0; queue < txq_number; queue++) {
787 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0);
788 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0);
789 }
790
791 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
792 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
793
794 /* Set Port Acceleration Mode */
795 val = MVNETA_ACC_MODE_EXT;
796 mvreg_write(pp, MVNETA_ACC_MODE, val);
797
798 /* Update val of portCfg register accordingly with all RxQueue types */
799 val = MVNETA_PORT_CONFIG_DEFL_VALUE(rxq_def);
800 mvreg_write(pp, MVNETA_PORT_CONFIG, val);
801
802 val = 0;
803 mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val);
804 mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64);
805
806 /* Build PORT_SDMA_CONFIG_REG */
807 val = 0;
808
809 /* Default burst size */
810 val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
811 val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
812 val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP;
813
814 /* Assign port SDMA configuration */
815 mvreg_write(pp, MVNETA_SDMA_CONFIG, val);
816
Konstantin Porotchkin278d30c2017-02-16 13:52:28 +0200817 /* Enable PHY polling in hardware if not in fixed-link mode */
Simon Glassb51b1a82023-02-22 09:33:51 -0700818 if (!IS_ENABLED(CONFIG_PHY_FIXED) ||
Marek Behúnbdbda1e2022-04-27 12:42:01 +0200819 pp->phydev->phy_id != PHY_FIXED_ID) {
Marek Behúne06c7f32022-04-27 12:41:59 +0200820 mvreg_write(pp, MVNETA_PHY_ADDR, pp->phydev->addr);
821
Konstantin Porotchkin278d30c2017-02-16 13:52:28 +0200822 val = mvreg_read(pp, MVNETA_UNIT_CONTROL);
823 val |= MVNETA_PHY_POLLING_ENABLE;
824 mvreg_write(pp, MVNETA_UNIT_CONTROL, val);
825 }
Stefan Roese19fc2ea2014-10-22 12:13:14 +0200826
827 mvneta_set_ucast_table(pp, -1);
828 mvneta_set_special_mcast_table(pp, -1);
829 mvneta_set_other_mcast_table(pp, -1);
830}
831
832/* Set unicast address */
833static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble,
834 int queue)
835{
836 unsigned int unicast_reg;
837 unsigned int tbl_offset;
838 unsigned int reg_offset;
839
840 /* Locate the Unicast table entry */
841 last_nibble = (0xf & last_nibble);
842
843 /* offset from unicast tbl base */
844 tbl_offset = (last_nibble / 4) * 4;
845
846 /* offset within the above reg */
847 reg_offset = last_nibble % 4;
848
849 unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset));
850
851 if (queue == -1) {
852 /* Clear accepts frame bit at specified unicast DA tbl entry */
853 unicast_reg &= ~(0xff << (8 * reg_offset));
854 } else {
855 unicast_reg &= ~(0xff << (8 * reg_offset));
856 unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
857 }
858
859 mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg);
860}
861
862/* Set mac address */
863static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr,
864 int queue)
865{
866 unsigned int mac_h;
867 unsigned int mac_l;
868
869 if (queue != -1) {
870 mac_l = (addr[4] << 8) | (addr[5]);
871 mac_h = (addr[0] << 24) | (addr[1] << 16) |
872 (addr[2] << 8) | (addr[3] << 0);
873
874 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l);
875 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h);
876 }
877
878 /* Accept frames of this address */
879 mvneta_set_ucast_addr(pp, addr[5], queue);
880}
881
Matt Pelland0a85f022018-03-27 13:18:25 -0400882static int mvneta_write_hwaddr(struct udevice *dev)
883{
884 mvneta_mac_addr_set(dev_get_priv(dev),
Simon Glassc69cda22020-12-03 16:55:20 -0700885 ((struct eth_pdata *)dev_get_plat(dev))->enetaddr,
Matt Pelland0a85f022018-03-27 13:18:25 -0400886 rxq_def);
887
888 return 0;
889}
890
Stefan Roese19fc2ea2014-10-22 12:13:14 +0200891/* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
892static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
893 u32 phys_addr, u32 cookie)
894{
895 rx_desc->buf_cookie = cookie;
896 rx_desc->buf_phys_addr = phys_addr;
897}
898
899/* Decrement sent descriptors counter */
900static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp,
901 struct mvneta_tx_queue *txq,
902 int sent_desc)
903{
904 u32 val;
905
906 /* Only 255 TX descriptors can be updated at once */
907 while (sent_desc > 0xff) {
908 val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT;
909 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
910 sent_desc = sent_desc - 0xff;
911 }
912
913 val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT;
914 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
915}
916
917/* Get number of TX descriptors already sent by HW */
918static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp,
919 struct mvneta_tx_queue *txq)
920{
921 u32 val;
922 int sent_desc;
923
924 val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id));
925 sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >>
926 MVNETA_TXQ_SENT_DESC_SHIFT;
927
928 return sent_desc;
929}
930
931/* Display more error info */
932static void mvneta_rx_error(struct mvneta_port *pp,
933 struct mvneta_rx_desc *rx_desc)
934{
935 u32 status = rx_desc->status;
936
937 if (!mvneta_rxq_desc_is_first_last(status)) {
Sean Andersonc519cbf2020-09-15 10:44:55 -0400938 dev_err(pp->phydev->dev,
939 "bad rx status %08x (buffer oversize), size=%d\n",
940 status, rx_desc->data_size);
Stefan Roese19fc2ea2014-10-22 12:13:14 +0200941 return;
942 }
943
944 switch (status & MVNETA_RXD_ERR_CODE_MASK) {
945 case MVNETA_RXD_ERR_CRC:
Sean Andersonc519cbf2020-09-15 10:44:55 -0400946 dev_err(pp->phydev->dev,
947 "bad rx status %08x (crc error), size=%d\n", status,
948 rx_desc->data_size);
Stefan Roese19fc2ea2014-10-22 12:13:14 +0200949 break;
950 case MVNETA_RXD_ERR_OVERRUN:
Sean Andersonc519cbf2020-09-15 10:44:55 -0400951 dev_err(pp->phydev->dev,
952 "bad rx status %08x (overrun error), size=%d\n", status,
953 rx_desc->data_size);
Stefan Roese19fc2ea2014-10-22 12:13:14 +0200954 break;
955 case MVNETA_RXD_ERR_LEN:
Sean Andersonc519cbf2020-09-15 10:44:55 -0400956 dev_err(pp->phydev->dev,
957 "bad rx status %08x (max frame length error), size=%d\n",
958 status, rx_desc->data_size);
Stefan Roese19fc2ea2014-10-22 12:13:14 +0200959 break;
960 case MVNETA_RXD_ERR_RESOURCE:
Sean Andersonc519cbf2020-09-15 10:44:55 -0400961 dev_err(pp->phydev->dev,
962 "bad rx status %08x (resource error), size=%d\n",
963 status, rx_desc->data_size);
Stefan Roese19fc2ea2014-10-22 12:13:14 +0200964 break;
965 }
966}
967
968static struct mvneta_rx_queue *mvneta_rxq_handle_get(struct mvneta_port *pp,
969 int rxq)
970{
971 return &pp->rxqs[rxq];
972}
973
974
975/* Drop packets received by the RXQ and free buffers */
976static void mvneta_rxq_drop_pkts(struct mvneta_port *pp,
977 struct mvneta_rx_queue *rxq)
978{
979 int rx_done;
980
981 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
982 if (rx_done)
983 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
984}
985
986/* Handle rxq fill: allocates rxq skbs; called when initializing a port */
987static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq,
988 int num)
989{
990 int i;
991
992 for (i = 0; i < num; i++) {
993 u32 addr;
994
995 /* U-Boot special: Fill in the rx buffer addresses */
996 addr = buffer_loc.rx_buffers + (i * RX_BUFFER_SIZE);
997 mvneta_rx_desc_fill(rxq->descs + i, addr, addr);
998 }
999
1000 /* Add this number of RX descriptors as non occupied (ready to
1001 * get packets)
1002 */
1003 mvneta_rxq_non_occup_desc_add(pp, rxq, i);
1004
1005 return 0;
1006}
1007
1008/* Rx/Tx queue initialization/cleanup methods */
1009
1010/* Create a specified RX queue */
1011static int mvneta_rxq_init(struct mvneta_port *pp,
1012 struct mvneta_rx_queue *rxq)
1013
1014{
1015 rxq->size = pp->rx_ring_size;
1016
1017 /* Allocate memory for RX descriptors */
1018 rxq->descs_phys = (dma_addr_t)rxq->descs;
1019 if (rxq->descs == NULL)
1020 return -ENOMEM;
1021
Jon Nettleton199b27b2018-05-30 08:52:29 +03001022 WARN_ON(rxq->descs != PTR_ALIGN(rxq->descs, ARCH_DMA_MINALIGN));
1023
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001024 rxq->last_desc = rxq->size - 1;
1025
1026 /* Set Rx descriptors queue starting address */
1027 mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys);
1028 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size);
1029
1030 /* Fill RXQ with buffers from RX pool */
1031 mvneta_rxq_buf_size_set(pp, rxq, RX_BUFFER_SIZE);
1032 mvneta_rxq_fill(pp, rxq, rxq->size);
1033
1034 return 0;
1035}
1036
1037/* Cleanup Rx queue */
1038static void mvneta_rxq_deinit(struct mvneta_port *pp,
1039 struct mvneta_rx_queue *rxq)
1040{
1041 mvneta_rxq_drop_pkts(pp, rxq);
1042
1043 rxq->descs = NULL;
1044 rxq->last_desc = 0;
1045 rxq->next_desc_to_proc = 0;
1046 rxq->descs_phys = 0;
1047}
1048
1049/* Create and initialize a tx queue */
1050static int mvneta_txq_init(struct mvneta_port *pp,
1051 struct mvneta_tx_queue *txq)
1052{
1053 txq->size = pp->tx_ring_size;
1054
1055 /* Allocate memory for TX descriptors */
Stefan Roese3cbc11d2016-05-19 18:09:17 +02001056 txq->descs_phys = (dma_addr_t)txq->descs;
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001057 if (txq->descs == NULL)
1058 return -ENOMEM;
1059
Jon Nettleton199b27b2018-05-30 08:52:29 +03001060 WARN_ON(txq->descs != PTR_ALIGN(txq->descs, ARCH_DMA_MINALIGN));
1061
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001062 txq->last_desc = txq->size - 1;
1063
1064 /* Set maximum bandwidth for enabled TXQs */
1065 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff);
1066 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff);
1067
1068 /* Set Tx descriptors queue starting address */
1069 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys);
1070 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size);
1071
1072 return 0;
1073}
1074
1075/* Free allocated resources when mvneta_txq_init() fails to allocate memory*/
1076static void mvneta_txq_deinit(struct mvneta_port *pp,
1077 struct mvneta_tx_queue *txq)
1078{
1079 txq->descs = NULL;
1080 txq->last_desc = 0;
1081 txq->next_desc_to_proc = 0;
1082 txq->descs_phys = 0;
1083
1084 /* Set minimum bandwidth for disabled TXQs */
1085 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0);
1086 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0);
1087
1088 /* Set Tx descriptors queue starting address and size */
1089 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0);
1090 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0);
1091}
1092
1093/* Cleanup all Tx queues */
1094static void mvneta_cleanup_txqs(struct mvneta_port *pp)
1095{
1096 int queue;
1097
1098 for (queue = 0; queue < txq_number; queue++)
1099 mvneta_txq_deinit(pp, &pp->txqs[queue]);
1100}
1101
1102/* Cleanup all Rx queues */
1103static void mvneta_cleanup_rxqs(struct mvneta_port *pp)
1104{
1105 int queue;
1106
1107 for (queue = 0; queue < rxq_number; queue++)
1108 mvneta_rxq_deinit(pp, &pp->rxqs[queue]);
1109}
1110
1111
1112/* Init all Rx queues */
1113static int mvneta_setup_rxqs(struct mvneta_port *pp)
1114{
1115 int queue;
1116
1117 for (queue = 0; queue < rxq_number; queue++) {
1118 int err = mvneta_rxq_init(pp, &pp->rxqs[queue]);
1119 if (err) {
Sean Andersonc519cbf2020-09-15 10:44:55 -04001120 dev_err(pp->phydev->dev, "%s: can't create rxq=%d\n",
1121 __func__, queue);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001122 mvneta_cleanup_rxqs(pp);
1123 return err;
1124 }
1125 }
1126
1127 return 0;
1128}
1129
1130/* Init all tx queues */
1131static int mvneta_setup_txqs(struct mvneta_port *pp)
1132{
1133 int queue;
1134
1135 for (queue = 0; queue < txq_number; queue++) {
1136 int err = mvneta_txq_init(pp, &pp->txqs[queue]);
1137 if (err) {
Sean Andersonc519cbf2020-09-15 10:44:55 -04001138 dev_err(pp->phydev->dev, "%s: can't create txq=%d\n",
1139 __func__, queue);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001140 mvneta_cleanup_txqs(pp);
1141 return err;
1142 }
1143 }
1144
1145 return 0;
1146}
1147
1148static void mvneta_start_dev(struct mvneta_port *pp)
1149{
1150 /* start the Rx/Tx activity */
1151 mvneta_port_enable(pp);
1152}
1153
Stefan Roesee3b9c982015-11-19 07:46:15 +01001154static void mvneta_adjust_link(struct udevice *dev)
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001155{
Stefan Roesee3b9c982015-11-19 07:46:15 +01001156 struct mvneta_port *pp = dev_get_priv(dev);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001157 struct phy_device *phydev = pp->phydev;
Marek Behún3b38fad2022-04-27 12:41:54 +02001158 bool status_change = false;
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001159
Marek Behúnca4730a2022-04-27 12:41:53 +02001160 if (phydev->link &&
1161 (pp->speed != phydev->speed || pp->duplex != phydev->duplex)) {
1162 u32 val;
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001163
Marek Behúnca4730a2022-04-27 12:41:53 +02001164 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
1165 val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED |
1166 MVNETA_GMAC_CONFIG_GMII_SPEED |
1167 MVNETA_GMAC_CONFIG_FULL_DUPLEX |
1168 MVNETA_GMAC_AN_SPEED_EN |
1169 MVNETA_GMAC_AN_DUPLEX_EN);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001170
Marek Behún77fcf3c2022-04-27 12:41:58 +02001171 /* FIXME: For fixed-link case, these were the initial settings
1172 * used before the code was converted to use PHY_FIXED. Some of
1173 * these may look nonsensical (for example BYPASS_AN makes sense
1174 * for 1000base-x and 2500base-x modes, AFAIK), and in fact this
1175 * may be changed in the future (when support for inband AN will
1176 * be added). Also, why is ADVERT_FC enabled if we don't enable
1177 * inband AN at all?
1178 */
Simon Glassb51b1a82023-02-22 09:33:51 -07001179 if (IS_ENABLED(CONFIG_PHY_FIXED) &&
Marek Behúnbdbda1e2022-04-27 12:42:01 +02001180 pp->phydev->phy_id == PHY_FIXED_ID)
Marek Behún95a3a6e2022-04-27 12:42:02 +02001181 val = MVNETA_GMAC_IB_BYPASS_AN_EN |
Marek Behún77fcf3c2022-04-27 12:41:58 +02001182 MVNETA_GMAC_SET_FC_EN |
1183 MVNETA_GMAC_ADVERT_FC_EN |
1184 MVNETA_GMAC_SAMPLE_TX_CFG_EN;
1185
Marek Behúnca4730a2022-04-27 12:41:53 +02001186 if (phydev->duplex)
1187 val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001188
Marek Behúnca4730a2022-04-27 12:41:53 +02001189 if (phydev->speed == SPEED_1000)
1190 val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
1191 else if (pp->speed == SPEED_100)
1192 val |= MVNETA_GMAC_CONFIG_MII_SPEED;
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001193
Marek Behúnca4730a2022-04-27 12:41:53 +02001194 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001195
Marek Behúnca4730a2022-04-27 12:41:53 +02001196 pp->duplex = phydev->duplex;
Marek Behún824f2f92022-04-27 12:41:55 +02001197 pp->speed = phydev->speed;
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001198 }
1199
1200 if (phydev->link != pp->link) {
1201 if (!phydev->link) {
1202 pp->duplex = -1;
1203 pp->speed = 0;
1204 }
1205
1206 pp->link = phydev->link;
Marek Behún3b38fad2022-04-27 12:41:54 +02001207 status_change = true;
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001208 }
1209
1210 if (status_change) {
1211 if (phydev->link) {
1212 u32 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
1213 val |= (MVNETA_GMAC_FORCE_LINK_PASS |
1214 MVNETA_GMAC_FORCE_LINK_DOWN);
1215 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
1216 mvneta_port_up(pp);
1217 } else {
1218 mvneta_port_down(pp);
1219 }
1220 }
1221}
1222
Stefan Roesee3b9c982015-11-19 07:46:15 +01001223static int mvneta_open(struct udevice *dev)
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001224{
Stefan Roesee3b9c982015-11-19 07:46:15 +01001225 struct mvneta_port *pp = dev_get_priv(dev);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001226 int ret;
1227
1228 ret = mvneta_setup_rxqs(pp);
1229 if (ret)
1230 return ret;
1231
1232 ret = mvneta_setup_txqs(pp);
1233 if (ret)
1234 return ret;
1235
1236 mvneta_adjust_link(dev);
1237
1238 mvneta_start_dev(pp);
1239
1240 return 0;
1241}
1242
1243/* Initialize hw */
Stefan Roesee3b9c982015-11-19 07:46:15 +01001244static int mvneta_init2(struct mvneta_port *pp)
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001245{
1246 int queue;
1247
1248 /* Disable port */
1249 mvneta_port_disable(pp);
1250
1251 /* Set port default values */
1252 mvneta_defaults_set(pp);
1253
1254 pp->txqs = kzalloc(txq_number * sizeof(struct mvneta_tx_queue),
1255 GFP_KERNEL);
1256 if (!pp->txqs)
1257 return -ENOMEM;
1258
1259 /* U-Boot special: use preallocated area */
1260 pp->txqs[0].descs = buffer_loc.tx_descs;
1261
1262 /* Initialize TX descriptor rings */
1263 for (queue = 0; queue < txq_number; queue++) {
1264 struct mvneta_tx_queue *txq = &pp->txqs[queue];
1265 txq->id = queue;
1266 txq->size = pp->tx_ring_size;
1267 }
1268
1269 pp->rxqs = kzalloc(rxq_number * sizeof(struct mvneta_rx_queue),
1270 GFP_KERNEL);
1271 if (!pp->rxqs) {
1272 kfree(pp->txqs);
1273 return -ENOMEM;
1274 }
1275
1276 /* U-Boot special: use preallocated area */
1277 pp->rxqs[0].descs = buffer_loc.rx_descs;
1278
1279 /* Create Rx descriptor rings */
1280 for (queue = 0; queue < rxq_number; queue++) {
1281 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
1282 rxq->id = queue;
1283 rxq->size = pp->rx_ring_size;
1284 }
1285
1286 return 0;
1287}
1288
1289/* platform glue : initialize decoding windows */
Stefan Roese544eefe2016-05-19 17:46:36 +02001290
1291/*
1292 * Not like A380, in Armada3700, there are two layers of decode windows for GBE:
1293 * First layer is: GbE Address window that resides inside the GBE unit,
1294 * Second layer is: Fabric address window which is located in the NIC400
1295 * (South Fabric).
1296 * To simplify the address decode configuration for Armada3700, we bypass the
1297 * first layer of GBE decode window by setting the first window to 4GB.
1298 */
1299static void mvneta_bypass_mbus_windows(struct mvneta_port *pp)
1300{
1301 /*
1302 * Set window size to 4GB, to bypass GBE address decode, leave the
1303 * work to MBUS decode window
1304 */
1305 mvreg_write(pp, MVNETA_WIN_SIZE(0), MVNETA_WIN_SIZE_MASK);
1306
1307 /* Enable GBE address decode window 0 by set bit 0 to 0 */
1308 clrbits_le32(pp->base + MVNETA_BASE_ADDR_ENABLE,
1309 MVNETA_BASE_ADDR_ENABLE_BIT);
1310
1311 /* Set GBE address decode window 0 to full Access (read or write) */
1312 setbits_le32(pp->base + MVNETA_PORT_ACCESS_PROTECT,
1313 MVNETA_PORT_ACCESS_PROTECT_WIN0_RW);
1314}
1315
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001316static void mvneta_conf_mbus_windows(struct mvneta_port *pp)
1317{
1318 const struct mbus_dram_target_info *dram;
1319 u32 win_enable;
1320 u32 win_protect;
1321 int i;
1322
1323 dram = mvebu_mbus_dram_info();
1324 for (i = 0; i < 6; i++) {
1325 mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
1326 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
1327
1328 if (i < 4)
1329 mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
1330 }
1331
1332 win_enable = 0x3f;
1333 win_protect = 0;
1334
1335 for (i = 0; i < dram->num_cs; i++) {
1336 const struct mbus_dram_window *cs = dram->cs + i;
1337 mvreg_write(pp, MVNETA_WIN_BASE(i), (cs->base & 0xffff0000) |
1338 (cs->mbus_attr << 8) | dram->mbus_dram_target_id);
1339
1340 mvreg_write(pp, MVNETA_WIN_SIZE(i),
1341 (cs->size - 1) & 0xffff0000);
1342
1343 win_enable &= ~(1 << i);
1344 win_protect |= 3 << (2 * i);
1345 }
1346
1347 mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
1348}
1349
Chris Packhamaaee5722022-11-05 17:23:56 +13001350static void mvneta_conf_ac5_cnm_xbar_windows(struct mvneta_port *pp)
1351{
1352 int i;
1353
1354 /* Clear all windows */
1355 for (i = 0; i < 6; i++) {
1356 mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
1357 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
1358
1359 if (i < 4)
1360 mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
1361 }
1362
1363 /*
1364 * Setup window #0 base 0x0 to target XBAR port 2 (AMB2), attribute 0xb, size 4GB
1365 * AMB2 address decoder remaps 0x0 to DDR 64 bit base address
1366 */
1367 mvreg_write(pp, MVNETA_WIN_BASE(0),
1368 (MVNETA_AC5_CNM_DDR_ATTR << 8) | MVNETA_AC5_CNM_DDR_TARGET);
1369 mvreg_write(pp, MVNETA_WIN_SIZE(0), 0xffff0000);
1370 mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, 0x3e);
1371}
1372
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001373/* Power up the port */
1374static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode)
1375{
1376 u32 ctrl;
1377
1378 /* MAC Cause register should be cleared */
1379 mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0);
1380
1381 ctrl = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
1382
1383 /* Even though it might look weird, when we're configured in
1384 * SGMII or QSGMII mode, the RGMII bit needs to be set.
1385 */
1386 switch (phy_mode) {
1387 case PHY_INTERFACE_MODE_QSGMII:
1388 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO);
1389 ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII;
1390 break;
1391 case PHY_INTERFACE_MODE_SGMII:
1392 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO);
1393 ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII;
1394 break;
1395 case PHY_INTERFACE_MODE_RGMII:
1396 case PHY_INTERFACE_MODE_RGMII_ID:
1397 ctrl |= MVNETA_GMAC2_PORT_RGMII;
1398 break;
1399 default:
1400 return -EINVAL;
1401 }
1402
1403 /* Cancel Port Reset */
1404 ctrl &= ~MVNETA_GMAC2_PORT_RESET;
1405 mvreg_write(pp, MVNETA_GMAC_CTRL_2, ctrl);
1406
1407 while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) &
1408 MVNETA_GMAC2_PORT_RESET) != 0)
1409 continue;
1410
1411 return 0;
1412}
1413
1414/* Device initialization routine */
Stefan Roesee3b9c982015-11-19 07:46:15 +01001415static int mvneta_init(struct udevice *dev)
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001416{
Simon Glassc69cda22020-12-03 16:55:20 -07001417 struct eth_pdata *pdata = dev_get_plat(dev);
Stefan Roesee3b9c982015-11-19 07:46:15 +01001418 struct mvneta_port *pp = dev_get_priv(dev);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001419 int err;
1420
1421 pp->tx_ring_size = MVNETA_MAX_TXD;
1422 pp->rx_ring_size = MVNETA_MAX_RXD;
1423
Stefan Roesee3b9c982015-11-19 07:46:15 +01001424 err = mvneta_init2(pp);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001425 if (err < 0) {
Sean Anderson13cbe292020-09-15 10:44:54 -04001426 dev_err(dev, "can't init eth hal\n");
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001427 return err;
1428 }
1429
Stefan Roesee3b9c982015-11-19 07:46:15 +01001430 mvneta_mac_addr_set(pp, pdata->enetaddr, rxq_def);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001431
1432 err = mvneta_port_power_up(pp, pp->phy_interface);
1433 if (err < 0) {
Sean Anderson13cbe292020-09-15 10:44:54 -04001434 dev_err(dev, "can't power up port\n");
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001435 return err;
1436 }
1437
1438 /* Call open() now as it needs to be done before runing send() */
1439 mvneta_open(dev);
1440
1441 return 0;
1442}
1443
1444/* U-Boot only functions follow here */
1445
Stefan Roesee3b9c982015-11-19 07:46:15 +01001446static int mvneta_start(struct udevice *dev)
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001447{
Stefan Roesee3b9c982015-11-19 07:46:15 +01001448 struct mvneta_port *pp = dev_get_priv(dev);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001449 struct phy_device *phydev;
1450
1451 mvneta_port_power_up(pp, pp->phy_interface);
1452
1453 if (!pp->init || pp->link == 0) {
Marek Behún77fcf3c2022-04-27 12:41:58 +02001454 phydev = dm_eth_phy_connect(dev);
1455 if (!phydev) {
1456 printf("dm_eth_phy_connect failed\n");
1457 return -ENODEV;
1458 }
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001459
Marek Behún77fcf3c2022-04-27 12:41:58 +02001460 pp->phydev = phydev;
1461 phy_config(phydev);
1462 phy_startup(phydev);
1463 if (!phydev->link) {
1464 printf("%s: No link.\n", phydev->dev->name);
1465 return -1;
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001466 }
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001467
Marek Behún77fcf3c2022-04-27 12:41:58 +02001468 /* Full init on first call */
1469 mvneta_init(dev);
1470 pp->init = 1;
1471 } else {
1472 /* Upon all following calls, this is enough */
1473 mvneta_port_up(pp);
1474 mvneta_port_enable(pp);
1475 }
Konstantin Porotchkin278d30c2017-02-16 13:52:28 +02001476
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001477 return 0;
1478}
1479
Stefan Roesee3b9c982015-11-19 07:46:15 +01001480static int mvneta_send(struct udevice *dev, void *packet, int length)
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001481{
Stefan Roesee3b9c982015-11-19 07:46:15 +01001482 struct mvneta_port *pp = dev_get_priv(dev);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001483 struct mvneta_tx_queue *txq = &pp->txqs[0];
1484 struct mvneta_tx_desc *tx_desc;
1485 int sent_desc;
1486 u32 timeout = 0;
1487
1488 /* Get a descriptor for the first part of the packet */
1489 tx_desc = mvneta_txq_next_desc_get(txq);
1490
Stefan Roese3cbc11d2016-05-19 18:09:17 +02001491 tx_desc->buf_phys_addr = (u32)(uintptr_t)packet;
Stefan Roesee3b9c982015-11-19 07:46:15 +01001492 tx_desc->data_size = length;
Stefan Roese3cbc11d2016-05-19 18:09:17 +02001493 flush_dcache_range((ulong)packet,
1494 (ulong)packet + ALIGN(length, PKTALIGN));
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001495
1496 /* First and Last descriptor */
1497 tx_desc->command = MVNETA_TX_L4_CSUM_NOT | MVNETA_TXD_FLZ_DESC;
1498 mvneta_txq_pend_desc_add(pp, txq, 1);
1499
1500 /* Wait for packet to be sent (queue might help with speed here) */
1501 sent_desc = mvneta_txq_sent_desc_num_get(pp, txq);
1502 while (!sent_desc) {
1503 if (timeout++ > 10000) {
1504 printf("timeout: packet not sent\n");
1505 return -1;
1506 }
1507 sent_desc = mvneta_txq_sent_desc_num_get(pp, txq);
1508 }
1509
1510 /* txDone has increased - hw sent packet */
1511 mvneta_txq_sent_desc_dec(pp, txq, sent_desc);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001512
1513 return 0;
1514}
1515
Stefan Roesee3b9c982015-11-19 07:46:15 +01001516static int mvneta_recv(struct udevice *dev, int flags, uchar **packetp)
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001517{
Stefan Roesee3b9c982015-11-19 07:46:15 +01001518 struct mvneta_port *pp = dev_get_priv(dev);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001519 int rx_done;
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001520 struct mvneta_rx_queue *rxq;
Stefan Roesee3b9c982015-11-19 07:46:15 +01001521 int rx_bytes = 0;
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001522
1523 /* get rx queue */
1524 rxq = mvneta_rxq_handle_get(pp, rxq_def);
1525 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001526
Stefan Roesee3b9c982015-11-19 07:46:15 +01001527 if (rx_done) {
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001528 struct mvneta_rx_desc *rx_desc;
1529 unsigned char *data;
1530 u32 rx_status;
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001531
1532 /*
1533 * No cache invalidation needed here, since the desc's are
1534 * located in a uncached memory region
1535 */
1536 rx_desc = mvneta_rxq_next_desc_get(rxq);
1537
1538 rx_status = rx_desc->status;
1539 if (!mvneta_rxq_desc_is_first_last(rx_status) ||
1540 (rx_status & MVNETA_RXD_ERR_SUMMARY)) {
1541 mvneta_rx_error(pp, rx_desc);
1542 /* leave the descriptor untouched */
Stefan Roesee3b9c982015-11-19 07:46:15 +01001543 return -EIO;
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001544 }
1545
1546 /* 2 bytes for marvell header. 4 bytes for crc */
1547 rx_bytes = rx_desc->data_size - 6;
1548
1549 /* give packet to stack - skip on first 2 bytes */
Stefan Roese3cbc11d2016-05-19 18:09:17 +02001550 data = (u8 *)(uintptr_t)rx_desc->buf_cookie + 2;
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001551 /*
1552 * No cache invalidation needed here, since the rx_buffer's are
1553 * located in a uncached memory region
1554 */
Chris Packhamaaee5722022-11-05 17:23:56 +13001555 *packetp = data + pp->dma_base;
Stefan Roesee3b9c982015-11-19 07:46:15 +01001556
Jason Brown32ac8b02017-11-28 11:12:43 -08001557 /*
1558 * Only mark one descriptor as free
1559 * since only one was processed
1560 */
1561 mvneta_rxq_desc_num_update(pp, rxq, 1, 1);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001562 }
1563
Stefan Roesee3b9c982015-11-19 07:46:15 +01001564 return rx_bytes;
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001565}
1566
Stefan Roesee3b9c982015-11-19 07:46:15 +01001567static int mvneta_probe(struct udevice *dev)
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001568{
Stefan Roesee3b9c982015-11-19 07:46:15 +01001569 struct mvneta_port *pp = dev_get_priv(dev);
Robert Marko2b7beb92022-03-24 10:57:37 +01001570#if CONFIG_IS_ENABLED(DM_GPIO)
1571 struct ofnode_phandle_args sfp_args;
1572#endif
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001573 void *bd_space;
Chris Packhamaaee5722022-11-05 17:23:56 +13001574 phys_addr_t cpu;
1575 dma_addr_t bus;
1576 u64 size;
1577 int ret;
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001578
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001579 /*
1580 * Allocate buffer area for descs and rx_buffers. This is only
1581 * done once for all interfaces. As only one interface can
Chris Packham6723b232016-08-29 20:54:02 +12001582 * be active. Make this area DMA safe by disabling the D-cache
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001583 */
1584 if (!buffer_loc.tx_descs) {
Jon Nettleton199b27b2018-05-30 08:52:29 +03001585 u32 size;
1586
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001587 /* Align buffer area for descs and rx_buffers to 1MiB */
1588 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
Rabeeh Khoury0f8888b2018-06-19 21:36:50 +03001589 flush_dcache_range((ulong)bd_space, (ulong)bd_space + BD_SPACE);
Stefan Roese3cbc11d2016-05-19 18:09:17 +02001590 mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, BD_SPACE,
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001591 DCACHE_OFF);
1592 buffer_loc.tx_descs = (struct mvneta_tx_desc *)bd_space;
Jon Nettleton199b27b2018-05-30 08:52:29 +03001593 size = roundup(MVNETA_MAX_TXD * sizeof(struct mvneta_tx_desc),
1594 ARCH_DMA_MINALIGN);
Rabeeh Khoury318b5d72018-06-19 21:36:51 +03001595 memset(buffer_loc.tx_descs, 0, size);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001596 buffer_loc.rx_descs = (struct mvneta_rx_desc *)
Jon Nettleton199b27b2018-05-30 08:52:29 +03001597 ((phys_addr_t)bd_space + size);
1598 size += roundup(MVNETA_MAX_RXD * sizeof(struct mvneta_rx_desc),
1599 ARCH_DMA_MINALIGN);
1600 buffer_loc.rx_buffers = (phys_addr_t)(bd_space + size);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001601 }
1602
Marek Behún443cf352022-04-27 12:41:44 +02001603 pp->base = dev_read_addr_ptr(dev);
1604 pp->phy_interface = dev_read_phy_mode(dev);
1605 if (pp->phy_interface == PHY_INTERFACE_MODE_NA)
1606 return -EINVAL;
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001607
Stefan Roesee3b9c982015-11-19 07:46:15 +01001608 /* Configure MBUS address windows */
Simon Glass911f3ae2017-05-18 20:08:57 -06001609 if (device_is_compatible(dev, "marvell,armada-3700-neta"))
Stefan Roese544eefe2016-05-19 17:46:36 +02001610 mvneta_bypass_mbus_windows(pp);
Chris Packhamaaee5722022-11-05 17:23:56 +13001611 else if (device_is_compatible(dev, "marvell,armada-ac5-neta"))
1612 mvneta_conf_ac5_cnm_xbar_windows(pp);
Stefan Roese544eefe2016-05-19 17:46:36 +02001613 else
1614 mvneta_conf_mbus_windows(pp);
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001615
Chris Packhamaaee5722022-11-05 17:23:56 +13001616 /* fetch dma ranges property */
1617 ret = dev_get_dma_range(dev, &cpu, &bus, &size);
1618 if (!ret)
1619 pp->dma_base = cpu;
1620 else
1621 pp->dma_base = 0;
1622
Simon Glassbcee8d62019-12-06 21:41:35 -07001623#if CONFIG_IS_ENABLED(DM_GPIO)
Marek Behún7ec50402022-04-27 12:41:52 +02001624 if (!dev_read_phandle_with_args(dev, "sfp", NULL, 0, 0, &sfp_args) &&
1625 ofnode_is_enabled(sfp_args.node))
Robert Marko2b7beb92022-03-24 10:57:37 +01001626 gpio_request_by_name_nodev(sfp_args.node, "tx-disable-gpio", 0,
1627 &pp->sfp_tx_disable_gpio, GPIOD_IS_OUT);
1628
Aditya Prayoga18bfc8f2018-12-05 00:39:23 +08001629 gpio_request_by_name(dev, "phy-reset-gpios", 0,
1630 &pp->phy_reset_gpio, GPIOD_IS_OUT);
1631
1632 if (dm_gpio_is_valid(&pp->phy_reset_gpio)) {
1633 dm_gpio_set_value(&pp->phy_reset_gpio, 1);
1634 mdelay(10);
1635 dm_gpio_set_value(&pp->phy_reset_gpio, 0);
1636 }
Robert Marko2b7beb92022-03-24 10:57:37 +01001637
1638 if (dm_gpio_is_valid(&pp->sfp_tx_disable_gpio))
1639 dm_gpio_set_value(&pp->sfp_tx_disable_gpio, 0);
Aditya Prayoga18bfc8f2018-12-05 00:39:23 +08001640#endif
1641
Marek Behún1d879042022-04-27 12:41:51 +02001642 return 0;
Stefan Roese19fc2ea2014-10-22 12:13:14 +02001643}
Stefan Roesee3b9c982015-11-19 07:46:15 +01001644
1645static void mvneta_stop(struct udevice *dev)
1646{
1647 struct mvneta_port *pp = dev_get_priv(dev);
1648
1649 mvneta_port_down(pp);
1650 mvneta_port_disable(pp);
1651}
1652
1653static const struct eth_ops mvneta_ops = {
1654 .start = mvneta_start,
1655 .send = mvneta_send,
1656 .recv = mvneta_recv,
1657 .stop = mvneta_stop,
Matt Pelland0a85f022018-03-27 13:18:25 -04001658 .write_hwaddr = mvneta_write_hwaddr,
Stefan Roesee3b9c982015-11-19 07:46:15 +01001659};
1660
Stefan Roesee3b9c982015-11-19 07:46:15 +01001661static const struct udevice_id mvneta_ids[] = {
1662 { .compatible = "marvell,armada-370-neta" },
Chris Packhamaaee5722022-11-05 17:23:56 +13001663 { .compatible = "marvell,armada-ac5-neta" },
Stefan Roesee3b9c982015-11-19 07:46:15 +01001664 { .compatible = "marvell,armada-xp-neta" },
Stefan Roese544eefe2016-05-19 17:46:36 +02001665 { .compatible = "marvell,armada-3700-neta" },
Stefan Roesee3b9c982015-11-19 07:46:15 +01001666 { }
1667};
1668
1669U_BOOT_DRIVER(mvneta) = {
1670 .name = "mvneta",
1671 .id = UCLASS_ETH,
1672 .of_match = mvneta_ids,
Stefan Roesee3b9c982015-11-19 07:46:15 +01001673 .probe = mvneta_probe,
1674 .ops = &mvneta_ops,
Simon Glass41575d82020-12-03 16:55:17 -07001675 .priv_auto = sizeof(struct mvneta_port),
Simon Glasscaa4daa2020-12-03 16:55:18 -07001676 .plat_auto = sizeof(struct eth_pdata),
Stefan Roesee3b9c982015-11-19 07:46:15 +01001677};