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Dave Liu8bd522c2008-01-11 18:48:24 +08001/*
Scott Woode8d3ca82010-08-30 18:04:52 -05002 * Copyright (C) 2007-2010 Freescale Semiconductor, Inc.
Dave Liu8bd522c2008-01-11 18:48:24 +08003 *
4 * Dave Liu <daveliu@freescale.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#ifndef __CONFIG_H
26#define __CONFIG_H
27
Scott Woodf1c574d2010-11-24 13:28:40 +000028#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
29#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
30#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
31#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
32#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
33
34#ifdef CONFIG_NAND_U_BOOT
35#define CONFIG_SYS_TEXT_BASE 0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */
36#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
37#ifdef CONFIG_NAND_SPL
38#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
39#endif /* CONFIG_NAND_SPL */
40#endif /* CONFIG_NAND_U_BOOT */
Wolfgang Denk2ae18242010-10-06 09:05:45 +020041
42#ifndef CONFIG_SYS_TEXT_BASE
43#define CONFIG_SYS_TEXT_BASE 0xFE000000
Anton Vorontsov2e950042009-11-24 20:12:12 +030044#endif
45
Scott Woodf1c574d2010-11-24 13:28:40 +000046#ifndef CONFIG_SYS_MONITOR_BASE
47#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
48#endif
49
Dave Liu8bd522c2008-01-11 18:48:24 +080050/*
51 * High Level Configuration Options
52 */
53#define CONFIG_E300 1 /* E300 family */
Peter Tyser0f898602009-05-22 17:23:24 -050054#define CONFIG_MPC83xx 1 /* MPC83xx family */
Peter Tyser2c7920a2009-05-22 17:23:25 -050055#define CONFIG_MPC831x 1 /* MPC831x CPU family */
Dave Liu8bd522c2008-01-11 18:48:24 +080056#define CONFIG_MPC8315 1 /* MPC8315 CPU specific */
57#define CONFIG_MPC8315ERDB 1 /* MPC8315ERDB board specific */
58
59/*
60 * System Clock Setup
61 */
62#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
63#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
64
65/*
66 * Hardware Reset Configuration Word
67 * if CLKIN is 66.66MHz, then
68 * CSB = 133MHz, CORE = 400MHz, DDRC = 266MHz, LBC = 133MHz
69 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020070#define CONFIG_SYS_HRCW_LOW (\
Dave Liu8bd522c2008-01-11 18:48:24 +080071 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
72 HRCWL_DDR_TO_SCB_CLK_2X1 |\
73 HRCWL_SVCOD_DIV_2 |\
74 HRCWL_CSB_TO_CLKIN_2X1 |\
75 HRCWL_CORE_TO_CSB_3X1)
Anton Vorontsov2e950042009-11-24 20:12:12 +030076#define CONFIG_SYS_HRCW_HIGH_BASE (\
Dave Liu8bd522c2008-01-11 18:48:24 +080077 HRCWH_PCI_HOST |\
78 HRCWH_PCI1_ARBITER_ENABLE |\
79 HRCWH_CORE_ENABLE |\
Dave Liu8bd522c2008-01-11 18:48:24 +080080 HRCWH_BOOTSEQ_DISABLE |\
81 HRCWH_SW_WATCHDOG_DISABLE |\
Dave Liu8bd522c2008-01-11 18:48:24 +080082 HRCWH_TSEC1M_IN_RGMII |\
83 HRCWH_TSEC2M_IN_RGMII |\
84 HRCWH_BIG_ENDIAN |\
85 HRCWH_LALE_NORMAL)
86
Anton Vorontsov2e950042009-11-24 20:12:12 +030087#ifdef CONFIG_NAND_SPL
88#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
89 HRCWH_FROM_0XFFF00100 |\
90 HRCWH_ROM_LOC_NAND_SP_8BIT |\
91 HRCWH_RL_EXT_NAND)
92#else
93#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
94 HRCWH_FROM_0X00000100 |\
95 HRCWH_ROM_LOC_LOCAL_16BIT |\
96 HRCWH_RL_EXT_LEGACY)
97#endif
98
Dave Liu8bd522c2008-01-11 18:48:24 +080099/*
100 * System IO Config
101 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102#define CONFIG_SYS_SICRH 0x00000000
103#define CONFIG_SYS_SICRL 0x00000000 /* 3.3V, no delay */
Dave Liu8bd522c2008-01-11 18:48:24 +0800104
105#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
Anton Vorontsovb8b71ff2009-06-10 00:25:36 +0400106#define CONFIG_HWCONFIG
Dave Liu8bd522c2008-01-11 18:48:24 +0800107
108/*
109 * IMMR new address
110 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#define CONFIG_SYS_IMMR 0xE0000000
Dave Liu8bd522c2008-01-11 18:48:24 +0800112
Anton Vorontsov2e950042009-11-24 20:12:12 +0300113#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
114#define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
115#endif
116
Dave Liu8bd522c2008-01-11 18:48:24 +0800117/*
118 * Arbiter Setup
119 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
Joe Hershberger6f681b72011-10-11 23:57:11 -0500121#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
122#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
Dave Liu8bd522c2008-01-11 18:48:24 +0800123
124/*
125 * DDR Setup
126 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
128#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
129#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
130#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
Joe Hershberger6f681b72011-10-11 23:57:11 -0500131#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
Dave Liu8bd522c2008-01-11 18:48:24 +0800132 | DDRCDR_PZ_LOZ \
133 | DDRCDR_NZ_LOZ \
134 | DDRCDR_ODT \
Joe Hershberger6f681b72011-10-11 23:57:11 -0500135 | DDRCDR_Q_DRN)
Dave Liu8bd522c2008-01-11 18:48:24 +0800136 /* 0x7b880001 */
137/*
138 * Manually set up DDR parameters
139 * consist of two chips HY5PS12621BFP-C4 from HYNIX
140 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_DDR_SIZE 128 /* MB */
142#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
Joe Hershberger6f681b72011-10-11 23:57:11 -0500143#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
Joe Hershberger2fef4022011-10-11 23:57:29 -0500144 | CSCONFIG_ODT_RD_NEVER \
145 | CSCONFIG_ODT_WR_ONLY_CURRENT \
Joe Hershberger6f681b72011-10-11 23:57:11 -0500146 | CSCONFIG_ROW_BIT_13 \
147 | CSCONFIG_COL_BIT_10)
Dave Liu8bd522c2008-01-11 18:48:24 +0800148 /* 0x80010102 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149#define CONFIG_SYS_DDR_TIMING_3 0x00000000
Joe Hershberger6f681b72011-10-11 23:57:11 -0500150#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
151 | (0 << TIMING_CFG0_WRT_SHIFT) \
152 | (0 << TIMING_CFG0_RRT_SHIFT) \
153 | (0 << TIMING_CFG0_WWT_SHIFT) \
154 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
155 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
156 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
157 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
Dave Liu8bd522c2008-01-11 18:48:24 +0800158 /* 0x00220802 */
Joe Hershberger6f681b72011-10-11 23:57:11 -0500159#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
160 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
161 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
162 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
163 | (6 << TIMING_CFG1_REFREC_SHIFT) \
164 | (2 << TIMING_CFG1_WRREC_SHIFT) \
165 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
166 | (2 << TIMING_CFG1_WRTORD_SHIFT))
Howard Gregory2f2a5c32008-11-04 14:55:33 +0800167 /* 0x27256222 */
Joe Hershberger6f681b72011-10-11 23:57:11 -0500168#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
169 | (4 << TIMING_CFG2_CPO_SHIFT) \
170 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
171 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
172 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
173 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
174 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
Howard Gregory2f2a5c32008-11-04 14:55:33 +0800175 /* 0x121048c5 */
Joe Hershberger6f681b72011-10-11 23:57:11 -0500176#define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
177 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
Dave Liu8bd522c2008-01-11 18:48:24 +0800178 /* 0x03600100 */
Joe Hershberger6f681b72011-10-11 23:57:11 -0500179#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
Dave Liu8bd522c2008-01-11 18:48:24 +0800180 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
Joe Hershberger2fef4022011-10-11 23:57:29 -0500181 | SDRAM_CFG_DBW_32)
Dave Liu8bd522c2008-01-11 18:48:24 +0800182 /* 0x43080000 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
Joe Hershberger6f681b72011-10-11 23:57:11 -0500184#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
185 | (0x0232 << SDRAM_MODE_SD_SHIFT))
Dave Liu8bd522c2008-01-11 18:48:24 +0800186 /* ODT 150ohm CL=3, AL=1 on SDRAM */
Joe Hershberger6f681b72011-10-11 23:57:11 -0500187#define CONFIG_SYS_DDR_MODE2 0x00000000
Dave Liu8bd522c2008-01-11 18:48:24 +0800188
189/*
190 * Memory test
191 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
193#define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */
194#define CONFIG_SYS_MEMTEST_END 0x00140000
Dave Liu8bd522c2008-01-11 18:48:24 +0800195
196/*
197 * The reserved memory
198 */
Joe Hershberger6f681b72011-10-11 23:57:11 -0500199#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
200#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
Dave Liu8bd522c2008-01-11 18:48:24 +0800201
202/*
203 * Initial RAM Base Address Setup
204 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_INIT_RAM_LOCK 1
206#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200207#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
Joe Hershberger6f681b72011-10-11 23:57:11 -0500208#define CONFIG_SYS_GBL_DATA_OFFSET \
209 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Dave Liu8bd522c2008-01-11 18:48:24 +0800210
211/*
212 * Local Bus Configuration & Clock Setup
213 */
Kim Phillipsc7190f02009-09-25 18:19:44 -0500214#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
215#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_LBC_LBCR 0x00040000
Becky Bruce0914f482010-06-17 11:37:18 -0500217#define CONFIG_FSL_ELBC 1
Dave Liu8bd522c2008-01-11 18:48:24 +0800218
219/*
220 * FLASH on the Local Bus
221 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200223#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
Dave Liu8bd522c2008-01-11 18:48:24 +0800225
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
Joe Hershberger6f681b72011-10-11 23:57:11 -0500227#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */
228#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
Dave Liu8bd522c2008-01-11 18:48:24 +0800229
Joe Hershberger6f681b72011-10-11 23:57:11 -0500230 /* Window base at flash base */
231#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500232#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
Dave Liu8bd522c2008-01-11 18:48:24 +0800233
Anton Vorontsov2e950042009-11-24 20:12:12 +0300234#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500235 | BR_PS_16 /* 16 bit port */ \
236 | BR_MS_GPCM /* MSEL = GPCM */ \
237 | BR_V) /* valid */
238#define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
239 | OR_UPM_XAM \
240 | OR_GPCM_CSNT \
241 | OR_GPCM_ACS_DIV2 \
242 | OR_GPCM_XACS \
243 | OR_GPCM_SCY_15 \
244 | OR_GPCM_TRLX_SET \
245 | OR_GPCM_EHTR_SET \
246 | OR_GPCM_EAD)
Dave Liu8bd522c2008-01-11 18:48:24 +0800247
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
Joe Hershberger6f681b72011-10-11 23:57:11 -0500249/* 127 64KB sectors and 8 8KB top sectors per device */
250#define CONFIG_SYS_MAX_FLASH_SECT 135
Dave Liu8bd522c2008-01-11 18:48:24 +0800251
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#undef CONFIG_SYS_FLASH_CHECKSUM
253#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
254#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Dave Liu8bd522c2008-01-11 18:48:24 +0800255
256/*
257 * NAND Flash on the Local Bus
258 */
Anton Vorontsov2e950042009-11-24 20:12:12 +0300259
260#ifdef CONFIG_NAND_SPL
261#define CONFIG_SYS_NAND_BASE 0xFFF00000
262#else
263#define CONFIG_SYS_NAND_BASE 0xE0600000
264#endif
265
Scott Woode8d3ca82010-08-30 18:04:52 -0500266#define CONFIG_MTD_DEVICE
267#define CONFIG_MTD_PARTITION
268#define CONFIG_CMD_MTDPARTS
269#define MTDIDS_DEFAULT "nand0=e0600000.flash"
Joe Hershberger6f681b72011-10-11 23:57:11 -0500270#define MTDPARTS_DEFAULT \
Scott Woode8d3ca82010-08-30 18:04:52 -0500271 "mtdparts=e0600000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)"
272
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273#define CONFIG_SYS_MAX_NAND_DEVICE 1
Dave Liu1ac57442008-11-04 14:55:06 +0800274#define CONFIG_MTD_NAND_VERIFY_WRITE 1
275#define CONFIG_CMD_NAND 1
276#define CONFIG_NAND_FSL_ELBC 1
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500277#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
278#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */
Dave Liu8bd522c2008-01-11 18:48:24 +0800279
Anton Vorontsov2e950042009-11-24 20:12:12 +0300280#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
281#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
282#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
283#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
284#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
285
286#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500287 | BR_DECC_CHK_GEN /* Use HW ECC */ \
Joe Hershberger6f681b72011-10-11 23:57:11 -0500288 | BR_PS_8 /* 8 bit port */ \
Dave Liu8bd522c2008-01-11 18:48:24 +0800289 | BR_MS_FCM /* MSEL = FCM */ \
Joe Hershberger6f681b72011-10-11 23:57:11 -0500290 | BR_V) /* valid */
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500291#define CONFIG_SYS_NAND_OR_PRELIM \
292 (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
Dave Liu8bd522c2008-01-11 18:48:24 +0800293 | OR_FCM_CSCT \
294 | OR_FCM_CST \
295 | OR_FCM_CHT \
296 | OR_FCM_SCY_1 \
297 | OR_FCM_TRLX \
Joe Hershberger6f681b72011-10-11 23:57:11 -0500298 | OR_FCM_EHTR)
Dave Liu8bd522c2008-01-11 18:48:24 +0800299 /* 0xFFFF8396 */
300
Anton Vorontsov2e950042009-11-24 20:12:12 +0300301#ifdef CONFIG_NAND_U_BOOT
302#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
303#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
304#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM
305#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM
306#else
307#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
308#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
309#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
310#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
311#endif
312
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500314#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
Dave Liu8bd522c2008-01-11 18:48:24 +0800315
Anton Vorontsov2e950042009-11-24 20:12:12 +0300316#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
317#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
318
319#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \
320 !defined(CONFIG_NAND_SPL)
321#define CONFIG_SYS_RAMBOOT
322#else
323#undef CONFIG_SYS_RAMBOOT
324#endif
325
Dave Liu8bd522c2008-01-11 18:48:24 +0800326/*
327 * Serial Port
328 */
329#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200330#define CONFIG_SYS_NS16550
331#define CONFIG_SYS_NS16550_SERIAL
332#define CONFIG_SYS_NS16550_REG_SIZE 1
Anton Vorontsov2e950042009-11-24 20:12:12 +0300333#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
Dave Liu8bd522c2008-01-11 18:48:24 +0800334
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200335#define CONFIG_SYS_BAUDRATE_TABLE \
Joe Hershberger6f681b72011-10-11 23:57:11 -0500336 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
Dave Liu8bd522c2008-01-11 18:48:24 +0800337
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200338#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
339#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
Dave Liu8bd522c2008-01-11 18:48:24 +0800340
341/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200342#define CONFIG_SYS_HUSH_PARSER
343#ifdef CONFIG_SYS_HUSH_PARSER
344#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Dave Liu8bd522c2008-01-11 18:48:24 +0800345#endif
346
347/* Pass open firmware flat tree */
348#define CONFIG_OF_LIBFDT 1
349#define CONFIG_OF_BOARD_SETUP 1
350#define CONFIG_OF_STDOUT_VIA_ALIAS 1
351
352/* I2C */
353#define CONFIG_HARD_I2C /* I2C with hardware support */
354#define CONFIG_FSL_I2C
Joe Hershberger6f681b72011-10-11 23:57:11 -0500355#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave addr */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200356#define CONFIG_SYS_I2C_SLAVE 0x7F
Joe Hershberger6f681b72011-10-11 23:57:11 -0500357#define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200358#define CONFIG_SYS_I2C_OFFSET 0x3000
359#define CONFIG_SYS_I2C2_OFFSET 0x3100
Dave Liu8bd522c2008-01-11 18:48:24 +0800360
361/*
362 * Board info - revision and where boot from
363 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200364#define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39
Dave Liu8bd522c2008-01-11 18:48:24 +0800365
366/*
367 * Config on-board RTC
368 */
369#define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200370#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
Dave Liu8bd522c2008-01-11 18:48:24 +0800371
372/*
373 * General PCI
374 * Addresses are mapped 1-1.
375 */
Joe Hershberger6f681b72011-10-11 23:57:11 -0500376#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
377#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
378#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200379#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
380#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
381#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
382#define CONFIG_SYS_PCI_IO_BASE 0x00000000
383#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
384#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
Dave Liu8bd522c2008-01-11 18:48:24 +0800385
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200386#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
387#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
388#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
Dave Liu8bd522c2008-01-11 18:48:24 +0800389
Anton Vorontsov8f11e342009-01-08 04:26:17 +0300390#define CONFIG_SYS_PCIE1_BASE 0xA0000000
391#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
392#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
393#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
394#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
395#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
396#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
397#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
398#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
399
400#define CONFIG_SYS_PCIE2_BASE 0xC0000000
401#define CONFIG_SYS_PCIE2_MEM_BASE 0xC0000000
402#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC0000000
403#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
404#define CONFIG_SYS_PCIE2_CFG_BASE 0xD0000000
405#define CONFIG_SYS_PCIE2_CFG_SIZE 0x01000000
406#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
407#define CONFIG_SYS_PCIE2_IO_PHYS 0xD1000000
408#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
409
Dave Liu8bd522c2008-01-11 18:48:24 +0800410#define CONFIG_PCI
Kim Phillipsbe9b56d2009-07-23 14:09:38 -0500411#define CONFIG_PCIE
Dave Liu8bd522c2008-01-11 18:48:24 +0800412
Dave Liu8bd522c2008-01-11 18:48:24 +0800413#define CONFIG_PCI_PNP /* do pci plug-and-play */
414
415#define CONFIG_EEPRO100
416#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200417#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
Dave Liu8bd522c2008-01-11 18:48:24 +0800418
Anton Vorontsov25f5f0d2008-07-08 21:00:04 +0400419#define CONFIG_HAS_FSL_DR_USB
Vivek Mahajan6823e9b2009-05-25 17:23:17 +0530420#define CONFIG_SYS_SCCR_USBDRCM 3
421
422#define CONFIG_CMD_USB
423#define CONFIG_USB_STORAGE
424#define CONFIG_USB_EHCI
425#define CONFIG_USB_EHCI_FSL
Joe Hershberger6f681b72011-10-11 23:57:11 -0500426#define CONFIG_USB_PHY_TYPE "utmi"
Vivek Mahajan6823e9b2009-05-25 17:23:17 +0530427#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
Anton Vorontsov25f5f0d2008-07-08 21:00:04 +0400428
Dave Liu8bd522c2008-01-11 18:48:24 +0800429/*
430 * TSEC
431 */
432#define CONFIG_TSEC_ENET /* TSEC ethernet support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200433#define CONFIG_SYS_TSEC1_OFFSET 0x24000
Joe Hershberger6f681b72011-10-11 23:57:11 -0500434#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200435#define CONFIG_SYS_TSEC2_OFFSET 0x25000
Joe Hershberger6f681b72011-10-11 23:57:11 -0500436#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
Dave Liu8bd522c2008-01-11 18:48:24 +0800437
438/*
439 * TSEC ethernet configuration
440 */
441#define CONFIG_MII 1 /* MII PHY management */
442#define CONFIG_TSEC1 1
443#define CONFIG_TSEC1_NAME "eTSEC0"
444#define CONFIG_TSEC2 1
445#define CONFIG_TSEC2_NAME "eTSEC1"
446#define TSEC1_PHY_ADDR 0
447#define TSEC2_PHY_ADDR 1
448#define TSEC1_PHYIDX 0
449#define TSEC2_PHYIDX 0
450#define TSEC1_FLAGS TSEC_GIGABIT
451#define TSEC2_FLAGS TSEC_GIGABIT
452
453/* Options are: eTSEC[0-1] */
454#define CONFIG_ETHPRIME "eTSEC1"
455
456/*
Kim Phillips730e7922008-03-28 14:31:23 -0500457 * SATA
458 */
459#define CONFIG_LIBATA
460#define CONFIG_FSL_SATA
461
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200462#define CONFIG_SYS_SATA_MAX_DEVICE 2
Kim Phillips730e7922008-03-28 14:31:23 -0500463#define CONFIG_SATA1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200464#define CONFIG_SYS_SATA1_OFFSET 0x18000
Joe Hershberger6f681b72011-10-11 23:57:11 -0500465#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
466#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
Kim Phillips730e7922008-03-28 14:31:23 -0500467#define CONFIG_SATA2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200468#define CONFIG_SYS_SATA2_OFFSET 0x19000
Joe Hershberger6f681b72011-10-11 23:57:11 -0500469#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
470#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
Kim Phillips730e7922008-03-28 14:31:23 -0500471
472#ifdef CONFIG_FSL_SATA
473#define CONFIG_LBA48
474#define CONFIG_CMD_SATA
475#define CONFIG_DOS_PARTITION
476#define CONFIG_CMD_EXT2
477#endif
478
479/*
Dave Liu8bd522c2008-01-11 18:48:24 +0800480 * Environment
481 */
Anton Vorontsov2e950042009-11-24 20:12:12 +0300482#if defined(CONFIG_NAND_U_BOOT)
483 #define CONFIG_ENV_IS_IN_NAND 1
484 #define CONFIG_ENV_OFFSET (512 * 1024)
485 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
486 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
487 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
488 #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4)
489 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
490 CONFIG_ENV_RANGE)
491#elif !defined(CONFIG_SYS_RAMBOOT)
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200492 #define CONFIG_ENV_IS_IN_FLASH 1
Joe Hershberger6f681b72011-10-11 23:57:11 -0500493 #define CONFIG_ENV_ADDR \
494 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200495 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
496 #define CONFIG_ENV_SIZE 0x2000
Dave Liu8bd522c2008-01-11 18:48:24 +0800497#else
Joe Hershberger6f681b72011-10-11 23:57:11 -0500498 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200499 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200500 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200501 #define CONFIG_ENV_SIZE 0x2000
Dave Liu8bd522c2008-01-11 18:48:24 +0800502#endif
503
504#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200505#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Dave Liu8bd522c2008-01-11 18:48:24 +0800506
507/*
508 * BOOTP options
509 */
510#define CONFIG_BOOTP_BOOTFILESIZE
511#define CONFIG_BOOTP_BOOTPATH
512#define CONFIG_BOOTP_GATEWAY
513#define CONFIG_BOOTP_HOSTNAME
514
515/*
516 * Command line configuration.
517 */
518#include <config_cmd_default.h>
519
520#define CONFIG_CMD_PING
521#define CONFIG_CMD_I2C
522#define CONFIG_CMD_MII
523#define CONFIG_CMD_DATE
524#define CONFIG_CMD_PCI
525
Anton Vorontsov2e950042009-11-24 20:12:12 +0300526#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT)
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500527 #undef CONFIG_CMD_SAVEENV
Dave Liu8bd522c2008-01-11 18:48:24 +0800528 #undef CONFIG_CMD_LOADS
529#endif
530
531#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Joe Hershberger6f681b72011-10-11 23:57:11 -0500532#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Dave Liu8bd522c2008-01-11 18:48:24 +0800533
534#undef CONFIG_WATCHDOG /* watchdog disabled */
535
536/*
537 * Miscellaneous configurable options
538 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200539#define CONFIG_SYS_LONGHELP /* undef to save memory */
540#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
541#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Dave Liu8bd522c2008-01-11 18:48:24 +0800542
543#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200544 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Dave Liu8bd522c2008-01-11 18:48:24 +0800545#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200546 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Dave Liu8bd522c2008-01-11 18:48:24 +0800547#endif
548
Joe Hershberger6f681b72011-10-11 23:57:11 -0500549 /* Print Buffer Size */
550#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
551#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
552 /* Boot Argument Buffer Size */
553#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
554#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
Dave Liu8bd522c2008-01-11 18:48:24 +0800555
556/*
557 * For booting Linux, the board info and command line data
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700558 * have to be in the first 256 MB of memory, since this is
Dave Liu8bd522c2008-01-11 18:48:24 +0800559 * the maximum mapped by the Linux kernel during initialization.
560 */
Joe Hershberger6f681b72011-10-11 23:57:11 -0500561#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
Dave Liu8bd522c2008-01-11 18:48:24 +0800562
563/*
564 * Core HID Setup
565 */
Kim Phillips1a2e2032010-04-20 19:37:54 -0500566#define CONFIG_SYS_HID0_INIT 0x000000000
567#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
568 HID0_ENABLE_INSTRUCTION_CACHE | \
Dave Liu8bd522c2008-01-11 18:48:24 +0800569 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200570#define CONFIG_SYS_HID2 HID2_HBE
Dave Liu8bd522c2008-01-11 18:48:24 +0800571
572/*
573 * MMU Setup
574 */
Becky Bruce31d82672008-05-08 19:02:12 -0500575#define CONFIG_HIGH_BATS 1 /* High BATs supported */
Dave Liu8bd522c2008-01-11 18:48:24 +0800576
577/* DDR: cache cacheable */
Joe Hershberger6f681b72011-10-11 23:57:11 -0500578#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500579 | BATL_PP_RW \
Joe Hershberger6f681b72011-10-11 23:57:11 -0500580 | BATL_MEMCOHERENCE)
581#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
582 | BATU_BL_128M \
583 | BATU_VS \
584 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200585#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
586#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
Dave Liu8bd522c2008-01-11 18:48:24 +0800587
588/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
Joe Hershberger6f681b72011-10-11 23:57:11 -0500589#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500590 | BATL_PP_RW \
Joe Hershberger6f681b72011-10-11 23:57:11 -0500591 | BATL_CACHEINHIBIT \
592 | BATL_GUARDEDSTORAGE)
593#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
594 | BATU_BL_8M \
595 | BATU_VS \
596 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200597#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
598#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
Dave Liu8bd522c2008-01-11 18:48:24 +0800599
600/* FLASH: icache cacheable, but dcache-inhibit and guarded */
Joe Hershberger6f681b72011-10-11 23:57:11 -0500601#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500602 | BATL_PP_RW \
Joe Hershberger6f681b72011-10-11 23:57:11 -0500603 | BATL_MEMCOHERENCE)
604#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \
605 | BATU_BL_32M \
606 | BATU_VS \
607 | BATU_VP)
608#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500609 | BATL_PP_RW \
Joe Hershberger6f681b72011-10-11 23:57:11 -0500610 | BATL_CACHEINHIBIT \
611 | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200612#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
Dave Liu8bd522c2008-01-11 18:48:24 +0800613
614/* Stack in dcache: cacheable, no memory coherence */
Joe Hershberger72cd4082011-10-11 23:57:28 -0500615#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
Joe Hershberger6f681b72011-10-11 23:57:11 -0500616#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR \
617 | BATU_BL_128K \
618 | BATU_VS \
619 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200620#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
621#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
Dave Liu8bd522c2008-01-11 18:48:24 +0800622
623/* PCI MEM space: cacheable */
Joe Hershberger6f681b72011-10-11 23:57:11 -0500624#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI_MEM_PHYS \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500625 | BATL_PP_RW \
Joe Hershberger6f681b72011-10-11 23:57:11 -0500626 | BATL_MEMCOHERENCE)
627#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI_MEM_PHYS \
628 | BATU_BL_256M \
629 | BATU_VS \
630 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200631#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
632#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
Dave Liu8bd522c2008-01-11 18:48:24 +0800633
634/* PCI MMIO space: cache-inhibit and guarded */
Joe Hershberger6f681b72011-10-11 23:57:11 -0500635#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI_MMIO_PHYS \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500636 | BATL_PP_RW \
Joe Hershberger6f681b72011-10-11 23:57:11 -0500637 | BATL_CACHEINHIBIT \
638 | BATL_GUARDEDSTORAGE)
639#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI_MMIO_PHYS \
640 | BATU_BL_256M \
641 | BATU_VS \
642 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200643#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
644#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
Dave Liu8bd522c2008-01-11 18:48:24 +0800645
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200646#define CONFIG_SYS_IBAT6L 0
647#define CONFIG_SYS_IBAT6U 0
648#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
649#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
Dave Liu8bd522c2008-01-11 18:48:24 +0800650
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200651#define CONFIG_SYS_IBAT7L 0
652#define CONFIG_SYS_IBAT7U 0
653#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
654#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Dave Liu8bd522c2008-01-11 18:48:24 +0800655
Dave Liu8bd522c2008-01-11 18:48:24 +0800656#if defined(CONFIG_CMD_KGDB)
657#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
658#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
659#endif
660
661/*
662 * Environment Configuration
663 */
664
665#define CONFIG_ENV_OVERWRITE
666
667#if defined(CONFIG_TSEC_ENET)
668#define CONFIG_HAS_ETH0
Dave Liu8bd522c2008-01-11 18:48:24 +0800669#define CONFIG_HAS_ETH1
Dave Liu8bd522c2008-01-11 18:48:24 +0800670#endif
671
672#define CONFIG_BAUDRATE 115200
673
Kim Phillips79f516b2009-08-21 16:34:38 -0500674#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
Dave Liu8bd522c2008-01-11 18:48:24 +0800675
676#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
677#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
678
679#define CONFIG_EXTRA_ENV_SETTINGS \
Joe Hershberger6f681b72011-10-11 23:57:11 -0500680 "netdev=eth0\0" \
681 "consoledev=ttyS0\0" \
682 "ramdiskaddr=1000000\0" \
683 "ramdiskfile=ramfs.83xx\0" \
684 "fdtaddr=780000\0" \
685 "fdtfile=mpc8315erdb.dtb\0" \
686 "usb_phy_type=utmi\0" \
687 ""
Dave Liu8bd522c2008-01-11 18:48:24 +0800688
689#define CONFIG_NFSBOOTCOMMAND \
Joe Hershberger6f681b72011-10-11 23:57:11 -0500690 "setenv bootargs root=/dev/nfs rw " \
691 "nfsroot=$serverip:$rootpath " \
692 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
693 "$netdev:off " \
694 "console=$consoledev,$baudrate $othbootargs;" \
695 "tftp $loadaddr $bootfile;" \
696 "tftp $fdtaddr $fdtfile;" \
697 "bootm $loadaddr - $fdtaddr"
Dave Liu8bd522c2008-01-11 18:48:24 +0800698
699#define CONFIG_RAMBOOTCOMMAND \
Joe Hershberger6f681b72011-10-11 23:57:11 -0500700 "setenv bootargs root=/dev/ram rw " \
701 "console=$consoledev,$baudrate $othbootargs;" \
702 "tftp $ramdiskaddr $ramdiskfile;" \
703 "tftp $loadaddr $bootfile;" \
704 "tftp $fdtaddr $fdtfile;" \
705 "bootm $loadaddr $ramdiskaddr $fdtaddr"
Dave Liu8bd522c2008-01-11 18:48:24 +0800706
707
708#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
709
710#endif /* __CONFIG_H */