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Phil Edworthy7fbeb642011-06-01 07:35:13 +01001/*
Phil Edworthyefa4e1b2011-06-09 16:22:43 +01002 * Configuation settings for the Renesas RSK2+SH7264 board
Phil Edworthy7fbeb642011-06-01 07:35:13 +01003 *
4 * Copyright (C) 2011 Renesas Electronics Europe Ltd.
5 * Copyright (C) 2008 Nobuhiro Iwamatsu
6 * Copyright (C) 2008 Renesas Solutions Corp.
7 *
8 * This file is released under the terms of GPL v2 and any later version.
9 * See the file COPYING in the root directory of the source tree for details.
10 */
11
12#ifndef __RSK7264_H
13#define __RSK7264_H
14
15#undef DEBUG
16#define CONFIG_SH 1
17#define CONFIG_SH2 1
18#define CONFIG_SH2A 1
19#define CONFIG_CPU_SH7264 1
Phil Edworthyefa4e1b2011-06-09 16:22:43 +010020#define CONFIG_RSK7264 1
Phil Edworthy7fbeb642011-06-01 07:35:13 +010021
Phil Edworthyefa4e1b2011-06-09 16:22:43 +010022#ifndef _CONFIG_CMD_DEFAULT_H
23# include <config_cmd_default.h>
24#endif
Phil Edworthy7fbeb642011-06-01 07:35:13 +010025
26#define CONFIG_BAUDRATE 115200
27#define CONFIG_BOOTARGS "console=ttySC3,115200"
28#define CONFIG_BOOTDELAY 3
Phil Edworthyefa4e1b2011-06-09 16:22:43 +010029#define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE }
Phil Edworthy7fbeb642011-06-01 07:35:13 +010030
Phil Edworthyefa4e1b2011-06-09 16:22:43 +010031#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */
Phil Edworthy7fbeb642011-06-01 07:35:13 +010032#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
33#define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */
34#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
35#define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */
Phil Edworthy7fbeb642011-06-01 07:35:13 +010036
Phil Edworthyefa4e1b2011-06-09 16:22:43 +010037/* Serial */
Phil Edworthy7fbeb642011-06-01 07:35:13 +010038#define CONFIG_SCIF_CONSOLE 1
39#define CONFIG_CONS_SCIF3 1
40
Phil Edworthyefa4e1b2011-06-09 16:22:43 +010041/* Memory */
42/* u-boot relocated to top 256KB of ram */
43#define CONFIG_SYS_TEXT_BASE 0x0CFC0000
44#define CONFIG_SYS_SDRAM_BASE 0x0C000000
Phil Edworthy7fbeb642011-06-01 07:35:13 +010045#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
46
Phil Edworthyefa4e1b2011-06-09 16:22:43 +010047#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
48#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
Phil Edworthy7fbeb642011-06-01 07:35:13 +010049#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
Phil Edworthyefa4e1b2011-06-09 16:22:43 +010050#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
51#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4*1024*1024)
Phil Edworthy7fbeb642011-06-01 07:35:13 +010052
Phil Edworthyefa4e1b2011-06-09 16:22:43 +010053/* Flash */
Phil Edworthy7fbeb642011-06-01 07:35:13 +010054#define CONFIG_FLASH_CFI_DRIVER
55#define CONFIG_SYS_FLASH_CFI
56#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
Phil Edworthyefa4e1b2011-06-09 16:22:43 +010057#define CONFIG_SYS_FLASH_BASE 0x20000000 /* Non-cached */
Phil Edworthy7fbeb642011-06-01 07:35:13 +010058#define CONFIG_SYS_MAX_FLASH_BANKS 1
Phil Edworthyefa4e1b2011-06-09 16:22:43 +010059#define CONFIG_SYS_MAX_FLASH_SECT 512
Phil Edworthy7fbeb642011-06-01 07:35:13 +010060
Phil Edworthyefa4e1b2011-06-09 16:22:43 +010061#define CONFIG_ENV_IS_IN_FLASH 1
62#define CONFIG_ENV_OFFSET (128 * 1024)
63#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
Phil Edworthy7fbeb642011-06-01 07:35:13 +010064#define CONFIG_ENV_SECT_SIZE (128 * 1024)
65#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
Phil Edworthy7fbeb642011-06-01 07:35:13 +010066
67/* Board Clock */
68#define CONFIG_SYS_CLK_FREQ 33333333
Phil Edworthyefa4e1b2011-06-09 16:22:43 +010069#define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */
Phil Edworthy7fbeb642011-06-01 07:35:13 +010070#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
71
72/* Network interface */
Phil Edworthy7fbeb642011-06-01 07:35:13 +010073#define CONFIG_SMC911X
74#define CONFIG_SMC911X_16_BIT
Phil Edworthyefa4e1b2011-06-09 16:22:43 +010075#define CONFIG_SMC911X_BASE 0x28000000
Phil Edworthy7fbeb642011-06-01 07:35:13 +010076
77#endif /* __RSK7264_H */