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wdenkce23b152002-10-24 23:29:41 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * (C) Copyright 2000-2005
wdenkce23b152002-10-24 23:29:41 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
37#define CONFIG_R360MPI 1
38
39#define CONFIG_LCD
40#undef CONFIG_EDT32F10
41#define CONFIG_SHARP_LQ057Q3DC02
42
wdenkd791b1d2003-04-20 14:04:18 +000043#define CONFIG_SPLASH_SCREEN
44
wdenkce23b152002-10-24 23:29:41 +000045#define MPC8XX_FACT 1 /* Multiply by 1 */
46#define MPC8XX_XIN 50000000 /* 50 MHz in */
47#define CONFIG_8xx_GCLK_FREQ 50000000 /* define if can't use get_gclk_freq */
48
49#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
50#undef CONFIG_8xx_CONS_SMC2
51#undef CONFIG_8xx_CONS_NONE
wdenk4a6fd342003-04-12 23:38:12 +000052#define CONFIG_BAUDRATE 115200 /* console baudrate in bps */
wdenkce23b152002-10-24 23:29:41 +000053#if 0
wdenkcb4dbb72003-07-16 16:40:22 +000054#define CONFIG_BOOTDELAY 0 /* immediate boot */
wdenkce23b152002-10-24 23:29:41 +000055#else
56#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
57#endif
58
59#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
60
61#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
62
63#undef CONFIG_BOOTARGS
64#define CONFIG_BOOTCOMMAND \
65 "bootp; " \
66 "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
67 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
68 "bootm"
69
70#undef CONFIG_SCC1_ENET
71#define CONFIG_SCC2_ENET
72
73#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
74#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
75
76#define CONFIG_MISC_INIT_R /* have misc_init_r() function */
77
78#undef CONFIG_WATCHDOG /* watchdog disabled */
79
wdenk4a6fd342003-04-12 23:38:12 +000080#define CONFIG_CAN_DRIVER /* CAN Driver support enabled */
wdenkce23b152002-10-24 23:29:41 +000081
82#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
83
84#define CONFIG_MAC_PARTITION
85#define CONFIG_DOS_PARTITION
86
87#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
88
89#define CONFIG_HARD_I2C 1 /* To I2C with hardware support */
90#undef CONFIG_SORT_I2C /* To I2C with software support */
91#define CFG_I2C_SPEED 4700 /* I2C speed and slave address */
92#define CFG_I2C_SLAVE 0x7F
93
94/*
95 * Software (bit-bang) I2C driver configuration
96 */
97#define PB_SCL 0x00000020 /* PB 26 */
98#define PB_SDA 0x00000010 /* PB 27 */
99
100#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
101#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
102#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
103#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
104#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
105 else immr->im_cpm.cp_pbdat &= ~PB_SDA
106#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
107 else immr->im_cpm.cp_pbdat &= ~PB_SCL
108#define I2C_DELAY udelay(50)
109
wdenk4a6fd342003-04-12 23:38:12 +0000110#define CFG_I2C_LCD_ADDR 0x8 /* LCD Control */
111#define CFG_I2C_KEY_ADDR 0x9 /* Keyboard coprocessor */
112#define CFG_I2C_TEM_ADDR 0x49 /* Temperature Sensors */
wdenkce23b152002-10-24 23:29:41 +0000113
114#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
wdenkd791b1d2003-04-20 14:04:18 +0000115 CFG_CMD_BMP | \
wdenk414eec32005-04-02 22:37:54 +0000116 CFG_CMD_BSP | \
wdenkce23b152002-10-24 23:29:41 +0000117 CFG_CMD_DATE | \
wdenk414eec32005-04-02 22:37:54 +0000118 CFG_CMD_DHCP | \
wdenkce23b152002-10-24 23:29:41 +0000119 CFG_CMD_I2C | \
120 CFG_CMD_IDE | \
wdenkcb4dbb72003-07-16 16:40:22 +0000121 CFG_CMD_JFFS2 | \
wdenk414eec32005-04-02 22:37:54 +0000122 CFG_CMD_NFS | \
wdenkce23b152002-10-24 23:29:41 +0000123 CFG_CMD_PCMCIA | \
wdenk414eec32005-04-02 22:37:54 +0000124 CFG_CMD_SNTP )
wdenkce23b152002-10-24 23:29:41 +0000125
126/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
127#include <cmd_confdefs.h>
128
129/*
130 * Miscellaneous configurable options
131 */
wdenkcb4dbb72003-07-16 16:40:22 +0000132#define CFG_DEVICE_NULLDEV 1 /* we need the null device */
133#define CFG_CONSOLE_IS_IN_ENV 1 /* must set console from env */
134
wdenkce23b152002-10-24 23:29:41 +0000135#define CFG_LONGHELP /* undef to save memory */
136#define CFG_PROMPT "=> " /* Monitor Command Prompt */
137#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
138#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
139#else
140#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
141#endif
142#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
143#define CFG_MAXARGS 16 /* max number of command args */
144#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
145
146#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
147#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
148
149#define CFG_LOAD_ADDR 0x100000 /* default load address */
150
151#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
152
153#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
154
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200155/*
156 * JFFS2 partitions
157 */
158/* No command line, one static partition
159 * use all the space starting at offset 3MB*/
160#undef CONFIG_JFFS2_CMDLINE
161#define CONFIG_JFFS2_DEV "nor0"
162#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
163#define CONFIG_JFFS2_PART_OFFSET 0x00300000
164
165/* mtdparts command line support */
166/*
167#define CONFIG_JFFS2_CMDLINE
168#define MTDIDS_DEFAULT "nor0=r360-0"
169#define MTDPARTS_DEFAULT "mtdparts=r360-0:-@3m(user)"
170*/
wdenkcb4dbb72003-07-16 16:40:22 +0000171
wdenkce23b152002-10-24 23:29:41 +0000172/*
173 * Low Level Configuration Settings
174 * (address mappings, register initial values, etc.)
175 * You should know what you are doing if you make changes here.
176 */
177/*-----------------------------------------------------------------------
178 * Internal Memory Mapped Register
179 */
180#define CFG_IMMR 0xFF000000
181
182/*-----------------------------------------------------------------------
183 * Definitions for initial stack pointer and data area (in DPRAM)
184 */
185#define CFG_INIT_RAM_ADDR CFG_IMMR
186#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
187#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
188#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
189#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
190
191/*-----------------------------------------------------------------------
192 * Start addresses for the final memory configuration
193 * (Set up by the startup code)
194 * Please note that CFG_SDRAM_BASE _must_ start at 0
195 */
196#define CFG_SDRAM_BASE 0x00000000
197#define CFG_FLASH_BASE 0x40000000
198#if defined(DEBUG)
199#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
200#else
201#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
202#endif
203#define CFG_MONITOR_BASE CFG_FLASH_BASE
204#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
205
206/*
207 * For booting Linux, the board info and command line data
208 * have to be in the first 8 MB of memory, since this is
209 * the maximum mapped by the Linux kernel during initialization.
210 */
211#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
212
213/*-----------------------------------------------------------------------
214 * FLASH organization
215 */
216#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
217#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
218
219#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
220#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
221
222#define CFG_ENV_IS_IN_FLASH 1
223#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment */
224#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment sector */
225#define CFG_ENV_SIZE 0x4000 /* Used Size of Environment sector */
226
227/*-----------------------------------------------------------------------
228 * Cache Configuration
229 */
230#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
231#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
232#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
233#endif
234
235/*-----------------------------------------------------------------------
236 * SYPCR - System Protection Control 11-9
237 * SYPCR can only be written once after reset!
238 *-----------------------------------------------------------------------
239 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
240 */
241#if defined(CONFIG_WATCHDOG)
242#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
243 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
244#else
245#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
246#endif
247
248/*-----------------------------------------------------------------------
249 * SIUMCR - SIU Module Configuration 11-6
250 *-----------------------------------------------------------------------
251 * PCMCIA config., multi-function pin tri-state
252 */
wdenkce23b152002-10-24 23:29:41 +0000253#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkce23b152002-10-24 23:29:41 +0000254
255/*-----------------------------------------------------------------------
256 * TBSCR - Time Base Status and Control 11-26
257 *-----------------------------------------------------------------------
258 * Clear Reference Interrupt Status, Timebase freezing enabled
259 */
260#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
261
262/*-----------------------------------------------------------------------
263 * RTCSC - Real-Time Clock Status and Control Register 11-27
264 *-----------------------------------------------------------------------
265 */
266#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
267
268/*-----------------------------------------------------------------------
269 * PISCR - Periodic Interrupt Status and Control 11-31
270 *-----------------------------------------------------------------------
271 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
272 */
273#define CFG_PISCR (PISCR_PS | PISCR_PITF)
274
275/*-----------------------------------------------------------------------
276 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
277 *-----------------------------------------------------------------------
278 * Reset PLL lock status sticky bit, timer expired status bit and timer
279 * interrupt status bit
280 *
281 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
282 */
283#ifdef CONFIG_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
284#define CFG_PLPRCR \
285 ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
286#else /* up to 50 MHz we use a 1:1 clock */
287#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
288#endif /* CONFIG_80MHz */
289
290/*-----------------------------------------------------------------------
291 * SCCR - System Clock and reset Control Register 15-27
292 *-----------------------------------------------------------------------
293 * Set clock output, timebase and RTC source and divider,
294 * power management and some other internal clocks
295 */
296#define SCCR_MASK SCCR_EBDF11
297#define CFG_SCCR (SCCR_TBS | \
298 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
299 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
300 SCCR_DFALCD00)
301
302/*-----------------------------------------------------------------------
303 * PCMCIA stuff
304 *-----------------------------------------------------------------------
305 *
306 */
307#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
308#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
309#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
310#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
311#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
312#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
313#define CFG_PCMCIA_IO_ADDR (0xEC000000)
314#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
315
316/*-----------------------------------------------------------------------
317 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
318 *-----------------------------------------------------------------------
319 */
320
321#if 1
322#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
323
324#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
325#undef CONFIG_IDE_LED /* LED for ide not supported */
326#undef CONFIG_IDE_RESET /* reset for ide not supported */
327
328#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
329#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
330
331#define CFG_ATA_IDE0_OFFSET 0x0000
332
333#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
334
335/* Offset for data I/O */
336#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
337
338/* Offset for normal register accesses */
339#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
340
341/* Offset for alternate registers */
342#define CFG_ATA_ALT_OFFSET 0x0100
343#endif
344
345/*-----------------------------------------------------------------------
346 *
347 *-----------------------------------------------------------------------
348 *
349 */
wdenk3b57fe02003-05-30 12:48:29 +0000350#define CFG_DER 0
wdenkce23b152002-10-24 23:29:41 +0000351
352/*
353 * Init Memory Controller:
354 *
355 * BR0/1 and OR0/1 (FLASH)
356 */
357
358#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
359
360/* used to re-map FLASH both when starting from SRAM or FLASH:
361 * restrict access enough to keep SRAM working (if any)
362 * but not too much to meddle with FLASH accesses
363 */
364#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
365#define CFG_PRELIM_OR_AM 0xFF000000 /* OR addr mask */
366
367/*
368 * FLASH timing:
369 */
370#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_SCY_7_CLK | OR_BI)
371
372#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
373#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
374#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
375
376
377/*
wdenk4a6fd342003-04-12 23:38:12 +0000378 * BR2 and OR2 (SDRAM)
wdenkce23b152002-10-24 23:29:41 +0000379 *
380 */
wdenk4a6fd342003-04-12 23:38:12 +0000381#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
wdenkce23b152002-10-24 23:29:41 +0000382#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
383
wdenk4a6fd342003-04-12 23:38:12 +0000384#define CFG_PRELIM_OR2_AM 0xF8000000 /* OR addr mask */
wdenkce23b152002-10-24 23:29:41 +0000385
386/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
387#define CFG_OR_TIMING_SDRAM (OR_ACS_DIV1 | OR_CSNT_SAM | \
388 OR_SCY_0_CLK | OR_G5LS)
389
wdenk4a6fd342003-04-12 23:38:12 +0000390#define CFG_OR2_PRELIM (CFG_PRELIM_OR2_AM | CFG_OR_TIMING_SDRAM )
391#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
392
393/*
394 * BR3 and OR3 (CAN Controller)
395 */
396#ifdef CONFIG_CAN_DRIVER
397#define CFG_CAN_BASE 0xC0000000 /* CAN base address */
398#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
399#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA |OR_BI)
400#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \
401 BR_PS_8 | BR_MS_UPMB | BR_V)
402#endif /* CONFIG_CAN_DRIVER */
wdenkce23b152002-10-24 23:29:41 +0000403
404
405/*
406 * Memory Periodic Timer Prescaler
407 *
408 * The Divider for PTA (refresh timer) configuration is based on an
409 * example SDRAM configuration (64 MBit, one bank). The adjustment to
410 * the number of chip selects (NCS) and the actually needed refresh
411 * rate is done by setting MPTPR.
412 *
413 * PTA is calculated from
414 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
415 *
416 * gclk CPU clock (not bus clock!)
417 * Trefresh Refresh cycle * 4 (four word bursts used)
418 *
419 * 4096 Rows from SDRAM example configuration
420 * 1000 factor s -> ms
421 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
422 * 4 Number of refresh cycles per period
423 * 64 Refresh cycle in ms per number of rows
424 * --------------------------------------------
425 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
426 *
427 * 50 MHz => 50.000.000 / Divider = 98
428 * 66 Mhz => 66.000.000 / Divider = 129
429 * 80 Mhz => 80.000.000 / Divider = 156
430 */
431#if defined(CONFIG_80MHz)
432#define CFG_MAMR_PTA 156
433#elif defined(CONFIG_66MHz)
434#define CFG_MAMR_PTA 129
435#else /* 50 MHz */
436#define CFG_MAMR_PTA 98
437#endif /*CONFIG_??MHz */
438
439/*
440 * For 16 MBit, refresh rates could be 31.3 us
441 * (= 64 ms / 2K = 125 / quad bursts).
442 * For a simpler initialization, 15.6 us is used instead.
443 *
444 * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
445 * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
446 */
447#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
448#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
449
450/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
451#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
452#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
453
454/*
455 * MAMR settings for SDRAM
456 */
457
458/* 8 column SDRAM */
459#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
460 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
461 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
462/* 9 column SDRAM */
463#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
464 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
465 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
466
467
468/*
469 * Internal Definitions
470 *
471 * Boot Flags
472 */
473#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
474#define BOOTFLAG_WARM 0x02 /* Software reboot */
475
476#endif /* __CONFIG_H */