blob: 7cb10fb01e01da0e0ca35a7c22e4d776d4b2e1d9 [file] [log] [blame]
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +00001/*
2 * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
3 * (C) Copyright 2010 DAVE Srl <www.dave.eu>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19/*
20 * ifm AC14xx (MPC5121e based) board configuration file
21 */
22
23#ifndef __CONFIG_H
24#define __CONFIG_H
25
26#define CONFIG_AC14XX 1
27/*
28 * Memory map for the ifm AC14xx board:
29 *
30 * 0x0000_0000-0x0FFF_FFFF DDR RAM (256 MB)
31 * 0x3000_0000-0x3001_FFFF On Chip SRAM (128 KB)
32 * 0x8000_0000-0x803F_FFFF IMMR (4 MB)
33 * 0xE000_0000-0xEFFF_FFFF several LPB attached hardware (CSx)
34 * 0xFC00_0000-0xFFFF_FFFF NOR Boot FLASH (64 MB)
35 */
36
37/*
38 * High Level Configuration Options
39 */
40#define CONFIG_E300 1 /* E300 Family */
41#define CONFIG_MPC512X 1 /* MPC512X family */
42
43#define CONFIG_SYS_TEXT_BASE 0xFFF00000
44
45#if defined(CONFIG_VIDEO)
46#define CONFIG_CFB_CONSOLE
47#define CONFIG_VGA_AS_SINGLE_DEVICE
48#endif
49
50#define CONFIG_SYS_MPC512X_CLKIN 25000000 /* in Hz */
51#define SCFR1_IPS_DIV 2
52#define SCFR1_LPC_DIV 2
53#define SCFR1_NFC_DIV 2
54#define SCFR1_DIU_DIV 240
55
56#define CONFIG_MISC_INIT_R
57
58#define CONFIG_SYS_IMMR 0x80000000
59#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR + 0x2100)
60
61/* more aggressive 'mtest' over a wider address range */
62#define CONFIG_SYS_ALT_MEMTEST
63#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest region */
64#define CONFIG_SYS_MEMTEST_END 0x0FE00000
65
66/*
67 * DDR Setup - manually set all parameters as there's no SPD etc.
68 */
69#define CONFIG_SYS_DDR_SIZE 256 /* MB */
70#define CONFIG_SYS_DDR_BASE 0x00000000
71#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
72#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000
73
74/*
75 * DDR Controller Configuration XXX TODO
76 *
77 * SYS_CFG:
78 * [31:31] MDDRC Soft Reset: Diabled
79 * [30:30] DRAM CKE pin: Enabled
80 * [29:29] DRAM CLK: Enabled
81 * [28:28] Command Mode: Enabled (For initialization only)
82 * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10]
83 * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10]
84 * [20:19] Read Test: DON'T USE
85 * [18:18] Self Refresh: Enabled
86 * [17:17] 16bit Mode: Disabled
87 * [16:13] Ready Delay: 2
88 * [12:12] Half DQS Delay: Disabled
89 * [11:11] Quarter DQS Delay: Disabled
90 * [10:08] Write Delay: 2
91 * [07:07] Early ODT: Disabled
92 * [06:06] On DIE Termination: Disabled
93 * [05:05] FIFO Overflow Clear: DON'T USE here
94 * [04:04] FIFO Underflow Clear: DON'T USE here
95 * [03:03] FIFO Overflow Pending: DON'T USE here
96 * [02:02] FIFO Underlfow Pending: DON'T USE here
97 * [01:01] FIFO Overlfow Enabled: Enabled
98 * [00:00] FIFO Underflow Enabled: Enabled
99 * TIME_CFG0
100 * [31:16] DRAM Refresh Time: 0 CSB clocks
101 * [15:8] DRAM Command Time: 0 CSB clocks
102 * [07:00] DRAM Precharge Time: 0 CSB clocks
103 * TIME_CFG1
104 * [31:26] DRAM tRFC:
105 * [25:21] DRAM tWR1:
106 * [20:17] DRAM tWRT1:
107 * [16:11] DRAM tDRR:
108 * [10:05] DRAM tRC:
109 * [04:00] DRAM tRAS:
110 * TIME_CFG2
111 * [31:28] DRAM tRCD:
112 * [27:23] DRAM tFAW:
113 * [22:19] DRAM tRTW1:
114 * [18:15] DRAM tCCD:
115 * [14:10] DRAM tRTP:
116 * [09:05] DRAM tRP:
117 * [04:00] DRAM tRPA
118 */
119
120/*
121 * NOTE: although this board uses DDR1 only, the common source brings defaults
122 * for DDR2 init sequences, that's why we have to keep those here as well
123 */
124
125/* DDR1 -- 32bit, drive strength (pad configuration) 3 for control and data */
126#define CONFIG_SYS_IOCTRL_MUX_DDR ((0 << 6) | (3 << 3) | (3 << 0))
127
128#define CONFIG_SYS_MDDRC_SYS_CFG (/* 0xEAA09100 */ 0 \
129 | (1 << 31) /* RST_B */ \
130 | (1 << 30) /* CKE */ \
131 | (1 << 29) /* CLK_ON */ \
132 | (0 << 28) /* CMD_MODE */ \
133 | (5 << 25) /* DRAM_ROW_SELECT */ \
134 | (5 << 21) /* DRAM_BANK_SELECT */ \
135 | (0 << 18) /* SELF_REF_EN */ \
136 | (0 << 17) /* 16BIT_MODE */ \
137 | (4 << 13) /* RDLY */ \
138 | (1 << 12) /* HALF_DQS_DLY */ \
139 | (0 << 11) /* QUART_DQS_DLY */ \
140 | (1 << 8) /* WDLY */ \
141 | (0 << 7) /* EARLY_ODT */ \
142 | (0 << 6) /* ON_DIE_TERMINATE */ \
143 | (0 << 5) /* FIFO_OV_CLEAR */ \
144 | (0 << 4) /* FIFO_UV_CLEAR */ \
145 | (0 << 1) /* FIFO_OV_EN */ \
146 | (0 << 0) /* FIFO_UV_EN */ \
147 )
148
149#define CONFIG_SYS_MDDRC_TIME_CFG0 0x04E03124
150#define CONFIG_SYS_MDDRC_TIME_CFG1 0x30CA1147
151#define CONFIG_SYS_MDDRC_TIME_CFG2 0x32B10864
152
153/* register address only, i.e. template without values */
154#define CONFIG_SYS_MICRON_BMODE 0x01000000
155#define CONFIG_SYS_MICRON_EMODE 0x01010000
156#define CONFIG_SYS_MICRON_EMODE2 0x01020000
157#define CONFIG_SYS_MICRON_EMODE3 0x01030000
158/*
159 * values for mode registers (without mode register address)
160 */
161/* CAS 2.5 (6), burst seq (0) and length 4 (2) */
162#define CONFIG_SYS_MICRON_BMODE_PARAM 0x00000062
163#define CONFIG_SYS_MICRON_BMODE_RSTDLL 0x00000100
164/* DLL enable, reduced drive strength */
165#define CONFIG_SYS_MICRON_EMODE_PARAM 0x00000002
166
167#define CONFIG_SYS_DDRCMD_NOP 0x01380000
168#define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400
169#define CONFIG_SYS_MICRON_EMR ((1 << 24) | /* CMD_REQ */ \
170 (0 << 22) | /* DRAM_CS */ \
171 (0 << 21) | /* DRAM_RAS */ \
172 (0 << 20) | /* DRAM_CAS */ \
173 (0 << 19) | /* DRAM_WEB */ \
174 (1 << 16) | /* DRAM_BS[2:0] */ \
175 (0 << 15) | /* */ \
176 (0 << 12) | /* A12->out */ \
177 (0 << 11) | /* A11->RDQS */ \
178 (0 << 10) | /* A10->DQS# */ \
179 (0 << 7) | /* OCD program */ \
180 (0 << 6) | /* Rtt1 */ \
181 (0 << 3) | /* posted CAS# */ \
182 (0 << 2) | /* Rtt0 */ \
183 (1 << 1) | /* ODS */ \
184 (0 << 0) /* DLL */ \
185 )
186#define CONFIG_SYS_MICRON_EMR2 0x01020000
187#define CONFIG_SYS_MICRON_EMR3 0x01030000
188#define CONFIG_SYS_DDRCMD_RFSH 0x01080000
189#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432
190#define CONFIG_SYS_MICRON_EMR_OCD ((1 << 24) | /* CMD_REQ */ \
191 (0 << 22) | /* DRAM_CS */ \
192 (0 << 21) | /* DRAM_RAS */ \
193 (0 << 20) | /* DRAM_CAS */ \
194 (0 << 19) | /* DRAM_WEB */ \
195 (1 << 16) | /* DRAM_BS[2:0] */ \
196 (0 << 15) | /* */ \
197 (0 << 12) | /* A12->out */ \
198 (0 << 11) | /* A11->RDQS */ \
199 (1 << 10) | /* A10->DQS# */ \
200 (7 << 7) | /* OCD program */ \
201 (0 << 6) | /* Rtt1 */ \
202 (0 << 3) | /* posted CAS# */ \
203 (1 << 2) | /* Rtt0 */ \
204 (0 << 1) | /* ODS */ \
205 (0 << 0) /* DLL */ \
206 )
207
208/*
209 * Backward compatible definitions,
210 * so we do not have to change arch/powerpc/cpu/mpc512x/fixed_sdram.c
211 */
212#define CONFIG_SYS_DDRCMD_EM2 (CONFIG_SYS_MICRON_EMR2)
213#define CONFIG_SYS_DDRCMD_EM3 (CONFIG_SYS_MICRON_EMR3)
214#define CONFIG_SYS_DDRCMD_EN_DLL (CONFIG_SYS_MICRON_EMR)
215#define CONFIG_SYS_DDRCMD_OCD_DEFAULT (CONFIG_SYS_MICRON_EMR_OCD)
216
217/* DDR Priority Manager Configuration */
218#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777
219#define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000
220#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001
221#define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC
222#define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA
223#define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666
224#define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555
225#define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444
226#define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444
227#define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555
228#define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558
229#define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111
230#define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122
231#define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa
232#define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa
233#define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666
234#define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666
235#define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111
236#define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111
237#define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111
238#define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111
239#define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111
240#define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111
241
242/*
243 * NOR FLASH on the Local Bus
244 */
245#define CONFIG_SYS_FLASH_CFI /* use the CFI code */
246#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
247#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* start of FLASH */
248#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* max flash size */
249
250#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
251#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
252#define CONFIG_SYS_FLASH_BANKS_LIST { \
253 CONFIG_SYS_FLASH_BASE + 0 * CONFIG_SYS_FLASH_SIZE, \
254 }
255#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */
256
257#undef CONFIG_SYS_FLASH_CHECKSUM
258#define CONFIG_SYS_FLASH_PROTECTION
259
260/*
261 * SRAM support
262 */
263#define CONFIG_SYS_SRAM_BASE 0x30000000
264#define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */
265
266/*
267 * CS related parameters
268 * TODO document these
269 */
270/* CS0 Flash */
271#define CONFIG_SYS_CS0_CFG 0x00031110
272#define CONFIG_SYS_CS0_START 0xFC000000
273#define CONFIG_SYS_CS0_SIZE 0x04000000
274/* CS1 FRAM */
275#define CONFIG_SYS_CS1_CFG 0x00011000
276#define CONFIG_SYS_CS1_START 0xE0000000
277#define CONFIG_SYS_CS1_SIZE 0x00010000
278/* CS2 AS-i 1 */
279#define CONFIG_SYS_CS2_CFG 0x00009100
280#define CONFIG_SYS_CS2_START 0xE0100000
281#define CONFIG_SYS_CS2_SIZE 0x00080000
282/* CS3 netX */
283#define CONFIG_SYS_CS3_CFG 0x000A1140
284#define CONFIG_SYS_CS3_START 0xE0300000
285#define CONFIG_SYS_CS3_SIZE 0x00020000
286/* CS5 safety */
287#define CONFIG_SYS_CS5_CFG 0x0011F000
288#define CONFIG_SYS_CS5_START 0xE0400000
289#define CONFIG_SYS_CS5_SIZE 0x00010000
290/* CS6 AS-i 2 */
291#define CONFIG_SYS_CS6_CFG 0x00009100
292#define CONFIG_SYS_CS6_START 0xE0200000
293#define CONFIG_SYS_CS6_SIZE 0x00080000
294
295/* Don't use alternative CS timing for any CS */
296#define CONFIG_SYS_CS_ALETIMING 0x00000000
297#define CONFIG_SYS_CS_BURST 0x00000000
298#define CONFIG_SYS_CS_DEADCYCLE 0x00000020
299#define CONFIG_SYS_CS_HOLDCYCLE 0x00000020
300
301/* Use SRAM for initial stack */
302#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE
303#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_SRAM_SIZE
304
305#define CONFIG_SYS_GBL_DATA_SIZE 0x100
306#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
307 CONFIG_SYS_GBL_DATA_SIZE)
308#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
309
310#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
311#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
312
313#ifdef CONFIG_FSL_DIU_FB
314#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024)
315#else
316#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
317#endif
318
319/*
320 * Serial Port
321 */
322#define CONFIG_CONS_INDEX 1
323
324/*
325 * Serial console configuration
326 */
327#define CONFIG_PSC_CONSOLE 3 /* console on PSC3 */
328#define CONFIG_SYS_PSC3
329#if CONFIG_PSC_CONSOLE != 3
330#error CONFIG_PSC_CONSOLE must be 3
331#endif
332
333#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
334#define CONFIG_SYS_BAUDRATE_TABLE \
335 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
336
337#define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE
338#define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR
339#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE
340#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR
341
342/*
343 * Clocks in use
344 */
345#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
346 CLOCK_SCCR1_LPC_EN | \
347 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
348 CLOCK_SCCR1_PSC_EN(7) | \
349 CLOCK_SCCR1_PSCFIFO_EN | \
350 CLOCK_SCCR1_DDR_EN | \
351 CLOCK_SCCR1_FEC_EN | \
352 CLOCK_SCCR1_TPR_EN)
353
354#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
355 CLOCK_SCCR2_SPDIF_EN | \
356 CLOCK_SCCR2_DIU_EN | \
357 CLOCK_SCCR2_I2C_EN)
358
359
360#define CONFIG_CMDLINE_EDITING 1 /* command line history */
361
362/* I2C */
363#define CONFIG_HARD_I2C /* I2C with hardware support */
364#define CONFIG_I2C_MULTI_BUS
365
366/* I2C speed and slave address */
367#define CONFIG_SYS_I2C_SPEED 100000
368#define CONFIG_SYS_I2C_SLAVE 0x7F
369
370/*
Benoît Thébaudeau83306922013-04-23 10:17:42 +0000371 * IIM - IC Identification Module
372 */
373#undef CONFIG_FSL_IIM
374
375/*
Anatolij Gustschinfcc7fe42013-02-08 00:03:48 +0000376 * EEPROM configuration for Atmel AT24C01:
377 * 8-bit addresses, 30ms write delay, 32-Byte Page Write Mode
378 */
379#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
380#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
381#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 30
382#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
383
384/*
385 * Ethernet configuration
386 */
387#define CONFIG_MPC512x_FEC 1
388#define CONFIG_NET_MULTI
389#define CONFIG_PHY_ADDR 0x1F
390#define CONFIG_MII 1 /* MII PHY management */
391#define CONFIG_FEC_AN_TIMEOUT 1
392#define CONFIG_HAS_ETH0
393
394/*
395 * Environment
396 */
397#define CONFIG_ENV_IS_IN_FLASH 1
398/* This has to be a multiple of the flash sector size */
399#define CONFIG_ENV_ADDR 0xFFF40000
400#define CONFIG_ENV_SIZE 0x2000
401#define CONFIG_ENV_SECT_SIZE 0x20000
402
403/* Address and size of Redundant Environment Sector */
404#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \
405 CONFIG_ENV_SECT_SIZE)
406#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
407
408#define CONFIG_LOADS_ECHO 1
409#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
410
411#include <config_cmd_default.h>
412
413#define CONFIG_CMD_ASKENV
414#define CONFIG_CMD_DHCP
415#define CONFIG_CMD_EEPROM
416#undef CONFIG_CMD_FUSE
417#define CONFIG_CMD_I2C
418#undef CONFIG_CMD_IDE
419#undef CONFIG_CMD_EXT2
420#define CONFIG_CMD_JFFS2
421#define CONFIG_CMD_MII
422#define CONFIG_CMD_NFS
423#define CONFIG_CMD_PING
424#define CONFIG_CMD_REGINFO
425
426#if defined(CONFIG_PCI)
427#define CONFIG_CMD_PCI
428#endif
429
430#if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_EXT2)
431#define CONFIG_DOS_PARTITION
432#define CONFIG_MAC_PARTITION
433#define CONFIG_ISO_PARTITION
434#endif /* defined(CONFIG_CMD_IDE) */
435
436/*
437 * Miscellaneous configurable options
438 */
439#define CONFIG_SYS_LONGHELP /* undef to save memory */
440#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
441#define CONFIG_SYS_PROMPT "ac14xx> " /* Monitor Command Prompt */
442
443#ifdef CONFIG_CMD_KGDB
444# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
445#else
446# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
447#endif
448
449/* Print Buffer Size */
450#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
451 sizeof(CONFIG_SYS_PROMPT) + 16)
452/* max number of command args */
453#define CONFIG_SYS_MAXARGS 32
454/* Boot Argument Buffer Size */
455#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
456
457/* decrementer freq: 1ms ticks */
458#define CONFIG_SYS_HZ 1000
459
460/*
461 * For booting Linux, the board info and command line data
462 * have to be in the first 8 MB of memory, since this is
463 * the maximum mapped by the Linux kernel during initialization.
464 */
465#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
466
467/* Cache Configuration */
468#define CONFIG_SYS_DCACHE_SIZE 32768
469#define CONFIG_SYS_CACHELINE_SIZE 32
470#ifdef CONFIG_CMD_KGDB
471#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of 32 */
472#endif
473
474#define CONFIG_SYS_HID0_INIT 0x000000000
475#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
476 HID0_ICE)
477#define CONFIG_SYS_HID2 HID2_HBE
478
479#define CONFIG_HIGH_BATS 1 /* High BATs supported */
480
481/*
482 * Internal Definitions
483 *
484 * Boot Flags
485 */
486#define BOOTFLAG_COLD 0x01
487#define BOOTFLAG_WARM 0x02
488
489#ifdef CONFIG_CMD_KGDB
490#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
491#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
492#endif
493
494/*
495 * Environment Configuration
496 */
497#define CONFIG_ENV_OVERWRITE
498#define CONFIG_TIMESTAMP
499
500#define CONFIG_HOSTNAME ac14xx
501#define CONFIG_BOOTFILE "ac14xx/uImage"
502#define CONFIG_ROOTPATH "/opt/eldk/ppc_6xx"
503
504/* default load addr for tftp and bootm */
505#define CONFIG_LOADADDR 400000
506
507#define CONFIG_BOOTDELAY 2 /* -1 disables auto-boot */
508
509/* XXX TODO need to specify the builtin environment */
510#define CONFIG_PREBOOT "echo;" \
511 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
512 "echo"
513
514#define CONFIG_EXTRA_ENV_SETTINGS_DEVEL \
515 "muster_nr=00\0" \
516 "fromram=run ramargs addip addtty; " \
517 "tftp ${fdt_addr_r} k6m2/ac14xx.dtb-${muster_nr}; " \
518 "tftp ${kernel_addr_r} k6m2/uImage-${muster_nr}; " \
519 "tftp ${ramdisk_addr_r} k6m2/uFS-${muster_nr}; " \
520 "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0" \
521 "fromnfs=run nfsargs addip addtty; " \
522 "tftp ${fdt_addr_r} k6m2/ac14xx.dtb-${muster_nr}; " \
523 "tftp ${kernel_addr_r} k6m2/uImage-${muster_nr}; " \
524 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
525 "fromflash=run nfsargs addip addtty; " \
526 "bootm fc020000 - fc000000\0" \
527 "mtdargsrec=setenv bootargs root=/dev/mtdblock1 ro\0" \
528 "recovery=run mtdargsrec addip addtty; " \
529 "bootm ffd20000 - ffee0000\0" \
530 "production=run ramargs addip addtty; " \
531 "bootm fc020000 fc400000 fc000000\0" \
532 "mtdargs=setenv bootargs root=/dev/mtdblock1 ro\0" \
533 "prodmtd=run mtdargs addip addtty; " \
534 "bootm fc020000 - fc000000\0" \
535 ""
536
537#define CONFIG_EXTRA_ENV_SETTINGS \
538 "u-boot_addr_r=200000\0" \
539 "kernel_addr_r=600000\0" \
540 "fdt_addr_r=a00000\0" \
541 "ramdisk_addr_r=b00000\0" \
542 "u-boot_addr=FFF00000\0" \
543 "kernel_addr=FC020000\0" \
544 "fdt_addr=FC000000\0" \
545 "ramdisk_addr=FC400000\0" \
546 "verify=n\0" \
547 "ramdiskfile=ac14xx/uRamdisk\0" \
548 "u-boot=ac14xx/u-boot.bin\0" \
549 "bootfile=ac14xx/uImage\0" \
550 "fdtfile=ac14xx/ac14xx.dtb\0" \
551 "rootpath=/opt/eldk/ppc_6xx\n" \
552 "netdev=eth0\0" \
553 "consdev=ttyPSC0\0" \
554 "hostname=ac14xx\0" \
555 "nfsargs=setenv bootargs root=/dev/nfs rw " \
556 "nfsroot=${serverip}:${rootpath}-${muster_nr}\0" \
557 "ramargs=setenv bootargs root=/dev/ram rw\0" \
558 "addip=setenv bootargs ${bootargs} " \
559 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
560 ":${hostname}:${netdev}:off panic=1\0" \
561 "addtty=setenv bootargs ${bootargs} " \
562 "console=${consdev},${baudrate}\0" \
563 "flash_nfs=run nfsargs addip addtty;" \
564 "bootm ${kernel_addr} - ${fdt_addr}\0" \
565 "flash_self=run ramargs addip addtty;" \
566 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
567 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
568 "tftp ${fdt_addr_r} ${fdtfile};" \
569 "run nfsargs addip addtty;" \
570 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
571 "net_self=tftp ${kernel_addr_r} ${bootfile};" \
572 "tftp ${ramdisk_addr_r} ${ramdiskfile};" \
573 "tftp ${fdt_addr_r} ${fdtfile};" \
574 "run ramargs addip addtty;" \
575 "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
576 "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
577 "update=protect off ${u-boot_addr} +${filesize};" \
578 "era ${u-boot_addr} +${filesize};" \
579 "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \
580 CONFIG_EXTRA_ENV_SETTINGS_DEVEL \
581 "upd=run load update\0" \
582 ""
583
584#define CONFIG_BOOTCOMMAND "run production"
585
586#define CONFIG_FIT 1
587#define CONFIG_OF_LIBFDT 1
588#define CONFIG_OF_BOARD_SETUP 1
589#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1
590
591#define OF_CPU "PowerPC,5121@0"
592#define OF_SOC_COMPAT "fsl,mpc5121-immr"
593#define OF_TBCLK (bd->bi_busfreq / 4)
594#define OF_STDOUT_PATH "/soc@80000000/serial@11300"
595
596#endif /* __CONFIG_H */