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Prafulla Wadaskarfbc83652009-07-16 21:02:24 +05301/*
2 * (C) Copyright 2009
3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 */
24
25#include <common.h>
26#include <miiphy.h>
27#include <netdev.h>
Lei Wena7efd712011-10-18 20:11:42 +053028#include <asm/arch/cpu.h>
Prafulla Wadaskarfbc83652009-07-16 21:02:24 +053029#include <asm/arch/kirkwood.h>
30#include <asm/arch/mpp.h>
31#include "rd6281a.h"
32
33DECLARE_GLOBAL_DATA_PTR;
34
Prafulla Wadaskar754ae3f2010-10-20 20:12:27 +053035int board_early_init_f(void)
Prafulla Wadaskarfbc83652009-07-16 21:02:24 +053036{
37 /*
38 * default gpio configuration
39 * There are maximum 64 gpios controlled through 2 sets of registers
40 * the below configuration configures mainly initial LED status
41 */
42 kw_config_gpio(RD6281A_OE_VAL_LOW,
43 RD6281A_OE_VAL_HIGH,
44 RD6281A_OE_LOW, RD6281A_OE_HIGH);
45
46 /* Multi-Purpose Pins Functionality configuration */
Albert ARIBAUD9d86f0c2012-11-26 11:27:36 +000047 static const u32 kwmpp_config[] = {
Prafulla Wadaskarfbc83652009-07-16 21:02:24 +053048 MPP0_NF_IO2,
49 MPP1_NF_IO3,
50 MPP2_NF_IO4,
51 MPP3_NF_IO5,
52 MPP4_NF_IO6,
53 MPP5_NF_IO7,
54 MPP6_SYSRST_OUTn,
55 MPP7_GPO,
56 MPP8_TW_SDA,
57 MPP9_TW_SCK,
58 MPP10_UART0_TXD,
59 MPP11_UART0_RXD,
60 MPP12_SD_CLK,
61 MPP13_SD_CMD,
62 MPP14_SD_D0,
63 MPP15_SD_D1,
64 MPP16_SD_D2,
65 MPP17_SD_D3,
66 MPP18_NF_IO0,
67 MPP19_NF_IO1,
68 MPP20_GE1_0,
69 MPP21_GE1_1,
70 MPP22_GE1_2,
71 MPP23_GE1_3,
72 MPP24_GE1_4,
73 MPP25_GE1_5,
74 MPP26_GE1_6,
75 MPP27_GE1_7,
76 MPP28_GPIO,
77 MPP29_GPIO,
78 MPP30_GE1_10,
79 MPP31_GE1_11,
80 MPP32_GE1_12,
81 MPP33_GE1_13,
82 MPP34_GE1_14,
83 MPP35_GPIO,
84 MPP36_AUDIO_SPDIFI,
85 MPP37_AUDIO_SPDIFO,
86 MPP38_GPIO,
87 MPP39_TDM_SPI_CS0,
88 MPP40_TDM_SPI_SCK,
89 MPP41_TDM_SPI_MISO,
90 MPP42_TDM_SPI_MOSI,
91 MPP43_TDM_CODEC_INTn,
92 MPP44_GPIO,
93 MPP45_TDM_PCLK,
94 MPP46_TDM_FS,
95 MPP47_TDM_DRX,
96 MPP48_TDM_DTX,
97 MPP49_GPIO,
98 0
99 };
Valentin Longchamp84683632012-06-01 01:31:00 +0000100 kirkwood_mpp_conf(kwmpp_config, NULL);
Prafulla Wadaskar754ae3f2010-10-20 20:12:27 +0530101 return 0;
102}
Prafulla Wadaskarfbc83652009-07-16 21:02:24 +0530103
Prafulla Wadaskar754ae3f2010-10-20 20:12:27 +0530104int board_init(void)
105{
Prafulla Wadaskarfbc83652009-07-16 21:02:24 +0530106 /*
107 * arch number of board
108 */
109 gd->bd->bi_arch_number = MACH_TYPE_RD88F6281;
110
111 /* adress of boot parameters */
112 gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
113
114 return 0;
115}
116
Prafulla Wadaskarfbc83652009-07-16 21:02:24 +0530117void mv_phy_88e1116_init(char *name)
118{
119 u16 reg;
120 u16 devadr;
121
122 if (miiphy_set_current_dev(name))
123 return;
124
125 /* command to read PHY dev address */
126 if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
127 printf("Err..%s could not read PHY dev address\n",
128 __FUNCTION__);
129 return;
130 }
131
132 /*
133 * Enable RGMII delay on Tx and Rx for CPU port
134 * Ref: sec 4.7.2 of chip datasheet
135 */
136 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
137 miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
138 reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
139 miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
140 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
141
142 /* reset the phy */
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500143 if (miiphy_read (name, devadr, MII_BMCR, &reg) != 0) {
Prafulla Wadaskarfbc83652009-07-16 21:02:24 +0530144 printf("Err..(%s) PHY status read failed\n", __FUNCTION__);
145 return;
146 }
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500147 if (miiphy_write (name, devadr, MII_BMCR, reg | 0x8000) != 0) {
Prafulla Wadaskarfbc83652009-07-16 21:02:24 +0530148 printf("Err..(%s) PHY reset failed\n", __FUNCTION__);
149 return;
150 }
151
152 printf("88E1116 Initialized on %s\n", name);
153}
154
155/* Configure and enable Switch and PHY */
156void reset_phy(void)
157{
158 /* configure and initialize switch */
159 struct mv88e61xx_config swcfg = {
160 .name = "egiga0",
161 .vlancfg = MV88E61XX_VLANCFG_ROUTER,
162 .rgmii_delay = MV88E61XX_RGMII_DELAY_EN,
163 .led_init = MV88E61XX_LED_INIT_EN,
164 .portstate = MV88E61XX_PORTSTT_FORWARDING,
165 .cpuport = (1 << 5),
166 .ports_enabled = 0x3f,
167 };
168
169 mv88e61xx_switch_initialize(&swcfg);
170
171 /* configure and initialize PHY */
172 mv_phy_88e1116_init("egiga1");
173}