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Stefan Roese16c0cc12007-03-21 13:39:57 +01001/*
2 * (C) Copyright 2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
Stefan Roese3cb86f32007-03-24 15:45:34 +010024/* define DEBUG for debugging output (obviously ;-)) */
25#if 0
26#define DEBUG
Stefan Roese16c0cc12007-03-21 13:39:57 +010027#endif
28
Stefan Roese3cb86f32007-03-24 15:45:34 +010029#include <common.h>
30#include <asm/processor.h>
31#include <asm/io.h>
Stefan Roese09887762010-09-16 14:30:37 +020032#include <asm/ppc4xx-gpio.h>
Stefan Roese3cb86f32007-03-24 15:45:34 +010033
Stefan Roesedf8a24c2007-06-19 16:42:31 +020034extern void board_pll_init_f(void);
35
Stefan Roesec440bfe2007-06-06 11:42:13 +020036#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
Stefan Roese16c0cc12007-03-21 13:39:57 +010037static void cram_bcr_write(u32 wr_val)
38{
Stefan Roese3cb86f32007-03-24 15:45:34 +010039 wr_val <<= 2;
Stefan Roese16c0cc12007-03-21 13:39:57 +010040
Stefan Roese3cb86f32007-03-24 15:45:34 +010041 /* set CRAM_CRE to 1 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020042 gpio_write_bit(CONFIG_SYS_GPIO_CRAM_CRE, 1);
Stefan Roese16c0cc12007-03-21 13:39:57 +010043
Stefan Roese3cb86f32007-03-24 15:45:34 +010044 /* Write BCR to CRAM on CS1 */
45 out32(wr_val + 0x00200000, 0);
46 debug("CRAM VAL: %08x for CS1 ", wr_val + 0x00200000);
Stefan Roese16c0cc12007-03-21 13:39:57 +010047
Stefan Roese3cb86f32007-03-24 15:45:34 +010048 /* Write BCR to CRAM on CS2 */
49 out32(wr_val + 0x02200000, 0);
50 debug("CRAM VAL: %08x for CS2\n", wr_val + 0x02200000);
Stefan Roese16c0cc12007-03-21 13:39:57 +010051
Stefan Roese3cb86f32007-03-24 15:45:34 +010052 sync();
53 eieio();
Stefan Roese16c0cc12007-03-21 13:39:57 +010054
Stefan Roese3cb86f32007-03-24 15:45:34 +010055 /* set CRAM_CRE back to 0 (normal operation) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020056 gpio_write_bit(CONFIG_SYS_GPIO_CRAM_CRE, 0);
Stefan Roese16c0cc12007-03-21 13:39:57 +010057
Stefan Roese16c0cc12007-03-21 13:39:57 +010058 return;
59}
Stefan Roesec440bfe2007-06-06 11:42:13 +020060#endif
Stefan Roese16c0cc12007-03-21 13:39:57 +010061
Becky Bruce9973e3c2008-06-09 16:03:40 -050062phys_size_t initdram(int board_type)
Stefan Roese16c0cc12007-03-21 13:39:57 +010063{
Stefan Roesedf8a24c2007-06-19 16:42:31 +020064#if defined(CONFIG_NAND_SPL)
65 u32 reg;
66
67 /* don't reinit PLL when booting via I2C bootstrap option */
Stefan Roesed1c3b272009-09-09 16:25:29 +020068 mfsdr(SDR0_PINSTP, reg);
Stefan Roesedf8a24c2007-06-19 16:42:31 +020069 if (reg != 0xf0000000)
70 board_pll_init_f();
71#endif
72
Stefan Roesec440bfe2007-06-06 11:42:13 +020073#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
74 int i;
Stefan Roese3cb86f32007-03-24 15:45:34 +010075 u32 val;
Stefan Roese16c0cc12007-03-21 13:39:57 +010076
Stefan Roese3cb86f32007-03-24 15:45:34 +010077 /* 1. EBC need to program READY, CLK, ADV for ASync mode */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078 gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
79 gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
80 gpio_config(CONFIG_SYS_GPIO_CRAM_CRE, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
81 gpio_config(CONFIG_SYS_GPIO_CRAM_WAIT, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG);
Stefan Roese16c0cc12007-03-21 13:39:57 +010082
Stefan Roese3cb86f32007-03-24 15:45:34 +010083 /* 2. EBC in Async mode */
Stefan Roesed1c3b272009-09-09 16:25:29 +020084 mtebc(PB1AP, 0x078F1EC0);
85 mtebc(PB2AP, 0x078F1EC0);
86 mtebc(PB1CR, 0x000BC000);
87 mtebc(PB2CR, 0x020BC000);
Stefan Roese3cb86f32007-03-24 15:45:34 +010088
89 /* 3. Set CRAM in Sync mode */
90 cram_bcr_write(0x7012); /* CRAM burst setting */
91
92 /* 4. EBC in Sync mode */
Stefan Roesed1c3b272009-09-09 16:25:29 +020093 mtebc(PB1AP, 0x9C0201C0);
94 mtebc(PB2AP, 0x9C0201C0);
Stefan Roese3cb86f32007-03-24 15:45:34 +010095
96 /* Set GPIO pins back to alternate function */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097 gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
98 gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
Stefan Roese3cb86f32007-03-24 15:45:34 +010099
100 /* Config EBC to use RDY */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200101 mfsdr(SDR0_ULTRA0, val);
102 mtsdr(SDR0_ULTRA0, val | SDR_ULTRA0_EBCRDYEN);
Stefan Roesec440bfe2007-06-06 11:42:13 +0200103
104 /* Wait a short while, since for NAND booting this is too fast */
105 for (i=0; i<200000; i++)
106 ;
107#endif
Stefan Roese3cb86f32007-03-24 15:45:34 +0100108
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109 return (CONFIG_SYS_MBYTES_RAM << 20);
Stefan Roese16c0cc12007-03-21 13:39:57 +0100110}