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wdenkaffae2b2002-08-17 09:36:01 +00001/*
2 * (C) Copyright 2002 SIXNET, dge@sixnetio.com.
3 *
wdenkec4c5442004-02-09 23:12:24 +00004 * (C) Copyright 2004, Li-Pro.Net <www.li-pro.net>
5 * Stephan Linz <linz@li-pro.net>
6 *
wdenkaffae2b2002-08-17 09:36:01 +00007 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26/*
wdenkec4c5442004-02-09 23:12:24 +000027 * Date & Time support for DS1306 RTC using SPI:
28 *
29 * - SXNI855T: it uses its own soft SPI here in this file
30 * - all other: use the external spi_xfer() function
31 * (see include/spi.h)
wdenkaffae2b2002-08-17 09:36:01 +000032 */
33
34#include <common.h>
35#include <command.h>
36#include <rtc.h>
wdenkec4c5442004-02-09 23:12:24 +000037#include <spi.h>
wdenkaffae2b2002-08-17 09:36:01 +000038
Michal Simek871c18d2008-07-14 19:45:37 +020039#if defined(CONFIG_CMD_DATE)
wdenkaffae2b2002-08-17 09:36:01 +000040
wdenkec4c5442004-02-09 23:12:24 +000041#define RTC_SECONDS 0x00
42#define RTC_MINUTES 0x01
43#define RTC_HOURS 0x02
44#define RTC_DAY_OF_WEEK 0x03
45#define RTC_DATE_OF_MONTH 0x04
46#define RTC_MONTH 0x05
47#define RTC_YEAR 0x06
48
49#define RTC_SECONDS_ALARM0 0x07
50#define RTC_MINUTES_ALARM0 0x08
51#define RTC_HOURS_ALARM0 0x09
52#define RTC_DAY_OF_WEEK_ALARM0 0x0a
53
54#define RTC_SECONDS_ALARM1 0x0b
55#define RTC_MINUTES_ALARM1 0x0c
56#define RTC_HOURS_ALARM1 0x0d
57#define RTC_DAY_OF_WEEK_ALARM1 0x0e
58
59#define RTC_CONTROL 0x0f
60#define RTC_STATUS 0x10
61#define RTC_TRICKLE_CHARGER 0x11
62
63#define RTC_USER_RAM_BASE 0x20
64
wdenkec4c5442004-02-09 23:12:24 +000065/* ************************************************************************* */
66#ifdef CONFIG_SXNI855T /* !!! SHOULD BE CHANGED TO NEW CODE !!! */
67
68static void soft_spi_send (unsigned char n);
69static unsigned char soft_spi_read (void);
70static void init_spi (void);
wdenkaffae2b2002-08-17 09:36:01 +000071
72/*-----------------------------------------------------------------------
73 * Definitions
74 */
75
76#define PB_SPISCK 0x00000002 /* PB 30 */
77#define PB_SPIMOSI 0x00000004 /* PB 29 */
78#define PB_SPIMISO 0x00000008 /* PB 28 */
79#define PB_SPI_CE 0x00010000 /* PB 15 */
80
81/* ------------------------------------------------------------------------- */
82
83/* read clock time from DS1306 and return it in *tmp */
Yuri Tikhonovb73a19e2008-03-20 17:56:04 +030084int rtc_get (struct rtc_time *tmp)
wdenkaffae2b2002-08-17 09:36:01 +000085{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
wdenkec4c5442004-02-09 23:12:24 +000087 unsigned char spi_byte; /* Data Byte */
wdenkaffae2b2002-08-17 09:36:01 +000088
wdenkec4c5442004-02-09 23:12:24 +000089 init_spi (); /* set port B for software SPI */
wdenkaffae2b2002-08-17 09:36:01 +000090
wdenkec4c5442004-02-09 23:12:24 +000091 /* Now we can enable the DS1306 RTC */
92 immap->im_cpm.cp_pbdat |= PB_SPI_CE;
93 udelay (10);
wdenkaffae2b2002-08-17 09:36:01 +000094
wdenkec4c5442004-02-09 23:12:24 +000095 /* Shift out the address (0) of the time in the Clock Chip */
96 soft_spi_send (0);
wdenkaffae2b2002-08-17 09:36:01 +000097
wdenkec4c5442004-02-09 23:12:24 +000098 /* Put the clock readings into the rtc_time structure */
99 tmp->tm_sec = bcd2bin (soft_spi_read ()); /* Read seconds */
100 tmp->tm_min = bcd2bin (soft_spi_read ()); /* Read minutes */
wdenkaffae2b2002-08-17 09:36:01 +0000101
wdenkec4c5442004-02-09 23:12:24 +0000102 /* Hours are trickier */
103 spi_byte = soft_spi_read (); /* Read Hours into temporary value */
104 if (spi_byte & 0x40) {
105 /* 12 hour mode bit is set (time is in 1-12 format) */
106 if (spi_byte & 0x20) {
107 /* since PM we add 11 to get 0-23 for hours */
108 tmp->tm_hour = (bcd2bin (spi_byte & 0x1F)) + 11;
109 } else {
110 /* since AM we subtract 1 to get 0-23 for hours */
111 tmp->tm_hour = (bcd2bin (spi_byte & 0x1F)) - 1;
112 }
113 } else {
114 /* Otherwise, 0-23 hour format */
115 tmp->tm_hour = (bcd2bin (spi_byte & 0x3F));
wdenkaffae2b2002-08-17 09:36:01 +0000116 }
wdenkaffae2b2002-08-17 09:36:01 +0000117
wdenkec4c5442004-02-09 23:12:24 +0000118 soft_spi_read (); /* Read and discard Day of week */
119 tmp->tm_mday = bcd2bin (soft_spi_read ()); /* Read Day of the Month */
120 tmp->tm_mon = bcd2bin (soft_spi_read ()); /* Read Month */
wdenkaffae2b2002-08-17 09:36:01 +0000121
wdenkec4c5442004-02-09 23:12:24 +0000122 /* Read Year and convert to this century */
123 tmp->tm_year = bcd2bin (soft_spi_read ()) + 2000;
wdenkaffae2b2002-08-17 09:36:01 +0000124
wdenkec4c5442004-02-09 23:12:24 +0000125 /* Now we can disable the DS1306 RTC */
126 immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; /* Disable DS1306 Chip */
127 udelay (10);
wdenkaffae2b2002-08-17 09:36:01 +0000128
wdenkec4c5442004-02-09 23:12:24 +0000129 GregorianDay (tmp); /* Determine the day of week */
wdenkaffae2b2002-08-17 09:36:01 +0000130
wdenkec4c5442004-02-09 23:12:24 +0000131 debug ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
132 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
133 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
Yuri Tikhonovb73a19e2008-03-20 17:56:04 +0300134
135 return 0;
wdenkaffae2b2002-08-17 09:36:01 +0000136}
137
138/* ------------------------------------------------------------------------- */
139
140/* set clock time in DS1306 RTC and in MPC8xx RTC */
Jean-Christophe PLAGNIOL-VILLARDd1e23192008-09-01 23:06:23 +0200141int rtc_set (struct rtc_time *tmp)
wdenkaffae2b2002-08-17 09:36:01 +0000142{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
wdenkaffae2b2002-08-17 09:36:01 +0000144
wdenkec4c5442004-02-09 23:12:24 +0000145 init_spi (); /* set port B for software SPI */
wdenkaffae2b2002-08-17 09:36:01 +0000146
wdenkec4c5442004-02-09 23:12:24 +0000147 /* Now we can enable the DS1306 RTC */
148 immap->im_cpm.cp_pbdat |= PB_SPI_CE; /* Enable DS1306 Chip */
149 udelay (10);
wdenkaffae2b2002-08-17 09:36:01 +0000150
wdenkec4c5442004-02-09 23:12:24 +0000151 /* First disable write protect in the clock chip control register */
152 soft_spi_send (0x8F); /* send address of the control register */
153 soft_spi_send (0x00); /* send control register contents */
wdenkaffae2b2002-08-17 09:36:01 +0000154
wdenkec4c5442004-02-09 23:12:24 +0000155 /* Now disable the DS1306 to terminate the write */
156 immap->im_cpm.cp_pbdat &= ~PB_SPI_CE;
157 udelay (10);
wdenkaffae2b2002-08-17 09:36:01 +0000158
wdenkec4c5442004-02-09 23:12:24 +0000159 /* Now enable the DS1306 to initiate a new write */
160 immap->im_cpm.cp_pbdat |= PB_SPI_CE;
161 udelay (10);
wdenkaffae2b2002-08-17 09:36:01 +0000162
wdenkec4c5442004-02-09 23:12:24 +0000163 /* Next, send the address of the clock time write registers */
164 soft_spi_send (0x80); /* send address of the first time register */
wdenkaffae2b2002-08-17 09:36:01 +0000165
wdenkec4c5442004-02-09 23:12:24 +0000166 /* Use Burst Mode to send all of the time data to the clock */
167 bin2bcd (tmp->tm_sec);
168 soft_spi_send (bin2bcd (tmp->tm_sec)); /* Send Seconds */
169 soft_spi_send (bin2bcd (tmp->tm_min)); /* Send Minutes */
170 soft_spi_send (bin2bcd (tmp->tm_hour)); /* Send Hour */
171 soft_spi_send (bin2bcd (tmp->tm_wday)); /* Send Day of the Week */
172 soft_spi_send (bin2bcd (tmp->tm_mday)); /* Send Day of Month */
173 soft_spi_send (bin2bcd (tmp->tm_mon)); /* Send Month */
174 soft_spi_send (bin2bcd (tmp->tm_year - 2000)); /* Send Year */
wdenkaffae2b2002-08-17 09:36:01 +0000175
wdenkec4c5442004-02-09 23:12:24 +0000176 /* Now we can disable the Clock chip to terminate the burst write */
177 immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; /* Disable DS1306 Chip */
178 udelay (10);
wdenkaffae2b2002-08-17 09:36:01 +0000179
wdenkec4c5442004-02-09 23:12:24 +0000180 /* Now we can enable the Clock chip to initiate a new write */
181 immap->im_cpm.cp_pbdat |= PB_SPI_CE; /* Enable DS1306 Chip */
182 udelay (10);
wdenkaffae2b2002-08-17 09:36:01 +0000183
wdenkec4c5442004-02-09 23:12:24 +0000184 /* First we Enable write protect in the clock chip control register */
185 soft_spi_send (0x8F); /* send address of the control register */
186 soft_spi_send (0x40); /* send out Control Register contents */
wdenkaffae2b2002-08-17 09:36:01 +0000187
wdenkec4c5442004-02-09 23:12:24 +0000188 /* Now disable the DS1306 */
189 immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; /* Disable DS1306 Chip */
190 udelay (10);
wdenkaffae2b2002-08-17 09:36:01 +0000191
wdenkec4c5442004-02-09 23:12:24 +0000192 /* Set standard MPC8xx clock to the same time so Linux will
193 * see the time even if it doesn't have a DS1306 clock driver.
194 * This helps with experimenting with standard kernels.
195 */
196 {
197 ulong tim;
wdenkaffae2b2002-08-17 09:36:01 +0000198
wdenkec4c5442004-02-09 23:12:24 +0000199 tim = mktime (tmp->tm_year, tmp->tm_mon, tmp->tm_mday,
200 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
wdenkaffae2b2002-08-17 09:36:01 +0000201
wdenkec4c5442004-02-09 23:12:24 +0000202 immap->im_sitk.sitk_rtck = KAPWR_KEY;
203 immap->im_sit.sit_rtc = tim;
204 }
wdenkaffae2b2002-08-17 09:36:01 +0000205
wdenkec4c5442004-02-09 23:12:24 +0000206 debug ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
207 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
208 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
Jean-Christophe PLAGNIOL-VILLARDd1e23192008-09-01 23:06:23 +0200209
210 return 0;
wdenkaffae2b2002-08-17 09:36:01 +0000211}
212
213/* ------------------------------------------------------------------------- */
214
215/* Initialize Port B for software SPI */
wdenkec4c5442004-02-09 23:12:24 +0000216static void init_spi (void)
217{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
wdenkaffae2b2002-08-17 09:36:01 +0000219
wdenkec4c5442004-02-09 23:12:24 +0000220 /* Force output pins to begin at logic 0 */
221 immap->im_cpm.cp_pbdat &= ~(PB_SPI_CE | PB_SPIMOSI | PB_SPISCK);
wdenkaffae2b2002-08-17 09:36:01 +0000222
wdenkec4c5442004-02-09 23:12:24 +0000223 /* Set these 3 signals as outputs */
224 immap->im_cpm.cp_pbdir |= (PB_SPIMOSI | PB_SPI_CE | PB_SPISCK);
wdenkaffae2b2002-08-17 09:36:01 +0000225
wdenkec4c5442004-02-09 23:12:24 +0000226 immap->im_cpm.cp_pbdir &= ~PB_SPIMISO; /* Make MISO pin an input */
227 udelay (10);
wdenkaffae2b2002-08-17 09:36:01 +0000228}
229
230/* ------------------------------------------------------------------------- */
231
232/* NOTE: soft_spi_send() assumes that the I/O lines are configured already */
wdenkec4c5442004-02-09 23:12:24 +0000233static void soft_spi_send (unsigned char n)
wdenkaffae2b2002-08-17 09:36:01 +0000234{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
wdenkec4c5442004-02-09 23:12:24 +0000236 unsigned char bitpos; /* bit position to receive */
237 unsigned char i; /* Loop Control */
wdenkaffae2b2002-08-17 09:36:01 +0000238
wdenkec4c5442004-02-09 23:12:24 +0000239 /* bit position to send, start with most significant bit */
240 bitpos = 0x80;
wdenkaffae2b2002-08-17 09:36:01 +0000241
wdenkec4c5442004-02-09 23:12:24 +0000242 /* Send 8 bits to software SPI */
243 for (i = 0; i < 8; i++) { /* Loop for 8 bits */
244 immap->im_cpm.cp_pbdat |= PB_SPISCK; /* Raise SCK */
wdenkaffae2b2002-08-17 09:36:01 +0000245
wdenkec4c5442004-02-09 23:12:24 +0000246 if (n & bitpos)
247 immap->im_cpm.cp_pbdat |= PB_SPIMOSI; /* Set MOSI to 1 */
248 else
249 immap->im_cpm.cp_pbdat &= ~PB_SPIMOSI; /* Set MOSI to 0 */
250 udelay (10);
wdenkaffae2b2002-08-17 09:36:01 +0000251
wdenkec4c5442004-02-09 23:12:24 +0000252 immap->im_cpm.cp_pbdat &= ~PB_SPISCK; /* Lower SCK */
253 udelay (10);
wdenkaffae2b2002-08-17 09:36:01 +0000254
wdenkec4c5442004-02-09 23:12:24 +0000255 bitpos >>= 1; /* Shift for next bit position */
256 }
wdenkaffae2b2002-08-17 09:36:01 +0000257}
258
259/* ------------------------------------------------------------------------- */
260
261/* NOTE: soft_spi_read() assumes that the I/O lines are configured already */
wdenkec4c5442004-02-09 23:12:24 +0000262static unsigned char soft_spi_read (void)
wdenkaffae2b2002-08-17 09:36:01 +0000263{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
wdenkaffae2b2002-08-17 09:36:01 +0000265
wdenkec4c5442004-02-09 23:12:24 +0000266 unsigned char spi_byte = 0; /* Return value, assume success */
267 unsigned char bitpos; /* bit position to receive */
268 unsigned char i; /* Loop Control */
wdenkaffae2b2002-08-17 09:36:01 +0000269
wdenkec4c5442004-02-09 23:12:24 +0000270 /* bit position to receive, start with most significant bit */
271 bitpos = 0x80;
wdenkaffae2b2002-08-17 09:36:01 +0000272
wdenkec4c5442004-02-09 23:12:24 +0000273 /* Read 8 bits here */
274 for (i = 0; i < 8; i++) { /* Do 8 bits in loop */
275 immap->im_cpm.cp_pbdat |= PB_SPISCK; /* Raise SCK */
276 udelay (10);
277 if (immap->im_cpm.cp_pbdat & PB_SPIMISO) /* Get a bit of data */
278 spi_byte |= bitpos; /* Set data accordingly */
279 immap->im_cpm.cp_pbdat &= ~PB_SPISCK; /* Lower SCK */
280 udelay (10);
281 bitpos >>= 1; /* Shift for next bit position */
282 }
wdenkaffae2b2002-08-17 09:36:01 +0000283
wdenkec4c5442004-02-09 23:12:24 +0000284 return spi_byte; /* Return the byte read */
wdenkaffae2b2002-08-17 09:36:01 +0000285}
286
287/* ------------------------------------------------------------------------- */
288
wdenkec4c5442004-02-09 23:12:24 +0000289void rtc_reset (void)
290{
291 return; /* nothing to do */
292}
293
294#else /* not CONFIG_SXNI855T */
295/* ************************************************************************* */
296
wdenk3f85ce22004-02-23 16:11:30 +0000297static unsigned char rtc_read (unsigned char reg);
298static void rtc_write (unsigned char reg, unsigned char val);
299
Haavard Skinnemoend255bb02008-05-16 11:10:31 +0200300static struct spi_slave *slave;
301
wdenkec4c5442004-02-09 23:12:24 +0000302/* read clock time from DS1306 and return it in *tmp */
Yuri Tikhonovb73a19e2008-03-20 17:56:04 +0300303int rtc_get (struct rtc_time *tmp)
wdenkec4c5442004-02-09 23:12:24 +0000304{
305 unsigned char sec, min, hour, mday, wday, mon, year;
306
Haavard Skinnemoend255bb02008-05-16 11:10:31 +0200307 /*
308 * Assuming Vcc = 2.0V (lowest speed)
309 *
310 * REVISIT: If we add an rtc_init() function we can do this
311 * step just once.
312 */
313 if (!slave) {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200314 slave = spi_setup_slave(0, CONFIG_SYS_SPI_RTC_DEVID, 600000,
Haavard Skinnemoend255bb02008-05-16 11:10:31 +0200315 SPI_MODE_3 | SPI_CS_HIGH);
316 if (!slave)
317 return;
318 }
319
320 if (spi_claim_bus(slave))
321 return;
322
wdenkec4c5442004-02-09 23:12:24 +0000323 sec = rtc_read (RTC_SECONDS);
324 min = rtc_read (RTC_MINUTES);
325 hour = rtc_read (RTC_HOURS);
326 mday = rtc_read (RTC_DATE_OF_MONTH);
327 wday = rtc_read (RTC_DAY_OF_WEEK);
328 mon = rtc_read (RTC_MONTH);
329 year = rtc_read (RTC_YEAR);
330
Haavard Skinnemoend255bb02008-05-16 11:10:31 +0200331 spi_release_bus(slave);
332
wdenkec4c5442004-02-09 23:12:24 +0000333 debug ("Get RTC year: %02x mon: %02x mday: %02x wday: %02x "
334 "hr: %02x min: %02x sec: %02x\n",
335 year, mon, mday, wday, hour, min, sec);
336 debug ("Alarms[0]: wday: %02x hour: %02x min: %02x sec: %02x\n",
337 rtc_read (RTC_DAY_OF_WEEK_ALARM0),
338 rtc_read (RTC_HOURS_ALARM0),
339 rtc_read (RTC_MINUTES_ALARM0), rtc_read (RTC_SECONDS_ALARM0));
340 debug ("Alarms[1]: wday: %02x hour: %02x min: %02x sec: %02x\n",
341 rtc_read (RTC_DAY_OF_WEEK_ALARM1),
342 rtc_read (RTC_HOURS_ALARM1),
343 rtc_read (RTC_MINUTES_ALARM1), rtc_read (RTC_SECONDS_ALARM1));
344
345 tmp->tm_sec = bcd2bin (sec & 0x7F); /* convert Seconds */
346 tmp->tm_min = bcd2bin (min & 0x7F); /* convert Minutes */
347
348 /* convert Hours */
349 tmp->tm_hour = (hour & 0x40)
350 ? ((hour & 0x20) /* 12 hour mode */
351 ? bcd2bin (hour & 0x1F) + 11 /* PM */
352 : bcd2bin (hour & 0x1F) - 1 /* AM */
353 )
354 : bcd2bin (hour & 0x3F); /* 24 hour mode */
355
356 tmp->tm_mday = bcd2bin (mday & 0x3F); /* convert Day of the Month */
357 tmp->tm_mon = bcd2bin (mon & 0x1F); /* convert Month */
358 tmp->tm_year = bcd2bin (year) + 2000; /* convert Year */
359 tmp->tm_wday = bcd2bin (wday & 0x07) - 1; /* convert Day of the Week */
360 tmp->tm_yday = 0;
361 tmp->tm_isdst = 0;
362
363 debug ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
364 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
365 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
Yuri Tikhonovb73a19e2008-03-20 17:56:04 +0300366
367 return 0;
wdenkec4c5442004-02-09 23:12:24 +0000368}
369
370/* ------------------------------------------------------------------------- */
371
372/* set clock time from *tmp in DS1306 RTC */
Jean-Christophe PLAGNIOL-VILLARDd1e23192008-09-01 23:06:23 +0200373int rtc_set (struct rtc_time *tmp)
wdenkec4c5442004-02-09 23:12:24 +0000374{
Haavard Skinnemoend255bb02008-05-16 11:10:31 +0200375 /* Assuming Vcc = 2.0V (lowest speed) */
376 if (!slave) {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200377 slave = spi_setup_slave(0, CONFIG_SYS_SPI_RTC_DEVID, 600000,
Haavard Skinnemoend255bb02008-05-16 11:10:31 +0200378 SPI_MODE_3 | SPI_CS_HIGH);
379 if (!slave)
380 return;
381 }
382
383 if (spi_claim_bus(slave))
384 return;
385
wdenkec4c5442004-02-09 23:12:24 +0000386 debug ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
387 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
388 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
389
wdenkec4c5442004-02-09 23:12:24 +0000390 rtc_write (RTC_SECONDS, bin2bcd (tmp->tm_sec));
Wolfgang Denkda4849f2006-05-03 01:04:58 +0200391 rtc_write (RTC_MINUTES, bin2bcd (tmp->tm_min));
392 rtc_write (RTC_HOURS, bin2bcd (tmp->tm_hour));
393 rtc_write (RTC_DAY_OF_WEEK, bin2bcd (tmp->tm_wday + 1));
394 rtc_write (RTC_DATE_OF_MONTH, bin2bcd (tmp->tm_mday));
395 rtc_write (RTC_MONTH, bin2bcd (tmp->tm_mon));
396 rtc_write (RTC_YEAR, bin2bcd (tmp->tm_year - 2000));
Haavard Skinnemoend255bb02008-05-16 11:10:31 +0200397
398 spi_release_bus(slave);
wdenkec4c5442004-02-09 23:12:24 +0000399}
400
401/* ------------------------------------------------------------------------- */
402
403/* reset the DS1306 */
404void rtc_reset (void)
405{
Haavard Skinnemoend255bb02008-05-16 11:10:31 +0200406 /* Assuming Vcc = 2.0V (lowest speed) */
407 if (!slave) {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200408 slave = spi_setup_slave(0, CONFIG_SYS_SPI_RTC_DEVID, 600000,
Haavard Skinnemoend255bb02008-05-16 11:10:31 +0200409 SPI_MODE_3 | SPI_CS_HIGH);
410 if (!slave)
411 return;
412 }
413
414 if (spi_claim_bus(slave))
415 return;
416
wdenkec4c5442004-02-09 23:12:24 +0000417 /* clear the control register */
418 rtc_write (RTC_CONTROL, 0x00); /* 1st step: reset WP */
419 rtc_write (RTC_CONTROL, 0x00); /* 2nd step: reset 1Hz, AIE1, AIE0 */
420
421 /* reset all alarms */
422 rtc_write (RTC_SECONDS_ALARM0, 0x00);
423 rtc_write (RTC_SECONDS_ALARM1, 0x00);
424 rtc_write (RTC_MINUTES_ALARM0, 0x00);
425 rtc_write (RTC_MINUTES_ALARM1, 0x00);
426 rtc_write (RTC_HOURS_ALARM0, 0x00);
427 rtc_write (RTC_HOURS_ALARM1, 0x00);
428 rtc_write (RTC_DAY_OF_WEEK_ALARM0, 0x00);
429 rtc_write (RTC_DAY_OF_WEEK_ALARM1, 0x00);
Haavard Skinnemoend255bb02008-05-16 11:10:31 +0200430
431 spi_release_bus(slave);
wdenkec4c5442004-02-09 23:12:24 +0000432}
433
434/* ------------------------------------------------------------------------- */
435
436static unsigned char rtc_read (unsigned char reg)
437{
Haavard Skinnemoend255bb02008-05-16 11:10:31 +0200438 int ret;
wdenkec4c5442004-02-09 23:12:24 +0000439
Haavard Skinnemoend255bb02008-05-16 11:10:31 +0200440 ret = spi_w8r8(slave, reg);
441 return ret < 0 ? 0 : ret;
wdenkec4c5442004-02-09 23:12:24 +0000442}
443
444/* ------------------------------------------------------------------------- */
445
446static void rtc_write (unsigned char reg, unsigned char val)
447{
448 unsigned char dout[2]; /* SPI Output Data Bytes */
449 unsigned char din[2]; /* SPI Input Data Bytes */
450
451 dout[0] = 0x80 | reg;
452 dout[1] = val;
453
Haavard Skinnemoend255bb02008-05-16 11:10:31 +0200454 spi_xfer (slave, 16, dout, din, SPI_XFER_BEGIN | SPI_XFER_END);
wdenkec4c5442004-02-09 23:12:24 +0000455}
456
457#endif /* end of code exclusion (see #ifdef CONFIG_SXNI855T above) */
458
wdenkaffae2b2002-08-17 09:36:01 +0000459#endif