| Paweł Anikiel | 6129827 | 2022-06-17 12:47:20 +0200 | [diff] [blame] | 1 | CONFIG_ARM=y |
| Philip Oberfichtner | 1116888 | 2022-08-17 15:07:12 +0200 | [diff] [blame] | 2 | CONFIG_SYS_L2_PL310=y |
| Paweł Anikiel | 6129827 | 2022-06-17 12:47:20 +0200 | [diff] [blame] | 3 | CONFIG_ARCH_SOCFPGA=y |
| Paweł Anikiel | 6129827 | 2022-06-17 12:47:20 +0200 | [diff] [blame] | 4 | CONFIG_ENV_SIZE=0x10000 |
| 5 | CONFIG_ENV_OFFSET=0x4400 |
| Tom Rini | d98a6a9 | 2022-07-04 08:15:34 -0400 | [diff] [blame] | 6 | CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_chameleonv3_480_2" |
| 7 | CONFIG_SPL_TEXT_BASE=0xFFE00000 |
| 8 | CONFIG_SPL_DRIVERS_MISC=y |
| 9 | CONFIG_TARGET_SOCFPGA_CHAMELEONV3=y |
| 10 | CONFIG_SPL_FS_FAT=y |
| 11 | CONFIG_DISTRO_DEFAULTS=y |
| 12 | CONFIG_FIT=y |
| 13 | CONFIG_SPL_FIT=y |
| 14 | # CONFIG_USE_SPL_FIT_GENERATOR is not set |
| 15 | CONFIG_MISC_INIT_R=y |
| Tom Rini | 36b661d | 2022-07-11 10:18:13 -0400 | [diff] [blame] | 16 | CONFIG_SPL_NO_BSS_LIMIT=y |
| 17 | CONFIG_SYS_SPL_MALLOC=y |
| 18 | CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y |
| 19 | CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0xffe2b000 |
| 20 | CONFIG_SYS_SPL_MALLOC_SIZE=0x15000 |
| Tom Rini | d98a6a9 | 2022-07-04 08:15:34 -0400 | [diff] [blame] | 21 | CONFIG_SPL_ENV_SUPPORT=y |
| 22 | CONFIG_SPL_FPGA=y |
| Tom Rini | 36b661d | 2022-07-11 10:18:13 -0400 | [diff] [blame] | 23 | CONFIG_SYS_BOOTM_LEN=0x2000000 |
| Tom Rini | d98a6a9 | 2022-07-04 08:15:34 -0400 | [diff] [blame] | 24 | CONFIG_ENV_IS_IN_MMC=y |
| 25 | CONFIG_SYS_I2C_DW=y |
| 26 | CONFIG_MISC=y |
| 27 | CONFIG_ATSHA204A=y |
| 28 | CONFIG_FS_LOADER=y |
| 29 | CONFIG_SPL_FS_LOADER=y |
| 30 | CONFIG_MMC_DW=y |
| Paweł Anikiel | 6129827 | 2022-06-17 12:47:20 +0200 | [diff] [blame] | 31 | CONFIG_ETH_DESIGNWARE=y |
| 32 | CONFIG_TIMER=y |
| 33 | CONFIG_SPL_TIMER=y |
| 34 | CONFIG_DESIGNWARE_APB_TIMER=y |