blob: 7c31f47953bd0c05497df7f37aa8be65cb6b6db8 [file] [log] [blame]
Dave Liu24c3aca2006-12-07 21:13:15 +08001/*
2 * Copyright (C) 2006 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Jerry Van Barenae0b05d2009-02-05 22:18:02 -050011 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
Dave Liu24c3aca2006-12-07 21:13:15 +080012 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
17 * MA 02111-1307 USA
18 */
19
20#ifndef __CONFIG_H
21#define __CONFIG_H
22
Dave Liu24c3aca2006-12-07 21:13:15 +080023/*
24 * High Level Configuration Options
25 */
26#define CONFIG_E300 1 /* E300 family */
27#define CONFIG_QE 1 /* Has QE */
Peter Tyser0f898602009-05-22 17:23:24 -050028#define CONFIG_MPC83xx 1 /* MPC83xx family */
Peter Tyser2c7920a2009-05-22 17:23:25 -050029#define CONFIG_MPC832x 1 /* MPC832x CPU specific */
Dave Liu24c3aca2006-12-07 21:13:15 +080030#define CONFIG_MPC832XEMDS 1 /* MPC832XEMDS board specific */
Wolfgang Denk2ae18242010-10-06 09:05:45 +020031
32#define CONFIG_SYS_TEXT_BASE 0xFE000000
Dave Liu24c3aca2006-12-07 21:13:15 +080033
34/*
35 * System Clock Setup
36 */
37#ifdef CONFIG_PCISLAVE
38#define CONFIG_83XX_PCICLK 66000000 /* in HZ */
39#else
40#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
41#endif
42
43#ifndef CONFIG_SYS_CLK_FREQ
44#define CONFIG_SYS_CLK_FREQ 66000000
45#endif
46
47/*
48 * Hardware Reset Configuration Word
49 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020050#define CONFIG_SYS_HRCW_LOW (\
Dave Liu24c3aca2006-12-07 21:13:15 +080051 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
52 HRCWL_DDR_TO_SCB_CLK_2X1 |\
53 HRCWL_VCO_1X2 |\
54 HRCWL_CSB_TO_CLKIN_2X1 |\
55 HRCWL_CORE_TO_CSB_2X1 |\
56 HRCWL_CE_PLL_VCO_DIV_2 |\
57 HRCWL_CE_PLL_DIV_1X1 |\
58 HRCWL_CE_TO_PLL_1X3)
59
60#ifdef CONFIG_PCISLAVE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020061#define CONFIG_SYS_HRCW_HIGH (\
Dave Liu24c3aca2006-12-07 21:13:15 +080062 HRCWH_PCI_AGENT |\
63 HRCWH_PCI1_ARBITER_DISABLE |\
64 HRCWH_CORE_ENABLE |\
65 HRCWH_FROM_0XFFF00100 |\
66 HRCWH_BOOTSEQ_DISABLE |\
67 HRCWH_SW_WATCHDOG_DISABLE |\
68 HRCWH_ROM_LOC_LOCAL_16BIT |\
69 HRCWH_BIG_ENDIAN |\
70 HRCWH_LALE_NORMAL)
71#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072#define CONFIG_SYS_HRCW_HIGH (\
Dave Liu24c3aca2006-12-07 21:13:15 +080073 HRCWH_PCI_HOST |\
74 HRCWH_PCI1_ARBITER_ENABLE |\
75 HRCWH_CORE_ENABLE |\
76 HRCWH_FROM_0X00000100 |\
77 HRCWH_BOOTSEQ_DISABLE |\
78 HRCWH_SW_WATCHDOG_DISABLE |\
79 HRCWH_ROM_LOC_LOCAL_16BIT |\
80 HRCWH_BIG_ENDIAN |\
81 HRCWH_LALE_NORMAL)
82#endif
83
84/*
85 * System IO Config
86 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020087#define CONFIG_SYS_SICRL 0x00000000
Dave Liu24c3aca2006-12-07 21:13:15 +080088
89#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
Tony Li14778582007-08-17 10:35:59 +080090#define CONFIG_BOARD_EARLY_INIT_R
Dave Liu24c3aca2006-12-07 21:13:15 +080091
92/*
93 * IMMR new address
94 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020095#define CONFIG_SYS_IMMR 0xE0000000
Dave Liu24c3aca2006-12-07 21:13:15 +080096
97/*
98 * DDR Setup
99 */
Joe Hershberger989091a2011-10-11 23:57:13 -0500100#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
101#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
Joe Hershberger989091a2011-10-11 23:57:13 -0500103#define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */
Dave Liu24c3aca2006-12-07 21:13:15 +0800104
105#undef CONFIG_SPD_EEPROM
106#if defined(CONFIG_SPD_EEPROM)
107/* Determine DDR configuration from I2C interface
108 */
109#define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */
110#else
111/* Manually set up DDR parameters
112 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#define CONFIG_SYS_DDR_SIZE 128 /* MB */
Joe Hershberger2fef4022011-10-11 23:57:29 -0500114#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
115 | CSCONFIG_AP \
116 | CSCONFIG_ODT_WR_CFG \
117 | CSCONFIG_ROW_BIT_13 \
118 | CSCONFIG_COL_BIT_10)
119 /* 0x80840102 */
120#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
121 | (0 << TIMING_CFG0_WRT_SHIFT) \
122 | (0 << TIMING_CFG0_RRT_SHIFT) \
123 | (0 << TIMING_CFG0_WWT_SHIFT) \
124 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
125 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
126 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
127 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
128 /* 0x00220802 */
129#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
130 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
131 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
132 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
133 | (13 << TIMING_CFG1_REFREC_SHIFT) \
134 | (3 << TIMING_CFG1_WRREC_SHIFT) \
135 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
136 | (2 << TIMING_CFG1_WRTORD_SHIFT))
137 /* 0x3935D322 */
138#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
139 | (31 << TIMING_CFG2_CPO_SHIFT) \
140 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
141 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
142 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
143 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
144 | (10 << TIMING_CFG2_FOUR_ACT_SHIFT))
145 /* 0x0F9048CA */
Joe Hershberger989091a2011-10-11 23:57:13 -0500146#define CONFIG_SYS_DDR_TIMING_3 0x00000000
Joe Hershberger2fef4022011-10-11 23:57:29 -0500147#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
148 /* 0x02000000 */
149#define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
150 | (0x0232 << SDRAM_MODE_SD_SHIFT))
151 /* 0x44400232 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_DDR_MODE2 0x8000c000
Joe Hershberger2fef4022011-10-11 23:57:29 -0500153#define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
154 | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
155 /* 0x03200064 */
Joe Hershberger989091a2011-10-11 23:57:13 -0500156#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
Joe Hershberger2fef4022011-10-11 23:57:29 -0500157#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
158 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
159 | SDRAM_CFG_32_BE)
160 /* 0x43080000 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
Dave Liu24c3aca2006-12-07 21:13:15 +0800162#endif
163
164/*
165 * Memory test
166 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
168#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
169#define CONFIG_SYS_MEMTEST_END 0x00100000
Dave Liu24c3aca2006-12-07 21:13:15 +0800170
171/*
172 * The reserved memory
173 */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200174#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Dave Liu24c3aca2006-12-07 21:13:15 +0800175
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
177#define CONFIG_SYS_RAMBOOT
Dave Liu24c3aca2006-12-07 21:13:15 +0800178#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#undef CONFIG_SYS_RAMBOOT
Dave Liu24c3aca2006-12-07 21:13:15 +0800180#endif
181
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
Joe Hershberger989091a2011-10-11 23:57:13 -0500183#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
Timur Tabi3b6b2562012-03-17 17:44:00 -0500184#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
Dave Liu24c3aca2006-12-07 21:13:15 +0800185
186/*
187 * Initial RAM Base Address Setup
188 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#define CONFIG_SYS_INIT_RAM_LOCK 1
Joe Hershberger989091a2011-10-11 23:57:13 -0500190#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM addr */
191#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
192#define CONFIG_SYS_GBL_DATA_OFFSET \
193 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Dave Liu24c3aca2006-12-07 21:13:15 +0800194
195/*
196 * Local Bus Configuration & Clock Setup
197 */
Kim Phillipsc7190f02009-09-25 18:19:44 -0500198#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
199#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200#define CONFIG_SYS_LBC_LBCR 0x00000000
Dave Liu24c3aca2006-12-07 21:13:15 +0800201
202/*
203 * FLASH on the Local Bus
204 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
Joe Hershberger989091a2011-10-11 23:57:13 -0500206#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
207#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
208#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
209#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
Dave Liu24c3aca2006-12-07 21:13:15 +0800210
Joe Hershberger989091a2011-10-11 23:57:13 -0500211 /* Window base at flash base */
212#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500213#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
Dave Liu24c3aca2006-12-07 21:13:15 +0800214
Joe Hershberger989091a2011-10-11 23:57:13 -0500215#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500216 | BR_PS_16 /* 16 bit port */ \
217 | BR_MS_GPCM /* MSEL = GPCM */ \
218 | BR_V) /* valid */
219#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
220 | OR_GPCM_XAM \
221 | OR_GPCM_CSNT \
222 | OR_GPCM_ACS_DIV2 \
223 | OR_GPCM_XACS \
224 | OR_GPCM_SCY_15 \
225 | OR_GPCM_TRLX_SET \
226 | OR_GPCM_EHTR_SET \
227 | OR_GPCM_EAD)
228 /* 0xfe006ff7 */
Dave Liu24c3aca2006-12-07 21:13:15 +0800229
Joe Hershberger989091a2011-10-11 23:57:13 -0500230#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
231#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
Dave Liu24c3aca2006-12-07 21:13:15 +0800232
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#undef CONFIG_SYS_FLASH_CHECKSUM
Dave Liu24c3aca2006-12-07 21:13:15 +0800234
235/*
236 * BCSR on the Local Bus
237 */
Joe Hershberger989091a2011-10-11 23:57:13 -0500238#define CONFIG_SYS_BCSR 0xF8000000
239 /* Access window base at BCSR base */
240#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500241#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
Dave Liu24c3aca2006-12-07 21:13:15 +0800242
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500243#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
244 | BR_PS_8 \
245 | BR_MS_GPCM \
246 | BR_V)
247#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
248 | OR_GPCM_XAM \
249 | OR_GPCM_CSNT \
250 | OR_GPCM_XACS \
251 | OR_GPCM_SCY_15 \
252 | OR_GPCM_TRLX_SET \
253 | OR_GPCM_EHTR_SET \
254 | OR_GPCM_EAD)
255 /* 0xFFFFE9F7 */
Dave Liu24c3aca2006-12-07 21:13:15 +0800256
257/*
258 * Windows to access PIB via local bus
259 */
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500260 /* PIB window base 0xF8008000 */
261#define CONFIG_SYS_PIB_BASE 0xF8008000
262#define CONFIG_SYS_PIB_WINDOW_SIZE (32 * 1024)
263#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PIB_BASE
264#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB)
Dave Liu24c3aca2006-12-07 21:13:15 +0800265
266/*
267 * CS2 on Local Bus, to PIB
268 */
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500269#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_PIB_BASE \
270 | BR_PS_8 \
271 | BR_MS_GPCM \
272 | BR_V)
273 /* 0xF8008801 */
274#define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
275 | OR_GPCM_XAM \
276 | OR_GPCM_CSNT \
277 | OR_GPCM_XACS \
278 | OR_GPCM_SCY_15 \
279 | OR_GPCM_TRLX_SET \
280 | OR_GPCM_EHTR_SET \
281 | OR_GPCM_EAD)
282 /* 0xffffe9f7 */
Dave Liu24c3aca2006-12-07 21:13:15 +0800283
284/*
285 * CS3 on Local Bus, to PIB
286 */
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500287#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_PIB_BASE + \
288 CONFIG_SYS_PIB_WINDOW_SIZE) \
289 | BR_PS_8 \
290 | BR_MS_GPCM \
291 | BR_V)
292 /* 0xF8010801 */
293#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
294 | OR_GPCM_XAM \
295 | OR_GPCM_CSNT \
296 | OR_GPCM_XACS \
297 | OR_GPCM_SCY_15 \
298 | OR_GPCM_TRLX_SET \
299 | OR_GPCM_EHTR_SET \
300 | OR_GPCM_EAD)
301 /* 0xffffe9f7 */
Dave Liu24c3aca2006-12-07 21:13:15 +0800302
303/*
304 * Serial Port
305 */
306#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200307#define CONFIG_SYS_NS16550
308#define CONFIG_SYS_NS16550_SERIAL
309#define CONFIG_SYS_NS16550_REG_SIZE 1
310#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Dave Liu24c3aca2006-12-07 21:13:15 +0800311
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200312#define CONFIG_SYS_BAUDRATE_TABLE \
Joe Hershberger989091a2011-10-11 23:57:13 -0500313 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
Dave Liu24c3aca2006-12-07 21:13:15 +0800314
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200315#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
316#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
Dave Liu24c3aca2006-12-07 21:13:15 +0800317
Kim Phillips22d71a72007-02-27 18:41:08 -0600318#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Kim Phillipsa059e902010-04-15 17:36:05 -0500319#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Dave Liu24c3aca2006-12-07 21:13:15 +0800320/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200321#define CONFIG_SYS_HUSH_PARSER
Dave Liu24c3aca2006-12-07 21:13:15 +0800322
323/* pass open firmware flat tree */
Kim Phillips35cc4e42007-08-15 22:30:39 -0500324#define CONFIG_OF_LIBFDT 1
Dave Liu24c3aca2006-12-07 21:13:15 +0800325#define CONFIG_OF_BOARD_SETUP 1
Kim Phillips5b8bc602007-12-20 14:09:22 -0600326#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Dave Liu24c3aca2006-12-07 21:13:15 +0800327
328/* I2C */
329#define CONFIG_HARD_I2C /* I2C with hardware support */
330#undef CONFIG_SOFT_I2C /* I2C bit-banged */
331#define CONFIG_FSL_I2C
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200332#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
333#define CONFIG_SYS_I2C_SLAVE 0x7F
334#define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */
335#define CONFIG_SYS_I2C_OFFSET 0x3000
Dave Liu24c3aca2006-12-07 21:13:15 +0800336
337/*
338 * Config on-board RTC
339 */
340#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200341#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
Dave Liu24c3aca2006-12-07 21:13:15 +0800342
343/*
344 * General PCI
345 * Addresses are mapped 1-1.
346 */
Kim Phillips9993e192009-07-18 18:42:13 -0500347#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
348#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
349#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
350#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
351#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
352#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
353#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
354#define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000
355#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
Dave Liu24c3aca2006-12-07 21:13:15 +0800356
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200357#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
358#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
359#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
Dave Liu24c3aca2006-12-07 21:13:15 +0800360
361
362#ifdef CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +0000363#define CONFIG_PCI_INDIRECT_BRIDGE
Dave Liu24c3aca2006-12-07 21:13:15 +0800364
Dave Liu24c3aca2006-12-07 21:13:15 +0800365#define CONFIG_PCI_PNP /* do pci plug-and-play */
Kim Phillips9993e192009-07-18 18:42:13 -0500366#define CONFIG_83XX_PCI_STREAMING
Dave Liu24c3aca2006-12-07 21:13:15 +0800367
368#undef CONFIG_EEPRO100
369#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200370#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
Dave Liu24c3aca2006-12-07 21:13:15 +0800371
372#endif /* CONFIG_PCI */
373
Dave Liu24c3aca2006-12-07 21:13:15 +0800374/*
375 * QE UEC ethernet configuration
376 */
377#define CONFIG_UEC_ETH
Kim Phillips78b7a8e2010-07-26 18:34:57 -0500378#define CONFIG_ETHPRIME "UEC0"
Dave Liu24c3aca2006-12-07 21:13:15 +0800379
380#define CONFIG_UEC_ETH1 /* ETH3 */
381
382#ifdef CONFIG_UEC_ETH1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200383#define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */
384#define CONFIG_SYS_UEC1_RX_CLK QE_CLK9
385#define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
386#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
387#define CONFIG_SYS_UEC1_PHY_ADDR 3
Andy Fleming865ff852011-04-13 00:37:12 -0500388#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
Heiko Schocher582c55a2010-01-20 09:04:28 +0100389#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
Dave Liu24c3aca2006-12-07 21:13:15 +0800390#endif
391
392#define CONFIG_UEC_ETH2 /* ETH4 */
393
394#ifdef CONFIG_UEC_ETH2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200395#define CONFIG_SYS_UEC2_UCC_NUM 3 /* UCC4 */
396#define CONFIG_SYS_UEC2_RX_CLK QE_CLK7
397#define CONFIG_SYS_UEC2_TX_CLK QE_CLK8
398#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
399#define CONFIG_SYS_UEC2_PHY_ADDR 4
Andy Fleming865ff852011-04-13 00:37:12 -0500400#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
Heiko Schocher582c55a2010-01-20 09:04:28 +0100401#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
Dave Liu24c3aca2006-12-07 21:13:15 +0800402#endif
403
404/*
405 * Environment
406 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200407#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200408 #define CONFIG_ENV_IS_IN_FLASH 1
Joe Hershberger989091a2011-10-11 23:57:13 -0500409 #define CONFIG_ENV_ADDR \
410 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200411 #define CONFIG_ENV_SECT_SIZE 0x20000
412 #define CONFIG_ENV_SIZE 0x2000
Dave Liu24c3aca2006-12-07 21:13:15 +0800413#else
Joe Hershberger989091a2011-10-11 23:57:13 -0500414 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200415 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200416 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200417 #define CONFIG_ENV_SIZE 0x2000
Dave Liu24c3aca2006-12-07 21:13:15 +0800418#endif
419
420#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200421#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Dave Liu24c3aca2006-12-07 21:13:15 +0800422
Jon Loeliger8ea54992007-07-04 22:30:06 -0500423/*
Jon Loeliger079a1362007-07-10 10:12:10 -0500424 * BOOTP options
425 */
426#define CONFIG_BOOTP_BOOTFILESIZE
427#define CONFIG_BOOTP_BOOTPATH
428#define CONFIG_BOOTP_GATEWAY
429#define CONFIG_BOOTP_HOSTNAME
430
431
432/*
Jon Loeliger8ea54992007-07-04 22:30:06 -0500433 * Command line configuration.
434 */
435#include <config_cmd_default.h>
436
437#define CONFIG_CMD_PING
438#define CONFIG_CMD_I2C
439#define CONFIG_CMD_ASKENV
440
Dave Liu24c3aca2006-12-07 21:13:15 +0800441#if defined(CONFIG_PCI)
Jon Loeliger8ea54992007-07-04 22:30:06 -0500442 #define CONFIG_CMD_PCI
Dave Liu24c3aca2006-12-07 21:13:15 +0800443#endif
444
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200445#if defined(CONFIG_SYS_RAMBOOT)
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500446 #undef CONFIG_CMD_SAVEENV
Jon Loeliger8ea54992007-07-04 22:30:06 -0500447 #undef CONFIG_CMD_LOADS
448#endif
449
Dave Liu24c3aca2006-12-07 21:13:15 +0800450
451#undef CONFIG_WATCHDOG /* watchdog disabled */
452
453/*
454 * Miscellaneous configurable options
455 */
Joe Hershberger989091a2011-10-11 23:57:13 -0500456#define CONFIG_SYS_LONGHELP /* undef to save memory */
457#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
458#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Dave Liu24c3aca2006-12-07 21:13:15 +0800459
Jon Loeliger8ea54992007-07-04 22:30:06 -0500460#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200461 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Dave Liu24c3aca2006-12-07 21:13:15 +0800462#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200463 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Dave Liu24c3aca2006-12-07 21:13:15 +0800464#endif
465
Joe Hershberger989091a2011-10-11 23:57:13 -0500466 /* Print Buffer Size */
467#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
468#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
469 /* Boot Argument Buffer Size */
470#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
471#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
Dave Liu24c3aca2006-12-07 21:13:15 +0800472
473/*
474 * For booting Linux, the board info and command line data
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700475 * have to be in the first 256 MB of memory, since this is
Dave Liu24c3aca2006-12-07 21:13:15 +0800476 * the maximum mapped by the Linux kernel during initialization.
477 */
Joe Hershberger989091a2011-10-11 23:57:13 -0500478 /* Initial Memory map for Linux */
479#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
Dave Liu24c3aca2006-12-07 21:13:15 +0800480
481/*
482 * Core HID Setup
483 */
Kim Phillips1a2e2032010-04-20 19:37:54 -0500484#define CONFIG_SYS_HID0_INIT 0x000000000
485#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
486 HID0_ENABLE_INSTRUCTION_CACHE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200487#define CONFIG_SYS_HID2 HID2_HBE
Dave Liu24c3aca2006-12-07 21:13:15 +0800488
489/*
Dave Liu24c3aca2006-12-07 21:13:15 +0800490 * MMU Setup
491 */
492
Becky Bruce31d82672008-05-08 19:02:12 -0500493#define CONFIG_HIGH_BATS 1 /* High BATs supported */
494
Dave Liu24c3aca2006-12-07 21:13:15 +0800495/* DDR: cache cacheable */
Joe Hershberger989091a2011-10-11 23:57:13 -0500496#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500497 | BATL_PP_RW \
Joe Hershberger989091a2011-10-11 23:57:13 -0500498 | BATL_MEMCOHERENCE)
499#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
500 | BATU_BL_256M \
501 | BATU_VS \
502 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200503#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
504#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
Dave Liu24c3aca2006-12-07 21:13:15 +0800505
506/* IMMRBAR & PCI IO: cache-inhibit and guarded */
Joe Hershberger989091a2011-10-11 23:57:13 -0500507#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500508 | BATL_PP_RW \
Joe Hershberger989091a2011-10-11 23:57:13 -0500509 | BATL_CACHEINHIBIT \
510 | BATL_GUARDEDSTORAGE)
511#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
512 | BATU_BL_4M \
513 | BATU_VS \
514 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200515#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
516#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
Dave Liu24c3aca2006-12-07 21:13:15 +0800517
518/* BCSR: cache-inhibit and guarded */
Joe Hershberger989091a2011-10-11 23:57:13 -0500519#define CONFIG_SYS_IBAT2L (CONFIG_SYS_BCSR \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500520 | BATL_PP_RW \
Joe Hershberger989091a2011-10-11 23:57:13 -0500521 | BATL_CACHEINHIBIT \
522 | BATL_GUARDEDSTORAGE)
523#define CONFIG_SYS_IBAT2U (CONFIG_SYS_BCSR \
524 | BATU_BL_128K \
525 | BATU_VS \
526 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200527#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
528#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
Dave Liu24c3aca2006-12-07 21:13:15 +0800529
530/* FLASH: icache cacheable, but dcache-inhibit and guarded */
Joe Hershberger989091a2011-10-11 23:57:13 -0500531#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500532 | BATL_PP_RW \
Joe Hershberger989091a2011-10-11 23:57:13 -0500533 | BATL_MEMCOHERENCE)
534#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \
535 | BATU_BL_32M \
536 | BATU_VS \
537 | BATU_VP)
538#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500539 | BATL_PP_RW \
Joe Hershberger989091a2011-10-11 23:57:13 -0500540 | BATL_CACHEINHIBIT \
541 | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200542#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
Dave Liu24c3aca2006-12-07 21:13:15 +0800543
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200544#define CONFIG_SYS_IBAT4L (0)
545#define CONFIG_SYS_IBAT4U (0)
546#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
547#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
Dave Liu24c3aca2006-12-07 21:13:15 +0800548
549/* Stack in dcache: cacheable, no memory coherence */
Joe Hershberger72cd4082011-10-11 23:57:28 -0500550#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
Joe Hershberger989091a2011-10-11 23:57:13 -0500551#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \
552 | BATU_BL_128K \
553 | BATU_VS \
554 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200555#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
556#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
Dave Liu24c3aca2006-12-07 21:13:15 +0800557
558#ifdef CONFIG_PCI
559/* PCI MEM space: cacheable */
Joe Hershberger989091a2011-10-11 23:57:13 -0500560#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500561 | BATL_PP_RW \
Joe Hershberger989091a2011-10-11 23:57:13 -0500562 | BATL_MEMCOHERENCE)
563#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS \
564 | BATU_BL_256M \
565 | BATU_VS \
566 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200567#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
568#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
Dave Liu24c3aca2006-12-07 21:13:15 +0800569/* PCI MMIO space: cache-inhibit and guarded */
Joe Hershberger989091a2011-10-11 23:57:13 -0500570#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500571 | BATL_PP_RW \
Joe Hershberger989091a2011-10-11 23:57:13 -0500572 | BATL_CACHEINHIBIT \
573 | BATL_GUARDEDSTORAGE)
574#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS \
575 | BATU_BL_256M \
576 | BATU_VS \
577 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200578#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
579#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Dave Liu24c3aca2006-12-07 21:13:15 +0800580#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200581#define CONFIG_SYS_IBAT6L (0)
582#define CONFIG_SYS_IBAT6U (0)
583#define CONFIG_SYS_IBAT7L (0)
584#define CONFIG_SYS_IBAT7U (0)
585#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
586#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
587#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
588#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Dave Liu24c3aca2006-12-07 21:13:15 +0800589#endif
590
Jon Loeliger8ea54992007-07-04 22:30:06 -0500591#if defined(CONFIG_CMD_KGDB)
Dave Liu24c3aca2006-12-07 21:13:15 +0800592#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
593#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
594#endif
595
596/*
597 * Environment Configuration
Kim Phillips9993e192009-07-18 18:42:13 -0500598 */ #define CONFIG_ENV_OVERWRITE
Dave Liu24c3aca2006-12-07 21:13:15 +0800599
600#if defined(CONFIG_UEC_ETH)
Kim Phillips977b5752008-01-09 15:24:06 -0600601#define CONFIG_HAS_ETH0
Dave Liu24c3aca2006-12-07 21:13:15 +0800602#define CONFIG_HAS_ETH1
Dave Liu24c3aca2006-12-07 21:13:15 +0800603#endif
604
605#define CONFIG_BAUDRATE 115200
606
Kim Phillips79f516b2009-08-21 16:34:38 -0500607#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
Dave Liu24c3aca2006-12-07 21:13:15 +0800608
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200609#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
Dave Liu24c3aca2006-12-07 21:13:15 +0800610#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
611
612#define CONFIG_EXTRA_ENV_SETTINGS \
Joe Hershberger989091a2011-10-11 23:57:13 -0500613 "netdev=eth0\0" \
614 "consoledev=ttyS0\0" \
615 "ramdiskaddr=1000000\0" \
616 "ramdiskfile=ramfs.83xx\0" \
617 "fdtaddr=780000\0" \
618 "fdtfile=mpc832x_mds.dtb\0" \
619 ""
Dave Liu24c3aca2006-12-07 21:13:15 +0800620
621#define CONFIG_NFSBOOTCOMMAND \
Joe Hershberger989091a2011-10-11 23:57:13 -0500622 "setenv bootargs root=/dev/nfs rw " \
623 "nfsroot=$serverip:$rootpath " \
624 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
625 "$netdev:off " \
626 "console=$consoledev,$baudrate $othbootargs;" \
627 "tftp $loadaddr $bootfile;" \
628 "tftp $fdtaddr $fdtfile;" \
629 "bootm $loadaddr - $fdtaddr"
Dave Liu24c3aca2006-12-07 21:13:15 +0800630
631#define CONFIG_RAMBOOTCOMMAND \
Joe Hershberger989091a2011-10-11 23:57:13 -0500632 "setenv bootargs root=/dev/ram rw " \
633 "console=$consoledev,$baudrate $othbootargs;" \
634 "tftp $ramdiskaddr $ramdiskfile;" \
635 "tftp $loadaddr $bootfile;" \
636 "tftp $fdtaddr $fdtfile;" \
637 "bootm $loadaddr $ramdiskaddr $fdtaddr"
Dave Liu24c3aca2006-12-07 21:13:15 +0800638
639
640#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
641
642#endif /* __CONFIG_H */