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Prabhakar Kushwaha41d91012013-01-14 18:26:57 +00001/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +00005 */
6
7/*
8 * BSC9132 QDS board configuration file
9 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
harninder rai4aafbb42014-12-02 15:55:47 +053014#define CONFIG_DISPLAY_BOARDINFO
15
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +000016#ifdef CONFIG_BSC9132QDS
17#define CONFIG_BSC9132
18#endif
19
20#define CONFIG_MISC_INIT_R
21
22#ifdef CONFIG_SDCARD
23#define CONFIG_RAMBOOT_SDCARD
24#define CONFIG_SYS_RAMBOOT
25#define CONFIG_SYS_EXTRA_ENV_RELOC
26#define CONFIG_SYS_TEXT_BASE 0x11000000
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053027#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +000028#endif
29#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 1
30#ifdef CONFIG_SPIFLASH
31#define CONFIG_RAMBOOT_SPIFLASH
32#define CONFIG_SYS_RAMBOOT
33#define CONFIG_SYS_EXTRA_ENV_RELOC
34#define CONFIG_SYS_TEXT_BASE 0x11000000
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053035#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +000036#endif
Aneesh Bansalbea3cbb2014-03-12 22:00:18 +053037#ifdef CONFIG_NAND_SECBOOT
38#define CONFIG_RAMBOOT_NAND
39#define CONFIG_SYS_RAMBOOT
40#define CONFIG_SYS_EXTRA_ENV_RELOC
41#define CONFIG_SYS_TEXT_BASE 0x11000000
42#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
43#endif
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +000044
Prabhakar Kushwaha83e0c2b2013-04-16 13:28:40 +053045#ifdef CONFIG_NAND
Prabhakar Kushwaha83e0c2b2013-04-16 13:28:40 +053046#define CONFIG_SPL_INIT_MINIMAL
47#define CONFIG_SPL_SERIAL_SUPPORT
48#define CONFIG_SPL_NAND_SUPPORT
Prabhakar Kushwahafbe76ae2013-12-11 12:42:11 +053049#define CONFIG_SPL_NAND_BOOT
Prabhakar Kushwaha83e0c2b2013-04-16 13:28:40 +053050#define CONFIG_SPL_FLUSH_IMAGE
51#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
52
53#define CONFIG_SYS_TEXT_BASE 0x00201000
54#define CONFIG_SPL_TEXT_BASE 0xFFFFE000
55#define CONFIG_SPL_MAX_SIZE 8192
56#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
57#define CONFIG_SPL_RELOC_STACK 0x00100000
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053058#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
Prabhakar Kushwaha83e0c2b2013-04-16 13:28:40 +053059#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
60#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
61#define CONFIG_SYS_NAND_U_BOOT_OFFS 0
62#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
63#endif
64
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +000065#ifndef CONFIG_SYS_TEXT_BASE
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053066#define CONFIG_SYS_TEXT_BASE 0x8ff40000
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +000067#endif
68
69#ifndef CONFIG_RESET_VECTOR_ADDRESS
70#define CONFIG_RESET_VECTOR_ADDRESS 0x8ffffffc
71#endif
72
Prabhakar Kushwaha83e0c2b2013-04-16 13:28:40 +053073#ifdef CONFIG_SPL_BUILD
74#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
75#else
76#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +000077#endif
78
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +000079/* High Level Configuration Options */
80#define CONFIG_BOOKE /* BOOKE */
81#define CONFIG_E500 /* BOOKE e500 family */
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +000082#define CONFIG_FSL_IFC /* Enable IFC Support */
Ruchika Gupta737537e2014-10-15 11:35:31 +053083#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +000084#define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
85
86#define CONFIG_PCI /* Enable PCI/PCIE */
87#if defined(CONFIG_PCI)
88#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
89#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
Gabor Juhos842033e2013-05-30 07:06:12 +000090#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +000091#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
92#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
93
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +000094#define CONFIG_CMD_PCI
95
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +000096
97/*
98 * PCI Windows
99 * Memory space is mapped 1-1, but I/O space must start from 0.
100 */
101/* controller 1, Slot 1, tgtid 1, Base address a000 */
102#define CONFIG_SYS_PCIE1_NAME "PCIe Slot"
103#define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000
104#define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000
105#define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000
106#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
107#define CONFIG_SYS_PCIE1_IO_VIRT 0xC0010000
108#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
109#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
110#define CONFIG_SYS_PCIE1_IO_PHYS 0xC0010000
111
112#define CONFIG_PCI_PNP /* do pci plug-and-play */
113
114#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
115#define CONFIG_DOS_PARTITION
116#endif
117
118#define CONFIG_FSL_LAW /* Use common FSL init code */
119#define CONFIG_ENV_OVERWRITE
120#define CONFIG_TSEC_ENET /* ethernet */
121
122#if defined(CONFIG_SYS_CLK_100_DDR_100)
123#define CONFIG_SYS_CLK_FREQ 100000000
124#define CONFIG_DDR_CLK_FREQ 100000000
125#elif defined(CONFIG_SYS_CLK_100_DDR_133)
126#define CONFIG_SYS_CLK_FREQ 100000000
127#define CONFIG_DDR_CLK_FREQ 133000000
128#endif
129
130#define CONFIG_MP
131
132#define CONFIG_HWCONFIG
133/*
134 * These can be toggled for performance analysis, otherwise use default.
135 */
136#define CONFIG_L2_CACHE /* toggle L2 cache */
137#define CONFIG_BTB /* enable branch predition */
138
139#define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */
140#define CONFIG_SYS_MEMTEST_END 0x01ffffff
141
142/* DDR Setup */
York Sun5614e712013-09-30 09:22:09 -0700143#define CONFIG_SYS_FSL_DDR3
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000144#define CONFIG_SYS_SPD_BUS_NUM 0
145#define SPD_EEPROM_ADDRESS1 0x54 /* I2C access */
146#define SPD_EEPROM_ADDRESS2 0x56 /* I2C access */
147#define CONFIG_FSL_DDR_INTERACTIVE
148
149#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
150
151#define CONFIG_SYS_SDRAM_SIZE (1024)
152#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
153#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
154
155#define CONFIG_DIMM_SLOTS_PER_CTLR 1
156
157/* DDR3 Controller Settings */
158#define CONFIG_CHIP_SELECTS_PER_CTRL 1
159#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
160#define CONFIG_SYS_DDR_CS0_CONFIG_1333 0x80004302
161#define CONFIG_SYS_DDR_CS0_CONFIG_800 0x80014302
162#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
163#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
164#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
165#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
166#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
167#define CONFIG_SYS_DDR1_CS0_BNDS 0x0040007F
168
169#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
170#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
171#define CONFIG_SYS_DDR_RCW_1 0x00000000
172#define CONFIG_SYS_DDR_RCW_2 0x00000000
173#define CONFIG_SYS_DDR_CONTROL_800 0x470C0000
174#define CONFIG_SYS_DDR_CONTROL_2_800 0x04401050
175#define CONFIG_SYS_DDR_TIMING_4_800 0x00220001
176#define CONFIG_SYS_DDR_TIMING_5_800 0x03402400
177
178#define CONFIG_SYS_DDR_CONTROL_1333 0x470C0008
179#define CONFIG_SYS_DDR_CONTROL_2_1333 0x24401010
180#define CONFIG_SYS_DDR_TIMING_4_1333 0x00000001
181#define CONFIG_SYS_DDR_TIMING_5_1333 0x03401400
182
183#define CONFIG_SYS_DDR_TIMING_3_800 0x00020000
184#define CONFIG_SYS_DDR_TIMING_0_800 0x00330004
185#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6B4846
186#define CONFIG_SYS_DDR_TIMING_2_800 0x0FA8C8CF
187#define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
188#define CONFIG_SYS_DDR_MODE_1_800 0x40461520
189#define CONFIG_SYS_DDR_MODE_2_800 0x8000c000
190#define CONFIG_SYS_DDR_INTERVAL_800 0x0C300000
191#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8655A608
192
193#define CONFIG_SYS_DDR_TIMING_3_1333 0x01061000
194#define CONFIG_SYS_DDR_TIMING_0_1333 0x00440104
195#define CONFIG_SYS_DDR_TIMING_1_1333 0x98913A45
196#define CONFIG_SYS_DDR_TIMING_2_1333 0x0FB8B114
197#define CONFIG_SYS_DDR_CLK_CTRL_1333 0x02800000
198#define CONFIG_SYS_DDR_MODE_1_1333 0x00061A50
199#define CONFIG_SYS_DDR_MODE_2_1333 0x00100000
200#define CONFIG_SYS_DDR_INTERVAL_1333 0x144E0513
201#define CONFIG_SYS_DDR_WRLVL_CONTROL_1333 0x8655F607
202
203/*FIXME: the following params are constant w.r.t diff freq
204combinations. this should be removed later
205*/
206#if CONFIG_DDR_CLK_FREQ == 100000000
207#define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800
208#define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800
209#define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800
210#define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800
211#define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800
212#elif CONFIG_DDR_CLK_FREQ == 133000000
213#define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_1333
214#define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_1333
215#define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_1333
216#define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_1333
217#define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_1333
218#else
219#define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800
220#define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800
221#define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800
222#define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800
223#define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800
224#endif
225
226
227/* relocated CCSRBAR */
228#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
229#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT
230
231#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
232
Priyanka Jain64501c62013-07-02 09:21:04 +0530233/* DSP CCSRBAR */
234#define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
235#define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
236
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000237/*
238 * IFC Definitions
239 */
240/* NOR Flash on IFC */
Prabhakar Kushwaha83e0c2b2013-04-16 13:28:40 +0530241
242#ifdef CONFIG_SPL_BUILD
243#define CONFIG_SYS_NO_FLASH
244#endif
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000245#define CONFIG_SYS_FLASH_BASE 0x88000000
246#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* Max number of sector: 32M */
247
248#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
249
250#define CONFIG_SYS_NOR_CSPR 0x88000101
251#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
252#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(5)
253/* NOR Flash Timing Params */
254
255#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) \
256 | FTIM0_NOR_TEADC(0x03) \
257 | FTIM0_NOR_TAVDS(0x00) \
258 | FTIM0_NOR_TEAHC(0x0f))
259#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1d) \
260 | FTIM1_NOR_TRAD_NOR(0x09) \
261 | FTIM1_NOR_TSEQRAD_NOR(0x09))
262#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) \
263 | FTIM2_NOR_TCH(0x4) \
264 | FTIM2_NOR_TWPH(0x7) \
265 | FTIM2_NOR_TWP(0x1e))
266#define CONFIG_SYS_NOR_FTIM3 0x0
267
268#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
269#define CONFIG_SYS_FLASH_QUIET_TEST
270#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
271#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
272
273#undef CONFIG_SYS_FLASH_CHECKSUM
274#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
275#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
276
277/* CFI for NOR Flash */
278#define CONFIG_FLASH_CFI_DRIVER
279#define CONFIG_SYS_FLASH_CFI
280#define CONFIG_SYS_FLASH_EMPTY_INFO
281#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
282
283/* NAND Flash on IFC */
284#define CONFIG_SYS_NAND_BASE 0xff800000
285#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
286
287#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
288 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
289 | CSPR_MSEL_NAND /* MSEL = NAND */ \
290 | CSPR_V)
291#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
292
293#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
294 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
295 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
296 | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \
297 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
298 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
299 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
300
301/* NAND Flash Timing Params */
302#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \
303 | FTIM0_NAND_TWP(0x05) \
304 | FTIM0_NAND_TWCHT(0x02) \
305 | FTIM0_NAND_TWH(0x04))
306#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1c) \
307 | FTIM1_NAND_TWBE(0x1e) \
308 | FTIM1_NAND_TRR(0x07) \
309 | FTIM1_NAND_TRP(0x05))
310#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \
311 | FTIM2_NAND_TREH(0x04) \
312 | FTIM2_NAND_TWHRE(0x11))
313#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
314
315#define CONFIG_SYS_NAND_DDR_LAW 11
316
317/* NAND */
318#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
319#define CONFIG_SYS_MAX_NAND_DEVICE 1
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000320#define CONFIG_CMD_NAND
321
322#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
323
Prabhakar Kushwaha83e0c2b2013-04-16 13:28:40 +0530324#ifndef CONFIG_SPL_BUILD
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000325#define CONFIG_FSL_QIXIS
Prabhakar Kushwaha83e0c2b2013-04-16 13:28:40 +0530326#endif
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000327#ifdef CONFIG_FSL_QIXIS
328#define CONFIG_SYS_FPGA_BASE 0xffb00000
329#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
330#define QIXIS_BASE CONFIG_SYS_FPGA_BASE
331#define QIXIS_LBMAP_SWITCH 9
332#define QIXIS_LBMAP_MASK 0x07
333#define QIXIS_LBMAP_SHIFT 0
334#define QIXIS_LBMAP_DFLTBANK 0x00
335#define QIXIS_LBMAP_ALTBANK 0x04
336#define QIXIS_RST_CTL_RESET 0x83
337#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
338#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
339#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
340
341#define CONFIG_SYS_FPGA_BASE_PHYS CONFIG_SYS_FPGA_BASE
342
343#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_FPGA_BASE) \
344 | CSPR_PORT_SIZE_8 \
345 | CSPR_MSEL_GPCM \
346 | CSPR_V)
347#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
348#define CONFIG_SYS_CSOR2 0x0
349/* CPLD Timing parameters for IFC CS3 */
350#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
351 FTIM0_GPCM_TEADC(0x0e) | \
352 FTIM0_GPCM_TEAHC(0x0e))
353#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
354 FTIM1_GPCM_TRAD(0x1f))
355#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
Shaohui Xiede519162014-06-26 14:41:33 +0800356 FTIM2_GPCM_TCH(0x8) | \
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000357 FTIM2_GPCM_TWP(0x1f))
358#define CONFIG_SYS_CS2_FTIM3 0x0
359#endif
360
361/* Set up IFC registers for boot location NOR/NAND */
Aneesh Bansal3051f3f2014-05-14 11:45:15 +0530362#if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
Prabhakar Kushwaha83e0c2b2013-04-16 13:28:40 +0530363#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
364#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
365#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
366#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
367#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
368#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
369#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
370#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
371#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
372#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
373#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
374#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
375#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
376#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
377#else
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000378#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
379#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
380#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
381#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
382#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
383#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
384#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
385#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
386#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
387#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
388#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
389#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
390#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
391#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
Prabhakar Kushwaha83e0c2b2013-04-16 13:28:40 +0530392#endif
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000393
394#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
395#define CONFIG_BOARD_EARLY_INIT_R
396
397#define CONFIG_SYS_INIT_RAM_LOCK
398#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
399#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
400
401#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \
402 - GENERATED_GBL_DATA_SIZE)
403#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
404
Prabhakar Kushwaha9307cba2014-03-31 15:31:48 +0530405#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000406#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
407
408/* Serial Port */
409#define CONFIG_CONS_INDEX 1
410#undef CONFIG_SERIAL_SOFTWARE_FIFO
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000411#define CONFIG_SYS_NS16550_SERIAL
412#define CONFIG_SYS_NS16550_REG_SIZE 1
413#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Prabhakar Kushwaha83e0c2b2013-04-16 13:28:40 +0530414#ifdef CONFIG_SPL_BUILD
415#define CONFIG_NS16550_MIN_FUNCTIONS
416#endif
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000417
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000418#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
419
420#define CONFIG_SYS_BAUDRATE_TABLE \
421 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
422
423#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
424#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
425#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x4700)
426#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x4800)
427
428/* Use the HUSH parser */
429#define CONFIG_SYS_HUSH_PARSER /* hush parser */
430#ifdef CONFIG_SYS_HUSH_PARSER
431#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
432#endif
433
434/*
435 * Pass open firmware flat tree
436 */
437#define CONFIG_OF_LIBFDT
438#define CONFIG_OF_BOARD_SETUP
439#define CONFIG_OF_STDOUT_VIA_ALIAS
440
441/* new uImage format support */
442#define CONFIG_FIT
443#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
444
Heiko Schocher00f792e2012-10-24 13:48:22 +0200445#define CONFIG_SYS_I2C
446#define CONFIG_SYS_I2C_FSL
447#define CONFIG_SYS_FSL_I2C_SPEED 400800 /* I2C speed and slave address*/
448#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
449#define CONFIG_SYS_FSL_I2C2_SPEED 400800 /* I2C speed and slave address*/
450#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
451#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
452#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000453
454/* I2C EEPROM */
455#define CONFIG_ID_EEPROM
456#ifdef CONFIG_ID_EEPROM
457#define CONFIG_SYS_I2C_EEPROM_NXID
458#endif
459#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
460#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
461#define CONFIG_SYS_EEPROM_BUS_NUM 0
462
463/* enable read and write access to EEPROM */
464#define CONFIG_CMD_EEPROM
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000465#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
466#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
467#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
468
469/* I2C FPGA */
470#define CONFIG_I2C_FPGA
471#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
472
473#define CONFIG_RTC_DS3231
474#define CONFIG_SYS_I2C_RTC_ADDR 0x68
475
476/*
477 * SPI interface will not be available in case of NAND boot SPI CS0 will be
478 * used for SLIC
479 */
480/* eSPI - Enhanced SPI */
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000481#ifdef CONFIG_FSL_ESPI
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000482#define CONFIG_CMD_SF
483#define CONFIG_SF_DEFAULT_SPEED 10000000
484#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
485#endif
486
487#if defined(CONFIG_TSEC_ENET)
488
489#define CONFIG_MII /* MII PHY management */
490#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
491#define CONFIG_TSEC1 1
492#define CONFIG_TSEC1_NAME "eTSEC1"
493#define CONFIG_TSEC2 1
494#define CONFIG_TSEC2_NAME "eTSEC2"
495
496#define TSEC1_PHY_ADDR 0
497#define TSEC2_PHY_ADDR 1
498
499#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
500#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
501
502#define TSEC1_PHYIDX 0
503#define TSEC2_PHYIDX 0
504
505#define CONFIG_ETHPRIME "eTSEC1"
506
507#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
508
509/* TBI PHY configuration for SGMII mode */
510#define CONFIG_TSEC_TBICR_SETTINGS ( \
511 TBICR_PHY_RESET \
512 | TBICR_ANEG_ENABLE \
513 | TBICR_FULL_DUPLEX \
514 | TBICR_SPEED1_SET \
515 )
516
517#endif /* CONFIG_TSEC_ENET */
518
519#define CONFIG_MMC
520#ifdef CONFIG_MMC
521#define CONFIG_CMD_MMC
522#define CONFIG_DOS_PARTITION
523#define CONFIG_FSL_ESDHC
524#define CONFIG_GENERIC_MMC
525#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
526#endif
527
528#define CONFIG_USB_EHCI /* USB */
529#ifdef CONFIG_USB_EHCI
530#define CONFIG_CMD_USB
531#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
532#define CONFIG_USB_EHCI_FSL
533#define CONFIG_USB_STORAGE
534#define CONFIG_HAS_FSL_DR_USB
535#endif
536
537/*
538 * Environment
539 */
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000540#if defined(CONFIG_RAMBOOT_SDCARD)
541#define CONFIG_ENV_IS_IN_MMC
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +0530542#define CONFIG_FSL_FIXED_MMC_LOCATION
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000543#define CONFIG_SYS_MMC_ENV_DEV 0
544#define CONFIG_ENV_SIZE 0x2000
545#elif defined(CONFIG_RAMBOOT_SPIFLASH)
546#define CONFIG_ENV_IS_IN_SPI_FLASH
547#define CONFIG_ENV_SPI_BUS 0
548#define CONFIG_ENV_SPI_CS 0
549#define CONFIG_ENV_SPI_MAX_HZ 10000000
550#define CONFIG_ENV_SPI_MODE 0
551#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
552#define CONFIG_ENV_SECT_SIZE 0x10000
553#define CONFIG_ENV_SIZE 0x2000
Aneesh Bansalbea3cbb2014-03-12 22:00:18 +0530554#elif defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
Prabhakar Kushwaha83e0c2b2013-04-16 13:28:40 +0530555#define CONFIG_ENV_IS_IN_NAND
556#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +0530557#define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
Prabhakar Kushwaha83e0c2b2013-04-16 13:28:40 +0530558#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
559#elif defined(CONFIG_SYS_RAMBOOT)
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000560#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
561#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
562#define CONFIG_ENV_SIZE 0x2000
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000563#else
564#define CONFIG_ENV_IS_IN_FLASH
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000565#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000566#define CONFIG_ENV_SIZE 0x2000
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +0530567#define CONFIG_ENV_SECT_SIZE 0x20000
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000568#endif
569
570#define CONFIG_LOADS_ECHO /* echo on for serial download */
571#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
572
573/*
574 * Command line configuration.
575 */
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000576#define CONFIG_CMD_DATE
577#define CONFIG_CMD_DHCP
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000578#define CONFIG_CMD_ERRATA
579#define CONFIG_CMD_I2C
580#define CONFIG_CMD_IRQ
581#define CONFIG_CMD_MII
582#define CONFIG_CMD_PING
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000583#define CONFIG_CMD_REGINFO
584
585#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
586#define CONFIG_CMD_EXT2
587#define CONFIG_CMD_FAT
588#define CONFIG_DOS_PARTITION
589#endif
590
Ruchika Gupta737537e2014-10-15 11:35:31 +0530591/* Hash command with SHA acceleration supported in hardware */
592#ifdef CONFIG_FSL_CAAM
593#define CONFIG_CMD_HASH
594#define CONFIG_SHA_HW_ACCEL
595#endif
596
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000597/*
598 * Miscellaneous configurable options
599 */
600#define CONFIG_SYS_LONGHELP /* undef to save memory */
601#define CONFIG_CMDLINE_EDITING /* Command-line editing */
602#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
603#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000604
605#if defined(CONFIG_CMD_KGDB)
606#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
607#else
608#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
609#endif
610#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
611 /* Print Buffer Size */
612#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
613#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000614
615
616/*
617 * For booting Linux, the board info and command line data
618 * have to be in the first 64 MB of memory, since this is
619 * the maximum mapped by the Linux kernel during initialization.
620 */
621#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
622#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
623
624#if defined(CONFIG_CMD_KGDB)
625#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000626#endif
627
628/*
Ashish Kumar42a9e2f2014-10-06 18:24:56 +0530629 * Dynamic MTD Partition support with mtdparts
630 */
631#ifndef CONFIG_SYS_NO_FLASH
632#define CONFIG_MTD_DEVICE
633#define CONFIG_MTD_PARTITIONS
634#define CONFIG_CMD_MTDPARTS
635#define CONFIG_FLASH_CFI_MTD
636#define MTDIDS_DEFAULT "nor0=88000000.nor,nand0=ff800000.flash,"
637#define MTDPARTS_DEFAULT "mtdparts=88000000.nor:256k(dtb),7m(kernel)," \
638 "55m(fs),1m(uboot);ff800000.flash:1m(uboot)," \
639 "8m(kernel),512k(dtb),-(fs)"
640#endif
641/*
642 * Override partitions in device tree using info
643 * in "mtdparts" environment variable
644 */
645#ifdef CONFIG_CMD_MTDPARTS
646#define CONFIG_FDT_FIXUP_PARTITIONS
647#endif
648
649/*
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000650 * Environment Configuration
651 */
652
653#if defined(CONFIG_TSEC_ENET)
654#define CONFIG_HAS_ETH0
655#define CONFIG_HAS_ETH1
656#endif
657
658#define CONFIG_HOSTNAME BSC9132qds
659#define CONFIG_ROOTPATH "/opt/nfsroot"
660#define CONFIG_BOOTFILE "uImage"
661#define CONFIG_UBOOTPATH "u-boot.bin"
662
663#define CONFIG_BAUDRATE 115200
harninder rai37811ec2014-12-15 12:58:45 +0530664#define CONFIG_BOOTDELAY 10 /* -1 disable auto-boot */
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000665
666#ifdef CONFIG_SDCARD
667#define CONFIG_DEF_HWCONFIG "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
668#else
669#define CONFIG_DEF_HWCONFIG "hwconfig=sim;usb1:dr_mode=host,phy_type=ulpi\0"
670#endif
671
672#define CONFIG_EXTRA_ENV_SETTINGS \
673 "netdev=eth0\0" \
674 "uboot=" CONFIG_UBOOTPATH "\0" \
675 "loadaddr=1000000\0" \
676 "bootfile=uImage\0" \
677 "consoledev=ttyS0\0" \
678 "ramdiskaddr=2000000\0" \
679 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
680 "fdtaddr=c00000\0" \
681 "fdtfile=bsc9132qds.dtb\0" \
682 "bdev=sda1\0" \
683 CONFIG_DEF_HWCONFIG\
684 "othbootargs=mem=880M ramdisk_size=600000 " \
685 "default_hugepagesz=256m hugepagesz=256m hugepages=1 " \
686 "isolcpus=0\0" \
687 "usbext2boot=setenv bootargs root=/dev/ram rw " \
688 "console=$consoledev,$baudrate $othbootargs; " \
689 "usb start;" \
690 "ext2load usb 0:4 $loadaddr $bootfile;" \
691 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
692 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
693 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
694 "debug_halt_off=mw ff7e0e30 0xf0000000;"
695
696#define CONFIG_NFSBOOTCOMMAND \
697 "setenv bootargs root=/dev/nfs rw " \
698 "nfsroot=$serverip:$rootpath " \
699 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
700 "console=$consoledev,$baudrate $othbootargs;" \
701 "tftp $loadaddr $bootfile;" \
702 "tftp $fdtaddr $fdtfile;" \
703 "bootm $loadaddr - $fdtaddr"
704
705#define CONFIG_HDBOOT \
706 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
707 "console=$consoledev,$baudrate $othbootargs;" \
708 "usb start;" \
709 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
710 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
711 "bootm $loadaddr - $fdtaddr"
712
713#define CONFIG_RAMBOOTCOMMAND \
714 "setenv bootargs root=/dev/ram rw " \
715 "console=$consoledev,$baudrate $othbootargs; " \
716 "tftp $ramdiskaddr $ramdiskfile;" \
717 "tftp $loadaddr $bootfile;" \
718 "tftp $fdtaddr $fdtfile;" \
719 "bootm $loadaddr $ramdiskaddr $fdtaddr"
720
721#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
722
Aneesh Bansalf978f7c2014-03-12 00:07:27 +0530723#include <asm/fsl_secure_boot.h>
724
Ruchika Gupta789490b2014-10-07 15:48:46 +0530725#ifdef CONFIG_SECURE_BOOT
726#define CONFIG_CMD_BLOB
727#endif
728
Prabhakar Kushwaha41d91012013-01-14 18:26:57 +0000729#endif /* __CONFIG_H */