blob: bc014169a4d5c25d56431ef86c33277cd4f15ff9 [file] [log] [blame]
Dirk Eibachd7b26d52008-10-08 15:37:50 +02001/*
2 * (C) Copyright 2007-2008
3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
4 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
Dirk Eibachd7b26d52008-10-08 15:37:50 +02006 */
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
11
12#define CONFIG_405EP 1 /* this is a PPC405 CPU */
Dirk Eibachd7b26d52008-10-08 15:37:50 +020013#define CONFIG_NEO 1 /* on a Neo board */
14
Wolfgang Denk2ae18242010-10-06 09:05:45 +020015#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
16
Dirk Eibachd7b26d52008-10-08 15:37:50 +020017/*
18 * Include common defines/options for all AMCC eval boards
19 */
20#define CONFIG_HOSTNAME neo
Dirk Eibach28437152013-06-26 16:04:31 +020021#define CONFIG_IDENT_STRING " neo 0.02"
Dirk Eibachd7b26d52008-10-08 15:37:50 +020022#include "amcc-common.h"
23
Dirk Eibach6e9e6c32012-04-26 03:54:22 +000024#define CONFIG_BOARD_EARLY_INIT_F
25#define CONFIG_BOARD_EARLY_INIT_R
26#define CONFIG_MISC_INIT_R
27#define CONFIG_LAST_STAGE_INIT
Dirk Eibachd7b26d52008-10-08 15:37:50 +020028
29#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
30
31/*
32 * Configure PLL
33 */
34#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
35#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
36
37/* new uImage format support */
38#define CONFIG_FIT
39#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
Dirk Eibach9a4f4792014-07-03 09:28:26 +020040#define CONFIG_FIT_DISABLE_SHA256
Dirk Eibachd7b26d52008-10-08 15:37:50 +020041
42#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
43
44/*
45 * Default environment variables
46 */
47#define CONFIG_EXTRA_ENV_SETTINGS \
48 CONFIG_AMCC_DEF_ENV \
49 CONFIG_AMCC_DEF_ENV_POWERPC \
50 CONFIG_AMCC_DEF_ENV_NOR_UPD \
51 "kernel_addr=fc000000\0" \
52 "fdt_addr=fc1e0000\0" \
53 "ramdisk_addr=fc200000\0" \
54 ""
55
56#define CONFIG_PHY_ADDR 4 /* PHY address */
57#define CONFIG_HAS_ETH0
58#define CONFIG_HAS_ETH1
59#define CONFIG_PHY1_ADDR 0xc /* EMAC1 PHY address */
60#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
61
62/*
63 * Commands additional to the ones defined in amcc-common.h
64 */
Dirk Eibachd7b26d52008-10-08 15:37:50 +020065#define CONFIG_CMD_DTT
Dirk Eibach4fb9b412014-07-03 09:28:25 +020066#undef CONFIG_CMD_DHCP
67#undef CONFIG_CMD_DIAG
Dirk Eibachd7b26d52008-10-08 15:37:50 +020068#undef CONFIG_CMD_EEPROM
Dirk Eibach4fb9b412014-07-03 09:28:25 +020069#undef CONFIG_CMD_I2C
70#undef CONFIG_CMD_IRQ
Dirk Eibachd7b26d52008-10-08 15:37:50 +020071
72/*
73 * SDRAM configuration (please see cpu/ppc/sdram.[ch])
74 */
75#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
76
77/* SDRAM timings used in datasheet */
78#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
79#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
80#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */
81#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
82#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
83
84/*
85 * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
86 * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
87 * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
88 * The Linux BASE_BAUD define should match this configuration.
89 * baseBaud = cpuClock/(uartDivisor*16)
90 * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
91 * set Linux BASE_BAUD to 403200.
92 */
Stefan Roese550650d2010-09-20 16:05:31 +020093#define CONFIG_CONS_INDEX 1 /* Use UART0 */
Stefan Roese550650d2010-09-20 16:05:31 +020094#define CONFIG_SYS_NS16550_SERIAL
95#define CONFIG_SYS_NS16550_REG_SIZE 1
96#define CONFIG_SYS_NS16550_CLK get_serial_clock()
97
Dirk Eibachd7b26d52008-10-08 15:37:50 +020098#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
99#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
100#define CONFIG_SYS_BASE_BAUD 691200
101
102/*
103 * I2C stuff
104 */
Dirk Eibach880540d2013-04-25 02:40:01 +0000105#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
Dirk Eibachd7b26d52008-10-08 15:37:50 +0200106
107/* RTC */
108#define CONFIG_RTC_DS1337
109#define CONFIG_SYS_I2C_RTC_ADDR 0x68
110
111/* Temp sensor/hwmon/dtt */
112#define CONFIG_DTT_LM63 1 /* National LM63 */
113#define CONFIG_DTT_SENSORS { 0 } /* Sensor addresses */
114#define CONFIG_DTT_PWM_LOOKUPTABLE \
115 { { 40, 10 }, { 50, 20 }, { 60, 40 } }
116#define CONFIG_DTT_TACH_LIMIT 0xa10
117
118/*
119 * FLASH organization
120 */
121#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
122#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
123
124#define CONFIG_SYS_FLASH_BASE 0xFC000000
125#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
126
127#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
128#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
129
130#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
131#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
132
133#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
Dirk Eibachd7b26d52008-10-08 15:37:50 +0200134
135#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
136#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
137
138#ifdef CONFIG_ENV_IS_IN_FLASH
139#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
Dirk Eibach6e9e6c32012-04-26 03:54:22 +0000140#define CONFIG_ENV_ADDR 0xFFF00000
Dirk Eibach00251262012-04-26 03:54:21 +0000141#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
Dirk Eibachd7b26d52008-10-08 15:37:50 +0200142
143/* Address and size of Redundant Environment Sector */
Dirk Eibach6e9e6c32012-04-26 03:54:22 +0000144#define CONFIG_ENV_ADDR_REDUND 0xFFF20000
Dirk Eibachd7b26d52008-10-08 15:37:50 +0200145#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
146#endif
147
148/*
149 * PPC405 GPIO Configuration
150 */
Dirk Eibach6e9e6c32012-04-26 03:54:22 +0000151#define CONFIG_SYS_4xx_GPIO_TABLE { \
152{ \
153/* GPIO Core 0 */ \
154{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
155{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
156{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
157{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
158{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
159{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \
160{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
161{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO7 TS5 */ \
162{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
163{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
164{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
165{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
166{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
167{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
168{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
169{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
170{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
171{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
172{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
173{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
174{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
175{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
176{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
177{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
178{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
179{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
180{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
181{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
182{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
183{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
184{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
185{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
186} \
Dirk Eibachd7b26d52008-10-08 15:37:50 +0200187}
188
189/*
190 * Definitions for initial stack pointer and data area (in data cache)
191 */
192/* use on chip memory (OCM) for temperary stack until sdram is tested */
193#define CONFIG_SYS_TEMP_STACK_OCM 1
194
195/* On Chip Memory location */
196#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
197#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
198#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200199#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
Dirk Eibachd7b26d52008-10-08 15:37:50 +0200200
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200201#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Dirk Eibachd7b26d52008-10-08 15:37:50 +0200202#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
203
204/*
205 * External Bus Controller (EBC) Setup
206 */
207
208/* Memory Bank 0 (NOR-FLASH) initialization */
209#define CONFIG_SYS_EBC_PB0AP 0x92015480
210#define CONFIG_SYS_EBC_PB0CR 0xFC0DA000 /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit */
211
212/* Memory Bank 1 (NVRAM) initialization */
213#define CONFIG_SYS_EBC_PB1AP 0x92015480
214#define CONFIG_SYS_EBC_PB1CR 0xFB85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */
215
216/* Memory Bank 2 (FPGA) initialization */
Dirk Eibach6e9e6c32012-04-26 03:54:22 +0000217#define CONFIG_SYS_FPGA0_BASE 0x7f100000
Dirk Eibachd7b26d52008-10-08 15:37:50 +0200218#define CONFIG_SYS_EBC_PB2AP 0x92015480
219#define CONFIG_SYS_EBC_PB2CR 0x7f11a000 /* BAS=0x7f1,BS=1MB,BU=R/W,BW=16bit */
220
Dirk Eibach6e9e6c32012-04-26 03:54:22 +0000221#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
222
223#define CONFIG_SYS_FPGA_COUNT 1
224
Dirk Eibachaba27ac2013-06-26 16:04:26 +0200225#define CONFIG_SYS_FPGA_PTR \
226 { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE }
227
228#define CONFIG_SYS_FPGA_COMMON
229
Dirk Eibachd7b26d52008-10-08 15:37:50 +0200230/* Memory Bank 3 (Latches) initialization */
Dirk Eibach6e9e6c32012-04-26 03:54:22 +0000231#define CONFIG_SYS_LATCH_BASE 0x7f200000
Dirk Eibachd7b26d52008-10-08 15:37:50 +0200232#define CONFIG_SYS_EBC_PB3AP 0x92015480
233#define CONFIG_SYS_EBC_PB3CR 0x7f21a000 /* BAS=0x7f2,BS=1MB,BU=R/W,BW=16bit */
234
Dirk Eibach6e9e6c32012-04-26 03:54:22 +0000235#define CONFIG_SYS_LATCH0_RESET 0xffff
236#define CONFIG_SYS_LATCH0_BOOT 0xffff
237#define CONFIG_SYS_LATCH1_RESET 0xffbf
238#define CONFIG_SYS_LATCH1_BOOT 0xffff
239
Dirk Eibachd7b26d52008-10-08 15:37:50 +0200240#endif /* __CONFIG_H */