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Sascha Hauercdace062008-03-26 20:40:49 +01001/*
2 * i2c driver for Freescale mx31
3 *
4 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <common.h>
26
Michal Simeka4a549b2008-07-14 19:45:35 +020027#if defined(CONFIG_HARD_I2C)
Sascha Hauercdace062008-03-26 20:40:49 +010028
29#include <asm/arch/mx31.h>
30#include <asm/arch/mx31-regs.h>
31
32#define IADR 0x00
33#define IFDR 0x04
34#define I2CR 0x08
35#define I2SR 0x0c
36#define I2DR 0x10
37
38#define I2CR_IEN (1 << 7)
39#define I2CR_IIEN (1 << 6)
40#define I2CR_MSTA (1 << 5)
41#define I2CR_MTX (1 << 4)
42#define I2CR_TX_NO_AK (1 << 3)
43#define I2CR_RSTA (1 << 2)
44
45#define I2SR_ICF (1 << 7)
46#define I2SR_IBB (1 << 5)
47#define I2SR_IIF (1 << 1)
48#define I2SR_RX_NO_AK (1 << 0)
49
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020050#ifdef CONFIG_SYS_I2C_MX31_PORT1
Sascha Hauercdace062008-03-26 20:40:49 +010051#define I2C_BASE 0x43f80000
Guennadi Liakhovetskie7de18a2009-02-13 09:23:36 +010052#define I2C_CLK_OFFSET 26
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020053#elif defined (CONFIG_SYS_I2C_MX31_PORT2)
Sascha Hauercdace062008-03-26 20:40:49 +010054#define I2C_BASE 0x43f98000
Guennadi Liakhovetskie7de18a2009-02-13 09:23:36 +010055#define I2C_CLK_OFFSET 28
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020056#elif defined (CONFIG_SYS_I2C_MX31_PORT3)
Sascha Hauercdace062008-03-26 20:40:49 +010057#define I2C_BASE 0x43f84000
Guennadi Liakhovetskie7de18a2009-02-13 09:23:36 +010058#define I2C_CLK_OFFSET 30
Sascha Hauercdace062008-03-26 20:40:49 +010059#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020060#error "define CONFIG_SYS_I2C_MX31_PORTx to use the mx31 I2C driver"
Sascha Hauercdace062008-03-26 20:40:49 +010061#endif
62
63#ifdef DEBUG
64#define DPRINTF(args...) printf(args)
65#else
66#define DPRINTF(args...)
67#endif
68
69static u16 div[] = { 30, 32, 36, 42, 48, 52, 60, 72, 80, 88, 104, 128, 144,
70 160, 192, 240, 288, 320, 384, 480, 576, 640, 768, 960,
71 1152, 1280, 1536, 1920, 2304, 2560, 3072, 3840};
72
73void i2c_init(int speed, int unused)
74{
75 int freq = mx31_get_ipg_clk();
76 int i;
77
Guennadi Liakhovetskie7de18a2009-02-13 09:23:36 +010078 /* start the required I2C clock */
79 __REG(CCM_CGR0) = __REG(CCM_CGR0) | (3 << I2C_CLK_OFFSET);
80
Sascha Hauercdace062008-03-26 20:40:49 +010081 for (i = 0; i < 0x1f; i++)
82 if (freq / div[i] <= speed)
83 break;
84
85 DPRINTF("%s: speed: %d\n",__FUNCTION__, speed);
86
87 __REG16(I2C_BASE + I2CR) = 0; /* Reset module */
88 __REG16(I2C_BASE + IFDR) = i;
89 __REG16(I2C_BASE + I2CR) = I2CR_IEN;
90 __REG16(I2C_BASE + I2SR) = 0;
91}
92
93static int wait_busy(void)
94{
95 int timeout = 10000;
96
97 while (!(__REG16(I2C_BASE + I2SR) & I2SR_IIF) && --timeout)
98 udelay(1);
99 __REG16(I2C_BASE + I2SR) = 0; /* clear interrupt */
100
101 return timeout;
102}
103
104static int tx_byte(u8 byte)
105{
106 __REG16(I2C_BASE + I2DR) = byte;
107
108 if (!wait_busy() || __REG16(I2C_BASE + I2SR) & I2SR_RX_NO_AK)
109 return -1;
110 return 0;
111}
112
113static int rx_byte(void)
114{
115 if (!wait_busy())
116 return -1;
117
118 return __REG16(I2C_BASE + I2DR);
119}
120
121int i2c_probe(uchar chip)
122{
123 int ret;
124
125 __REG16(I2C_BASE + I2CR) = 0; /* Reset module */
126 __REG16(I2C_BASE + I2CR) = I2CR_IEN;
127
128 __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | I2CR_MTX;
129 ret = tx_byte(chip << 1);
130 __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MTX;
131
132 return ret;
133}
134
135static int i2c_addr(uchar chip, uint addr, int alen)
136{
137 __REG16(I2C_BASE + I2SR) = 0; /* clear interrupt */
138 __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | I2CR_MTX;
139
140 if (tx_byte(chip << 1))
141 return -1;
142
143 while (alen--)
144 if (tx_byte((addr >> (alen * 8)) & 0xff))
145 return -1;
146 return 0;
147}
148
149int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
150{
151 int timeout = 10000;
152 int ret;
153
154 DPRINTF("%s chip: 0x%02x addr: 0x%04x alen: %d len: %d\n",__FUNCTION__, chip, addr, alen, len);
155
156 if (i2c_addr(chip, addr, alen)) {
157 printf("i2c_addr failed\n");
158 return -1;
159 }
160
161 __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | I2CR_MTX | I2CR_RSTA;
162
163 if (tx_byte(chip << 1 | 1))
164 return -1;
165
166 __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | ((len == 1) ? I2CR_TX_NO_AK : 0);
167
168 ret = __REG16(I2C_BASE + I2DR);
169
170 while (len--) {
171 if ((ret = rx_byte()) < 0)
172 return -1;
173 *buf++ = ret;
174 if (len <= 1)
175 __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | I2CR_TX_NO_AK;
176 }
177
178 wait_busy();
179
180 __REG16(I2C_BASE + I2CR) = I2CR_IEN;
181
182 while (__REG16(I2C_BASE + I2SR) & I2SR_IBB && --timeout)
183 udelay(1);
184
185 return 0;
186}
187
188int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
189{
190 int timeout = 10000;
191 DPRINTF("%s chip: 0x%02x addr: 0x%04x alen: %d len: %d\n",__FUNCTION__, chip, addr, alen, len);
192
193 if (i2c_addr(chip, addr, alen))
194 return -1;
195
196 while (len--)
197 if (tx_byte(*buf++))
198 return -1;
199
200 __REG16(I2C_BASE + I2CR) = I2CR_IEN;
201
202 while (__REG16(I2C_BASE + I2SR) & I2SR_IBB && --timeout)
203 udelay(1);
204
205 return 0;
206}
207
208#endif /* CONFIG_HARD_I2C */