blob: d16262b6cffe8c0c422c5706ba420546edd27227 [file] [log] [blame]
Wolfgang Denk6bdf4302005-08-15 15:55:00 +02001/*
2 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * Dan Malek, Embedded Edge, LLC, dan@embeddededge.com
26 * U-Boot port on STx XTc 8xx board
27 * Mostly copied from Panto's NETTA2 board.
28 */
29
30#ifndef __CONFIG_H
31#define __CONFIG_H
32
33/*
34 * High Level Configuration Options
35 * (easy to change)
36 */
37
38#define CONFIG_MPC875 1 /* This is a MPC875 CPU */
39#define CONFIG_STXXTC 1 /* ...on a STx XTc board */
40
41#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
42#undef CONFIG_8xx_CONS_SMC2
43#undef CONFIG_8xx_CONS_NONE
44
Wolfgang Denk670d9f12005-09-13 00:12:33 +020045#define CONFIG_BAUDRATE 115200 /* console baudrate = 115.2kbps */
Wolfgang Denk6bdf4302005-08-15 15:55:00 +020046
47#define CONFIG_XIN 10000000 /* 10 MHz input xtal */
48
49/* Select one of few clock rates defined later in this file.
50*/
51/* #define MPC8XX_HZ 50000000 */
52#define MPC8XX_HZ 66666666
53
54#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ
55
56#if 0
57#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
58#else
59#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
60#endif
61
62#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */
63
64#undef CONFIG_BOOTARGS
65#define CONFIG_BOOTCOMMAND \
Wolfgang Denk53677ef2008-05-20 16:00:29 +020066 "tftpboot; " \
67 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
68 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
Wolfgang Denk6bdf4302005-08-15 15:55:00 +020069 "bootm"
70
Wolfgang Denk74de7ae2009-04-01 23:34:12 +020071#define CONFIG_SOURCE
Wolfgang Denk6bdf4302005-08-15 15:55:00 +020072#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020073#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
Wolfgang Denk6bdf4302005-08-15 15:55:00 +020074
75#undef CONFIG_WATCHDOG /* watchdog disabled */
76
77#define CONFIG_STATUS_LED 1 /* Status LED enabled */
78#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */
79
Jon Loeligerd3b8c1a2007-07-09 21:57:31 -050080/*
81 * BOOTP options
82 */
83#define CONFIG_BOOTP_SUBNETMASK
84#define CONFIG_BOOTP_GATEWAY
85#define CONFIG_BOOTP_HOSTNAME
86#define CONFIG_BOOTP_BOOTPATH
87#define CONFIG_BOOTP_BOOTFILESIZE
88#define CONFIG_BOOTP_NISDOMAIN
89
Wolfgang Denk6bdf4302005-08-15 15:55:00 +020090
91#undef CONFIG_MAC_PARTITION
92#undef CONFIG_DOS_PARTITION
93
94#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
95
Wolfgang Denk53677ef2008-05-20 16:00:29 +020096#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */
Wolfgang Denk6bdf4302005-08-15 15:55:00 +020097#define FEC_ENET 1 /* eth.c needs it that way... */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#undef CONFIG_SYS_DISCOVER_PHY
Wolfgang Denk6bdf4302005-08-15 15:55:00 +020099#define CONFIG_MII 1
TsiChung Liew0f3ba7e2008-03-30 01:22:13 -0500100#define CONFIG_MII_INIT 1
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200101#undef CONFIG_RMII
102
103#define CONFIG_ETHER_ON_FEC1 1
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200104#define CONFIG_FEC1_PHY 1 /* phy address of FEC */
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200105#undef CONFIG_FEC1_PHY_NORXERR
106
107#define CONFIG_ETHER_ON_FEC2 1
108#define CONFIG_FEC2_PHY 3
109#undef CONFIG_FEC2_PHY_NORXERR
110
111#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */
112
Jon Loeligeref0df522007-07-04 22:31:07 -0500113
114/*
115 * Command line configuration.
116 */
117#include <config_cmd_default.h>
118
119#define CONFIG_CMD_DHCP
120#define CONFIG_CMD_MII
Jon Loeligeref0df522007-07-04 22:31:07 -0500121#define CONFIG_CMD_NFS
122#define CONFIG_CMD_PING
123
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200124
125#define CONFIG_BOARD_EARLY_INIT_F 1
126#define CONFIG_MISC_INIT_R
127
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200128/*
129 * Miscellaneous configurable options
130 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_LONGHELP /* undef to save memory */
132#define CONFIG_SYS_PROMPT "xtc> " /* Monitor Command Prompt */
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200133
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_HUSH_PARSER 1
135#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200136
Jon Loeligeref0df522007-07-04 22:31:07 -0500137#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200139#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200141#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
143#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
144#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200145
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_MEMTEST_START 0x0300000 /* memtest works on */
147#define CONFIG_SYS_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200148
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200150
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200152
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200154
155/*
156 * Low Level Configuration Settings
157 * (address mappings, register initial values, etc.)
158 * You should know what you are doing if you make changes here.
159 */
160/*-----------------------------------------------------------------------
161 * Internal Memory Mapped Register
162 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#define CONFIG_SYS_IMMR 0xFF000000
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200164
165/*-----------------------------------------------------------------------
166 * Definitions for initial stack pointer and data area (in DPRAM)
167 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200168#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
169#define CONFIG_SYS_INIT_RAM_END 0x3000 /* End of used area in DPRAM */
170#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
171#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
172#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200173
174/*-----------------------------------------------------------------------
175 * Start addresses for the final memory configuration
176 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200178 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_SDRAM_BASE 0x00000000
180#define CONFIG_SYS_FLASH_BASE 0x40000000
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200181#if defined(DEBUG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200183#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200185#endif
186
187/* yes this is weird, I know :) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE | 0x00F00000)
189#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200190
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#define CONFIG_SYS_RESET_ADDRESS 0x80000000
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200192
193/*
194 * For booting Linux, the board info and command line data
195 * have to be in the first 8 MB of memory, since this is
196 * the maximum mapped by the Linux kernel during initialization.
197 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200199
200/*-----------------------------------------------------------------------
201 * FLASH organization
202 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200203#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200204#define CONFIG_ENV_SECT_SIZE 0x10000
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200205
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00000000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200207#define CONFIG_ENV_OFFSET 0
208#define CONFIG_ENV_SIZE 0x4000
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200209
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x00010000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200211#define CONFIG_ENV_OFFSET_REDUND 0
212#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200213
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#define CONFIG_SYS_FLASH_CFI 1
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200215#define CONFIG_FLASH_CFI_DRIVER 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */
217#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
218#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200219
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x2000000 }
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200221
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_FLASH_PROTECTION
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200223
224/*-----------------------------------------------------------------------
225 * Cache Configuration
226 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeligeref0df522007-07-04 22:31:07 -0500228#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200230#endif
231
232/*-----------------------------------------------------------------------
233 * SYPCR - System Protection Control 11-9
234 * SYPCR can only be written once after reset!
235 *-----------------------------------------------------------------------
236 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
237 */
238#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200240 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
241#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200243#endif
244
245/*-----------------------------------------------------------------------
246 * SIUMCR - SIU Module Configuration 11-6
247 *-----------------------------------------------------------------------
248 * PCMCIA config., multi-function pin tri-state
249 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC | SIUMCR_GB5E)
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200251
252/*-----------------------------------------------------------------------
253 * TBSCR - Time Base Status and Control 11-26
254 *-----------------------------------------------------------------------
255 * Clear Reference Interrupt Status, Timebase freezing enabled
256 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200257#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200258
259/*-----------------------------------------------------------------------
260 * RTCSC - Real-Time Clock Status and Control Register 11-27
261 *-----------------------------------------------------------------------
262 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200263#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200264
265/*-----------------------------------------------------------------------
266 * PISCR - Periodic Interrupt Status and Control 11-31
267 *-----------------------------------------------------------------------
268 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
269 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200271
272/*-----------------------------------------------------------------------
273 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
274 *-----------------------------------------------------------------------
275 * Reset PLL lock status sticky bit, timer expired status bit and timer
276 * interrupt status bit
277 *
278 */
279
280#if CONFIG_XIN == 10000000
281
282#if MPC8XX_HZ == 50000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200284 (1 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200285 PLPRCR_TEXPS)
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200286#elif MPC8XX_HZ == 66666666
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200287#define CONFIG_SYS_PLPRCR ((1 << PLPRCR_MFN_SHIFT) | (2 << PLPRCR_MFD_SHIFT) | \
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200288 (1 << PLPRCR_S_SHIFT) | (13 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200289 PLPRCR_TEXPS)
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200290#else
291#error unsupported CPU freq for XIN = 10MHz
292#endif
293#else
294#error unsupported freq for XIN (must be 10MHz)
295#endif
296
297
298/*
299 *-----------------------------------------------------------------------
300 * SCCR - System Clock and reset Control Register 15-27
301 *-----------------------------------------------------------------------
302 * Set clock output, timebase and RTC source and divider,
303 * power management and some other internal clocks
304 *
305 * Note: When TBS == 0 the timebase is independent of current cpu clock.
306 */
307
308#define SCCR_MASK SCCR_EBDF11
309#if MPC8XX_HZ > 66666666
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200310#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200311 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
312 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
313 SCCR_DFALCD00 | SCCR_EBDF01)
314#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200315#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200316 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
317 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
318 SCCR_DFALCD00)
319#endif
320
321/*-----------------------------------------------------------------------
322 *
323 *-----------------------------------------------------------------------
324 *
325 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326/*#define CONFIG_SYS_DER 0x2002000F*/
327#define CONFIG_SYS_DER 0
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200328
329/*
330 * Init Memory Controller:
331 *
332 * BR0/1 and OR0/1 (FLASH)
333 */
334
335#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
336#define FLASH_BASE1_PRELIM 0x42000000 /* FLASH bank #1 */
337
338/* used to re-map FLASH both when starting from SRAM or FLASH:
339 * restrict access enough to keep SRAM working (if any)
340 * but not too much to meddle with FLASH accesses
341 */
342
343#define FLASH_BANK_MAX_SIZE 0x01000000 /* max size per chip */
344
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200345#define CONFIG_SYS_REMAP_OR_AM 0x80000000
346#define CONFIG_SYS_PRELIM_OR_AM (0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1))
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200347
348/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200349#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX)
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200350
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200351#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
352#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
353#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200354
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200355#define CONFIG_SYS_OR1_PRELIM ((0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_FLASH)
356#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200357
358/*
359 * BR4 and OR4 (SDRAM)
360 *
361 */
362#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */
363#define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */
364
365/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200366#define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS)
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200367
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200368#define CONFIG_SYS_OR4_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM)
369#define CONFIG_SYS_BR4_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_PS_32 | BR_V)
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200370
371/*
372 * Memory Periodic Timer Prescaler
373 */
374
375/*
376 * Memory Periodic Timer Prescaler
377 *
378 * The Divider for PTA (refresh timer) configuration is based on an
379 * example SDRAM configuration (64 MBit, one bank). The adjustment to
380 * the number of chip selects (NCS) and the actually needed refresh
381 * rate is done by setting MPTPR.
382 *
383 * PTA is calculated from
384 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
385 *
386 * gclk CPU clock (not bus clock!)
387 * Trefresh Refresh cycle * 4 (four word bursts used)
388 *
389 * 4096 Rows from SDRAM example configuration
390 * 1000 factor s -> ms
391 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
392 * 4 Number of refresh cycles per period
393 * 64 Refresh cycle in ms per number of rows
394 * --------------------------------------------
395 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
396 *
397 * 50 MHz => 50.000.000 / Divider = 98
398 * 66 Mhz => 66.000.000 / Divider = 129
399 * 80 Mhz => 80.000.000 / Divider = 156
400 */
401
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200402#define CONFIG_SYS_MAMR_PTA 234
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200403
404/*
405 * For 16 MBit, refresh rates could be 31.3 us
406 * (= 64 ms / 2K = 125 / quad bursts).
407 * For a simpler initialization, 15.6 us is used instead.
408 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200409 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
410 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200411 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200412#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
413#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200414
415/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200416#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
417#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200418
419/*
420 * MAMR settings for SDRAM
421 */
422
423/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200424#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200425 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
426 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
427
428/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200429#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200430 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
431 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
432
433/*
434 * Internal Definitions
435 *
436 * Boot Flags
437 */
438#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
439#define BOOTFLAG_WARM 0x02 /* Software reboot */
440
441#define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */
442
443/****************************************************************/
444
445#define NAND_SIZE 0x00010000 /* 64K */
446#define NAND_BASE 0xF1000000
447
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200448/*****************************************************************************/
449
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200450#define CONFIG_SYS_DIRECT_FLASH_TFTP
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200451
452/*****************************************************************************/
453
454/* Status Leds are on the MODCK pins, which become the PCMCIA PGCRB,
455 * CxOE and CxRESET. We use the CxOE.
456 */
457#define STATUS_LED_BIT 0x00000080 /* bit 24 */
458
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200459#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200460#define STATUS_LED_STATE STATUS_LED_BLINKING
461
462#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
463#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
464
465#ifndef __ASSEMBLY__
466
467/* LEDs */
468
469/* led_id_t is unsigned int mask */
470typedef unsigned int led_id_t;
471
472#define __led_toggle(_msk) \
473 do { \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200474 ((volatile immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcrb ^= (_msk); \
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200475 } while(0)
476
477#define __led_set(_msk, _st) \
478 do { \
479 if ((_st)) \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200480 ((volatile immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcrb |= (_msk); \
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200481 else \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200482 ((volatile immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcrb &= ~(_msk); \
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200483 } while(0)
484
485#define __led_init(msk, st) __led_set(msk, st)
486
487#endif
488
489/******************************************************************************/
490
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200491#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
492#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 1
493#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 1
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200494
495/******************************************************************************/
496
497/* use board specific hardware */
498#undef CONFIG_WATCHDOG /* watchdog disabled */
499#define CONFIG_HW_WATCHDOG
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200500
501/*****************************************************************************/
502
503#define CONFIG_AUTO_COMPLETE 1
504#define CONFIG_CRC32_VERIFY 1
505#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1
506
Wolfgang Denk070610c2005-10-13 01:49:09 +0200507/*****************************************************************************/
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200508
Gerald Van Baren62bcdda2008-06-03 20:26:29 -0400509/* pass open firmware flattened device tree */
510#define CONFIG_OF_LIBFDT 1
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200511
Wolfgang Denk070610c2005-10-13 01:49:09 +0200512#define OF_CPU "PowerPC,MPC870@0"
513#define OF_TBCLK (MPC8XX_HZ / 16)
Wolfgang Denk6bdf4302005-08-15 15:55:00 +0200514
515#endif /* __CONFIG_H */