| b.l.huang | d9c3417 | 2020-06-01 00:02:11 +0800 | [diff] [blame] | 1 | CONFIG_ARM=y |
| 2 | CONFIG_ARCH_ROCKCHIP=y |
| 3 | CONFIG_SYS_TEXT_BASE=0x00200000 |
| Simon Glass | 83061db | 2021-07-10 21:14:30 -0600 | [diff] [blame] | 4 | CONFIG_SPL_GPIO=y |
| Tom Rini | 554e551 | 2020-08-10 15:31:07 -0400 | [diff] [blame] | 5 | CONFIG_NR_DRAM_BANKS=1 |
| b.l.huang | d9c3417 | 2020-06-01 00:02:11 +0800 | [diff] [blame] | 6 | CONFIG_ENV_OFFSET=0x3F8000 |
| Tom Rini | 2bba780 | 2021-06-28 10:17:29 -0400 | [diff] [blame] | 7 | CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock-pi-e" |
| b.l.huang | d9c3417 | 2020-06-01 00:02:11 +0800 | [diff] [blame] | 8 | CONFIG_ROCKCHIP_RK3328=y |
| 9 | CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y |
| 10 | CONFIG_TPL_LIBCOMMON_SUPPORT=y |
| 11 | CONFIG_TPL_LIBGENERIC_SUPPORT=y |
| Simon Glass | 9ca0068 | 2021-07-10 21:14:31 -0600 | [diff] [blame] | 12 | CONFIG_SPL_DRIVERS_MISC=y |
| b.l.huang | d9c3417 | 2020-06-01 00:02:11 +0800 | [diff] [blame] | 13 | CONFIG_SPL_STACK_R_ADDR=0x4000000 |
| 14 | CONFIG_SPL_SYS_MALLOC_F_LEN=0x4000 |
| b.l.huang | d9c3417 | 2020-06-01 00:02:11 +0800 | [diff] [blame] | 15 | CONFIG_DEBUG_UART_BASE=0xFF130000 |
| 16 | CONFIG_DEBUG_UART_CLOCK=24000000 |
| b.l.huang | d9c3417 | 2020-06-01 00:02:11 +0800 | [diff] [blame] | 17 | CONFIG_DEBUG_UART=y |
| 18 | CONFIG_TPL_SYS_MALLOC_F_LEN=0x800 |
| 19 | # CONFIG_ANDROID_BOOT_IMAGE is not set |
| 20 | CONFIG_FIT=y |
| 21 | CONFIG_FIT_VERBOSE=y |
| 22 | CONFIG_SPL_LOAD_FIT=y |
| 23 | CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-rock-pi-e.dtb" |
| b.l.huang | d9c3417 | 2020-06-01 00:02:11 +0800 | [diff] [blame] | 24 | # CONFIG_DISPLAY_CPUINFO is not set |
| 25 | CONFIG_DISPLAY_BOARDINFO_LATE=y |
| Tom Rini | 0817daa | 2020-10-09 12:22:06 -0400 | [diff] [blame] | 26 | CONFIG_MISC_INIT_R=y |
| b.l.huang | d9c3417 | 2020-06-01 00:02:11 +0800 | [diff] [blame] | 27 | # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set |
| 28 | CONFIG_TPL_SYS_MALLOC_SIMPLE=y |
| 29 | CONFIG_SPL_STACK_R=y |
| Tom Rini | 7635def | 2020-06-23 08:20:07 -0400 | [diff] [blame] | 30 | CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 |
| Simon Glass | 975e7cf | 2021-07-10 21:14:36 -0600 | [diff] [blame] | 31 | CONFIG_SPL_I2C=y |
| Simon Glass | 933b2f0 | 2021-07-10 21:14:24 -0600 | [diff] [blame] | 32 | CONFIG_SPL_POWER=y |
| b.l.huang | d9c3417 | 2020-06-01 00:02:11 +0800 | [diff] [blame] | 33 | CONFIG_SPL_ATF=y |
| 34 | CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y |
| Simon Glass | 9ca0068 | 2021-07-10 21:14:31 -0600 | [diff] [blame] | 35 | CONFIG_TPL_DRIVERS_MISC=y |
| b.l.huang | d9c3417 | 2020-06-01 00:02:11 +0800 | [diff] [blame] | 36 | CONFIG_CMD_BOOTZ=y |
| 37 | CONFIG_CMD_GPT=y |
| 38 | CONFIG_CMD_MMC=y |
| 39 | CONFIG_CMD_USB=y |
| 40 | CONFIG_CMD_TIME=y |
| 41 | CONFIG_SPL_OF_CONTROL=y |
| 42 | CONFIG_TPL_OF_CONTROL=y |
| b.l.huang | d9c3417 | 2020-06-01 00:02:11 +0800 | [diff] [blame] | 43 | CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" |
| 44 | CONFIG_TPL_OF_PLATDATA=y |
| 45 | CONFIG_ENV_IS_IN_MMC=y |
| 46 | CONFIG_SYS_RELOC_GD_ENV_ADDR=y |
| Tom Rini | 7d08077 | 2020-07-24 17:14:47 -0400 | [diff] [blame] | 47 | CONFIG_SYS_MMC_ENV_DEV=1 |
| b.l.huang | d9c3417 | 2020-06-01 00:02:11 +0800 | [diff] [blame] | 48 | CONFIG_NET_RANDOM_ETHADDR=y |
| 49 | CONFIG_TPL_DM=y |
| 50 | CONFIG_REGMAP=y |
| 51 | CONFIG_SPL_REGMAP=y |
| 52 | CONFIG_TPL_REGMAP=y |
| 53 | CONFIG_SYSCON=y |
| 54 | CONFIG_SPL_SYSCON=y |
| 55 | CONFIG_TPL_SYSCON=y |
| 56 | CONFIG_CLK=y |
| 57 | CONFIG_SPL_CLK=y |
| 58 | CONFIG_FASTBOOT_BUF_ADDR=0x800800 |
| 59 | CONFIG_FASTBOOT_CMD_OEM_FORMAT=y |
| 60 | CONFIG_ROCKCHIP_GPIO=y |
| 61 | CONFIG_SYS_I2C_ROCKCHIP=y |
| 62 | CONFIG_MMC_DW=y |
| 63 | CONFIG_MMC_DW_ROCKCHIP=y |
| 64 | CONFIG_SF_DEFAULT_SPEED=20000000 |
| 65 | CONFIG_DM_ETH=y |
| 66 | CONFIG_ETH_DESIGNWARE=y |
| 67 | CONFIG_GMAC_ROCKCHIP=y |
| 68 | CONFIG_PHY=y |
| 69 | CONFIG_PINCTRL=y |
| 70 | CONFIG_SPL_PINCTRL=y |
| 71 | CONFIG_DM_PMIC=y |
| 72 | CONFIG_PMIC_RK8XX=y |
| 73 | CONFIG_SPL_DM_REGULATOR=y |
| 74 | CONFIG_REGULATOR_PWM=y |
| b.l.huang | d9c3417 | 2020-06-01 00:02:11 +0800 | [diff] [blame] | 75 | CONFIG_DM_REGULATOR_FIXED=y |
| Tom Rini | 7635def | 2020-06-23 08:20:07 -0400 | [diff] [blame] | 76 | CONFIG_SPL_DM_REGULATOR_FIXED=y |
| b.l.huang | d9c3417 | 2020-06-01 00:02:11 +0800 | [diff] [blame] | 77 | CONFIG_REGULATOR_RK8XX=y |
| 78 | CONFIG_PWM_ROCKCHIP=y |
| 79 | CONFIG_RAM=y |
| 80 | CONFIG_SPL_RAM=y |
| 81 | CONFIG_TPL_RAM=y |
| 82 | CONFIG_DM_RESET=y |
| 83 | CONFIG_BAUDRATE=1500000 |
| 84 | CONFIG_DEBUG_UART_SHIFT=2 |
| 85 | CONFIG_DEBUG_UART_ANNOUNCE=y |
| 86 | CONFIG_DEBUG_UART_SKIP_INIT=y |
| Tom Rini | 74f11b5 | 2020-11-09 14:23:01 -0500 | [diff] [blame] | 87 | CONFIG_SYSINFO=y |
| 88 | CONFIG_SYSINFO_SMBIOS=y |
| b.l.huang | d9c3417 | 2020-06-01 00:02:11 +0800 | [diff] [blame] | 89 | CONFIG_SYSRESET=y |
| 90 | # CONFIG_TPL_SYSRESET is not set |
| 91 | CONFIG_USB=y |
| 92 | CONFIG_USB_XHCI_HCD=y |
| 93 | CONFIG_USB_XHCI_DWC3=y |
| 94 | CONFIG_USB_EHCI_HCD=y |
| 95 | CONFIG_USB_EHCI_GENERIC=y |
| 96 | CONFIG_USB_OHCI_HCD=y |
| 97 | CONFIG_USB_OHCI_GENERIC=y |
| 98 | CONFIG_USB_DWC2=y |
| 99 | CONFIG_USB_DWC3=y |
| 100 | # CONFIG_USB_DWC3_GADGET is not set |
| 101 | CONFIG_USB_GADGET=y |
| 102 | CONFIG_USB_GADGET_DWC2_OTG=y |
| 103 | CONFIG_SPL_TINY_MEMSET=y |
| 104 | CONFIG_TPL_TINY_MEMSET=y |
| 105 | CONFIG_ERRNO_STR=y |