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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / d826b8751925aa535fd692f157b6d0dbfbea490a / . / arch / powerpc / include / asm / config.h
blob: bf11f40e23138ac322e383b5d7ce1207a4ecb78d [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Kumar Gala47d41cc2009-02-05 20:40:57 -0600[diff] [blame]2/*
Poonam Aggrwalb8cdd012011-01-13 21:39:27 +0530[diff] [blame]3 * Copyright 2009-2011 Freescale Semiconductor, Inc.
Kumar Gala47d41cc2009-02-05 20:40:57 -0600[diff] [blame]4 */
5
6#ifndef _ASM_CONFIG_H_
7#define _ASM_CONFIG_H_
8
Kumar Gala243be8e2011-01-19 03:05:26 -0600[diff] [blame]9#ifdef CONFIG_MPC85xx
10#include <asm/config_mpc85xx.h>
11#endif
12
13#ifdef CONFIG_MPC86xx
14#include <asm/config_mpc86xx.h>
York Sun5614e712013-09-30 09:22:09 -0700[diff] [blame]15#endif
16
York Sun7ac3cc22012-08-17 09:00:54 +0000[diff] [blame]17#ifndef HWCONFIG_BUFFER_SIZE
18 #define HWCONFIG_BUFFER_SIZE 256
19#endif
20
Mingkai Hu273feaf2011-04-26 16:31:16 +0800[diff] [blame]21/* CONFIG_HARD_SPI triggers SPI bus initialization in PowerPC */
22#if defined(CONFIG_MPC8XXX_SPI) || defined(CONFIG_FSL_ESPI)
23# ifndef CONFIG_HARD_SPI
24# define CONFIG_HARD_SPI
25# endif
26#endif
27
Mike Frysingera16028d2009-11-03 11:35:59 -0500[diff] [blame]28#define CONFIG_LMB
John Rigbyfca43cc2010-10-13 13:57:35 -0600[diff] [blame]29#define CONFIG_SYS_BOOT_RAMDISK_HIGH
Mike Frysingera16028d2009-11-03 11:35:59 -0500[diff] [blame]30
Kumar Gala87c90632009-02-05 20:40:58 -0600[diff] [blame]31#ifndef CONFIG_MAX_MEM_MAPPED
Heiko Schocher98f705c2017-06-27 16:49:14 +0200[diff] [blame]32#if defined(CONFIG_E500) || \
York Sund29d17d2011-08-26 11:32:44 -0700[diff] [blame]33 defined(CONFIG_MPC86xx) || \
34 defined(CONFIG_E300)
Kumar Gala87c90632009-02-05 20:40:58 -0600[diff] [blame]35#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30)
36#else
Stefan Roese2ede8792009-02-11 09:37:12 +0100[diff] [blame]37#define CONFIG_MAX_MEM_MAPPED (256 << 20)
Kumar Gala87c90632009-02-05 20:40:58 -0600[diff] [blame]38#endif
39#endif
40
Peter Tyserf732a752009-07-15 00:01:08 -0500[diff] [blame]41/* Check if boards need to enable FSL DMA engine for SDRAM init */
42#if !defined(CONFIG_FSL_DMA) && defined(CONFIG_DDR_ECC)
43#if (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)) || \
44 ((defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) && \
45 !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER))
Peter Tyser017f11f2009-06-30 17:15:40 -0500[diff] [blame]46#define CONFIG_FSL_DMA
Kumar Gala47d41cc2009-02-05 20:40:57 -0600[diff] [blame]47#endif
Peter Tyser017f11f2009-06-30 17:15:40 -0500[diff] [blame]48#endif
49
Peter Tyser5ccd29c2009-10-23 15:55:47 -0500[diff] [blame]50/*
51 * Provide a default boot page translation virtual address that lines up with
52 * Freescale's default e500 reset page.
53 */
54#if (defined(CONFIG_E500) && defined(CONFIG_MP))
55#ifndef CONFIG_BPTR_VIRT_ADDR
56#define CONFIG_BPTR_VIRT_ADDR 0xfffff000
57#endif
58#endif
59
Becky Brucef51cdaf2010-06-17 11:37:20 -0500[diff] [blame]60/* Since so many PPC SOCs have a semi-common LBC, define this here */
61#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \
62 defined(CONFIG_MPC83xx)
Dipen Dudhatd789b5f2011-01-20 16:29:35 +0530[diff] [blame]63#if !defined(CONFIG_FSL_IFC)
Becky Brucef51cdaf2010-06-17 11:37:20 -0500[diff] [blame]64#define CONFIG_FSL_LBC
65#endif
Dipen Dudhatd789b5f2011-01-20 16:29:35 +0530[diff] [blame]66#endif
Becky Brucef51cdaf2010-06-17 11:37:20 -0500[diff] [blame]67
Andy Fleming063c1262011-04-08 02:10:54 -0500[diff] [blame]68/* The TSEC driver uses the PHYLIB infrastructure */
Zhao Qiang990d06b2018-02-07 10:01:56 +0800[diff] [blame]69#if defined(CONFIG_TSEC_ENET) && defined(CONFIG_PHYLIB)
Andy Fleming063c1262011-04-08 02:10:54 -0500[diff] [blame]70#include <config_phylib_all_drivers.h>
71#endif /* TSEC_ENET */
Andy Fleming063c1262011-04-08 02:10:54 -0500[diff] [blame]72
Kumar Galac916d7c2011-04-13 08:37:44 -0500[diff] [blame]73/* The FMAN driver uses the PHYLIB infrastructure */
Kumar Galac916d7c2011-04-13 08:37:44 -0500[diff] [blame]74
Albert Aribaudf2a37fc2010-08-08 05:17:05 +0530[diff] [blame]75/* All PPC boards must swap IDE bytes */
76#define CONFIG_IDE_SWAP_IO
77
Thomas Chouf27445c2015-11-19 21:48:07 +0800[diff] [blame]78#if defined(CONFIG_DM_SERIAL)
79/*
80 * TODO: Convert this to a clock driver exists that can give us the UART
81 * clock here.
82 */
83#define CONFIG_SYS_NS16550_CLK get_serial_clock()
84#endif
85
Peter Tyser017f11f2009-06-30 17:15:40 -0500[diff] [blame]86#endif /* _ASM_CONFIG_H_ */