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wdenked247f42002-10-07 21:58:02 +00001/*
Wolfgang Denk8e6f1a82005-09-25 18:59:36 +02002 * (C) Copyright 2000-2005
wdenked247f42002-10-07 21:58:02 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenked247f42002-10-07 21:58:02 +00006 */
7
8#ifndef _FLASH_H_
9#define _FLASH_H_
10
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020011#ifndef CONFIG_SYS_NO_FLASH
wdenked247f42002-10-07 21:58:02 +000012/*-----------------------------------------------------------------------
13 * FLASH Info: contains chip specific data, per FLASH bank
14 */
15
16typedef struct {
17 ulong size; /* total bank size in bytes */
18 ushort sector_count; /* number of erase units */
19 ulong flash_id; /* combined device & manufacturer code */
Becky Bruce09ce9922009-02-02 16:34:51 -060020 ulong start[CONFIG_SYS_MAX_FLASH_SECT]; /* virtual sector start address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020021 uchar protect[CONFIG_SYS_MAX_FLASH_SECT]; /* sector protection status */
22#ifdef CONFIG_SYS_FLASH_CFI
wdenked247f42002-10-07 21:58:02 +000023 uchar portwidth; /* the width of the port */
24 uchar chipwidth; /* the width of the chip */
wdenk2abbe072003-06-16 23:50:08 +000025 ushort buffer_size; /* # of bytes in write buffer */
wdenked247f42002-10-07 21:58:02 +000026 ulong erase_blk_tout; /* maximum block erase timeout */
27 ulong write_tout; /* maximum write timeout */
wdenk2abbe072003-06-16 23:50:08 +000028 ulong buffer_write_tout; /* maximum buffer write timeout */
wdenk1eaeb582004-06-08 00:22:43 +000029 ushort vendor; /* the primary vendor id */
Stefan Roese260421a2006-11-13 13:55:24 +010030 ushort cmd_reset; /* vendor specific reset command */
Angelo Dureghello07b2c5c2012-12-01 01:14:18 +010031 uchar cmd_erase_sector; /* vendor specific erase sect. command */
wdenk1eaeb582004-06-08 00:22:43 +000032 ushort interface; /* used for x8/x16 adjustments */
Stefan Roese2662b402006-04-01 13:41:03 +020033 ushort legacy_unlock; /* support Intel legacy (un)locking */
Niklaus Giger3a7b2c22009-07-22 17:13:24 +020034 ushort manufacturer_id; /* manufacturer id */
Stefan Roese260421a2006-11-13 13:55:24 +010035 ushort device_id; /* device id */
36 ushort device_id2; /* extended device id */
37 ushort ext_addr; /* extended query table address */
38 ushort cfi_version; /* cfi version */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020039 ushort cfi_offset; /* offset for cfi query */
Michael Schwingen81b20cc2007-12-07 23:35:02 +010040 ulong addr_unlock1; /* unlock address 1 for AMD flash roms */
41 ulong addr_unlock2; /* unlock address 2 for AMD flash roms */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020042 const char *name; /* human-readable name */
wdenked247f42002-10-07 21:58:02 +000043#endif
Thomas Choud8587992015-11-07 14:20:31 +080044#ifdef CONFIG_MTD
45 struct mtd_info *mtd;
46#endif
wdenked247f42002-10-07 21:58:02 +000047} flash_info_t;
48
Stefan Roeseca5def32010-08-31 10:00:10 +020049extern flash_info_t flash_info[]; /* info for FLASH chips */
50
Piotr Ziecikebc97842008-11-20 15:17:38 +010051typedef unsigned long flash_sect_t;
52
wdenked247f42002-10-07 21:58:02 +000053/*
54 * Values for the width of the port
55 */
56#define FLASH_CFI_8BIT 0x01
57#define FLASH_CFI_16BIT 0x02
58#define FLASH_CFI_32BIT 0x04
59#define FLASH_CFI_64BIT 0x08
60/*
61 * Values for the width of the chip
62 */
63#define FLASH_CFI_BY8 0x01
64#define FLASH_CFI_BY16 0x02
65#define FLASH_CFI_BY32 0x04
66#define FLASH_CFI_BY64 0x08
wdenkbf9e3b32004-02-12 00:47:09 +000067/* convert between bit value and numeric value */
wdenk1eaeb582004-06-08 00:22:43 +000068#define CFI_FLASH_SHIFT_WIDTH 3
wdenkbf9e3b32004-02-12 00:47:09 +000069/*
70 * Values for the flash device interface
71 */
72#define FLASH_CFI_X8 0x00
73#define FLASH_CFI_X16 0x01
74#define FLASH_CFI_X8X16 0x02
Bartlomiej Sieka42026c92007-12-11 13:59:57 +010075#define FLASH_CFI_X16X32 0x05
wdenked247f42002-10-07 21:58:02 +000076
wdenk5653fc32004-02-08 22:55:38 +000077/* convert between bit value and numeric value */
wdenk1eaeb582004-06-08 00:22:43 +000078#define CFI_FLASH_SHIFT_WIDTH 3
Piotr Ziecik91809ed2008-11-17 15:57:58 +010079
wdenked247f42002-10-07 21:58:02 +000080/* Prototypes */
81
82extern unsigned long flash_init (void);
Heiko Schocher6ee14162011-04-04 08:10:21 +020083extern void flash_protect_default(void);
wdenked247f42002-10-07 21:58:02 +000084extern void flash_print_info (flash_info_t *);
85extern int flash_erase (flash_info_t *, int, int);
86extern int flash_sect_erase (ulong addr_first, ulong addr_last);
87extern int flash_sect_protect (int flag, ulong addr_first, ulong addr_last);
Bartlomiej Sieka3f0cf512008-10-01 15:26:27 +020088extern int flash_sect_roundb (ulong *addr);
Piotr Ziecikebc97842008-11-20 15:17:38 +010089extern unsigned long flash_sector_size(flash_info_t *info, flash_sect_t sect);
Piotr Ziecik6ea808e2008-11-17 15:49:32 +010090extern void flash_set_verbose(uint);
wdenked247f42002-10-07 21:58:02 +000091
92/* common/flash.c */
93extern void flash_protect (int flag, ulong from, ulong to, flash_info_t *info);
Wolfgang Denk77ddac92005-10-13 16:45:02 +020094extern int flash_write (char *, ulong, ulong);
wdenked247f42002-10-07 21:58:02 +000095extern flash_info_t *addr2info (ulong);
96extern int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt);
97
Piotr Ziecik91809ed2008-11-17 15:57:58 +010098/* drivers/mtd/cfi_mtd.c */
99#ifdef CONFIG_FLASH_CFI_MTD
100extern int cfi_mtd_init(void);
101#endif
102
wdenked247f42002-10-07 21:58:02 +0000103/* board/?/flash.c */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104#if defined(CONFIG_SYS_FLASH_PROTECTION)
wdenked247f42002-10-07 21:58:02 +0000105extern int flash_real_protect(flash_info_t *info, long sector, int prot);
wdenk5653fc32004-02-08 22:55:38 +0000106extern void flash_read_user_serial(flash_info_t * info, void * buffer, int offset, int len);
107extern void flash_read_factory_serial(flash_info_t * info, void * buffer, int offset, int len);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108#endif /* CONFIG_SYS_FLASH_PROTECTION */
wdenked247f42002-10-07 21:58:02 +0000109
Michael Schwingen81b20cc2007-12-07 23:35:02 +0100110#ifdef CONFIG_FLASH_CFI_LEGACY
111extern ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info);
112extern int jedec_flash_match(flash_info_t *info, ulong base);
113#define CFI_CMDSET_AMD_LEGACY 0xFFF0
114#endif
115
Heiko Schocher4f975672009-02-10 09:53:29 +0100116#if defined(CONFIG_SYS_FLASH_CFI)
117extern flash_info_t *flash_get_info(ulong base);
118#endif
Michael Schwingen81b20cc2007-12-07 23:35:02 +0100119
wdenked247f42002-10-07 21:58:02 +0000120/*-----------------------------------------------------------------------
121 * return codes from flash_write():
122 */
123#define ERR_OK 0
124#define ERR_TIMOUT 1
125#define ERR_NOT_ERASED 2
126#define ERR_PROTECTED 4
127#define ERR_INVAL 8
128#define ERR_ALIGN 16
129#define ERR_UNKNOWN_FLASH_VENDOR 32
130#define ERR_UNKNOWN_FLASH_TYPE 64
131#define ERR_PROG_ERROR 128
Joe Hershbergerde15a062012-08-17 15:36:41 -0500132#define ERR_ABORTED 256
wdenked247f42002-10-07 21:58:02 +0000133
134/*-----------------------------------------------------------------------
135 * Protection Flags for flash_protect():
136 */
137#define FLAG_PROTECT_SET 0x01
138#define FLAG_PROTECT_CLEAR 0x02
Peter Pearsed4fc6012007-08-14 10:10:52 +0100139#define FLAG_PROTECT_INVALID 0x03
140/*-----------------------------------------------------------------------
141 * Set Environment according to label:
142 */
143#define FLAG_SETENV 0x80
wdenked247f42002-10-07 21:58:02 +0000144
145/*-----------------------------------------------------------------------
146 * Device IDs
147 */
148
Niklaus Giger3a7b2c22009-07-22 17:13:24 +0200149/* Manufacturers inside bank 0 have ids like 0x00xx00xx */
wdenk2abbe072003-06-16 23:50:08 +0000150#define AMD_MANUFACT 0x00010001 /* AMD manuf. ID in D23..D16, D7..D0 */
wdenked247f42002-10-07 21:58:02 +0000151#define FUJ_MANUFACT 0x00040004 /* FUJITSU manuf. ID in D23..D16, D7..D0 */
wdenk2abbe072003-06-16 23:50:08 +0000152#define ATM_MANUFACT 0x001F001F /* ATMEL */
153#define STM_MANUFACT 0x00200020 /* STM (Thomson) manuf. ID in D23.. -"- */
154#define SST_MANUFACT 0x00BF00BF /* SST manuf. ID in D23..D16, D7..D0 */
155#define MT_MANUFACT 0x00890089 /* MT manuf. ID in D23..D16, D7..D0 */
wdenked247f42002-10-07 21:58:02 +0000156#define INTEL_MANUFACT 0x00890089 /* INTEL manuf. ID in D23..D16, D7..D0 */
wdenk2abbe072003-06-16 23:50:08 +0000157#define INTEL_ALT_MANU 0x00B000B0 /* alternate INTEL namufacturer ID */
wdenked247f42002-10-07 21:58:02 +0000158#define MX_MANUFACT 0x00C200C2 /* MXIC manuf. ID in D23..D16, D7..D0 */
wdenk608c9142003-01-13 23:54:46 +0000159#define TOSH_MANUFACT 0x00980098 /* TOSHIBA manuf. ID in D23..D16, D7..D0 */
wdenk1eaeb582004-06-08 00:22:43 +0000160#define MT2_MANUFACT 0x002C002C /* alternate MICRON manufacturer ID*/
Wolfgang Denk8e6f1a82005-09-25 18:59:36 +0200161#define EXCEL_MANUFACT 0x004A004A /* Excel Semiconductor */
Niklaus Giger3a7b2c22009-07-22 17:13:24 +0200162#define AMIC_MANUFACT 0x00370037 /* AMIC manuf. ID in D23..D16, D7..D0 */
163#define WINB_MANUFACT 0x00DA00DA /* Winbond manuf. ID in D23..D16, D7..D0 */
Dirk Eibachf3c89d92014-11-13 19:21:13 +0100164#define EON_ALT_MANU 0x001C001C /* EON manuf. ID in D23..D16, D7..D0 */
Niklaus Giger3a7b2c22009-07-22 17:13:24 +0200165
166/* Manufacturers inside bank 1 have ids like 0x01xx01xx */
167#define EON_MANUFACT 0x011C011C /* EON manuf. ID in D23..D16, D7..D0 */
168
169/* Manufacturers inside bank 2 have ids like 0x02xx02xx */
wdenked247f42002-10-07 21:58:02 +0000170
171 /* Micron Technologies (INTEL compat.) */
172#define MT_ID_28F400_T 0x44704470 /* 28F400B3 ID ( 4 M, top boot sector) */
wdenk2abbe072003-06-16 23:50:08 +0000173#define MT_ID_28F400_B 0x44714471 /* 28F400B3 ID ( 4 M, bottom boot sect) */
wdenked247f42002-10-07 21:58:02 +0000174
175#define AMD_ID_LV040B 0x4F /* 29LV040B ID */
176 /* 4 Mbit, 512K x 8, */
177 /* 8 64K x 8 uniform sectors */
Wolfgang Denk8e6f1a82005-09-25 18:59:36 +0200178#define AMD_ID_F033C 0xA3 /* 29LV033C ID */
179 /* 32 Mbit, 4Mbits x 8, */
180 /* 64 64K x 8 uniform sectors */
181#define AMD_ID_F065D 0x93 /* 29LV065D ID */
182 /* 64 Mbit, 8Mbits x 8, */
183 /* 126 64K x 8 uniform sectors */
184#define ATM_ID_LV040 0x13 /* 29LV040B ID */
185 /* 4 Mbit, 512K x 8, */
186 /* 8 64K x 8 uniform sectors */
wdenked247f42002-10-07 21:58:02 +0000187#define AMD_ID_F040B 0xA4 /* 29F040B ID */
188 /* 4 Mbit, 512K x 8, */
189 /* 8 64K x 8 uniform sectors */
wdenk2abbe072003-06-16 23:50:08 +0000190#define STM_ID_M29W040B 0xE3 /* M29W040B ID */
wdenked247f42002-10-07 21:58:02 +0000191 /* 4 Mbit, 512K x 8, */
192 /* 8 64K x 8 uniform sectors */
193#define AMD_ID_F080B 0xD5 /* 29F080 ID ( 1 M) */
wdenk5d232d02003-05-22 22:52:13 +0000194 /* 8 Mbit, 512K x 16, */
195 /* 8 64K x 16 uniform sectors */
wdenked247f42002-10-07 21:58:02 +0000196#define AMD_ID_F016D 0xAD /* 29F016 ID ( 2 M x 8) */
197#define AMD_ID_F032B 0x41 /* 29F032 ID ( 4 M x 8) */
198#define AMD_ID_LV116DT 0xC7 /* 29LV116DT ( 2 M x 8, top boot sect) */
Wolfgang Denk8e6f1a82005-09-25 18:59:36 +0200199#define AMD_ID_LV116DB 0x4C /* 29LV116DB ( 2 M x 8, bottom boot sect) */
wdenk7a8e9bed2003-05-31 18:35:21 +0000200#define AMD_ID_LV016B 0xc8 /* 29LV016 ID ( 2 M x 8) */
wdenked247f42002-10-07 21:58:02 +0000201
Wolfgang Denk8e6f1a82005-09-25 18:59:36 +0200202#define AMD_ID_PL160CB 0x22452245 /* 29PL160CB ID (16 M, bottom boot sect */
wdenk4e5ca3e2003-12-08 01:34:36 +0000203
wdenked247f42002-10-07 21:58:02 +0000204#define AMD_ID_LV400T 0x22B922B9 /* 29LV400T ID ( 4 M, top boot sector) */
wdenk2abbe072003-06-16 23:50:08 +0000205#define AMD_ID_LV400B 0x22BA22BA /* 29LV400B ID ( 4 M, bottom boot sect) */
wdenked247f42002-10-07 21:58:02 +0000206
wdenkd1cbe852003-06-28 17:24:46 +0000207#define AMD_ID_LV033C 0xA3 /* 29LV033C ID ( 4 M x 8) */
208#define AMD_ID_LV065D 0x93 /* 29LV065D ID ( 8 M x 8) */
wdenked247f42002-10-07 21:58:02 +0000209
210#define AMD_ID_LV800T 0x22DA22DA /* 29LV800T ID ( 8 M, top boot sector) */
wdenk2abbe072003-06-16 23:50:08 +0000211#define AMD_ID_LV800B 0x225B225B /* 29LV800B ID ( 8 M, bottom boot sect) */
wdenked247f42002-10-07 21:58:02 +0000212
213#define AMD_ID_LV160T 0x22C422C4 /* 29LV160T ID (16 M, top boot sector) */
wdenk2abbe072003-06-16 23:50:08 +0000214#define AMD_ID_LV160B 0x22492249 /* 29LV160B ID (16 M, bottom boot sect) */
wdenked247f42002-10-07 21:58:02 +0000215
wdenk3bbc8992003-12-07 22:27:15 +0000216#define AMD_ID_DL163T 0x22282228 /* 29DL163T ID (16 M, top boot sector) */
Wolfgang Denk8e6f1a82005-09-25 18:59:36 +0200217#define AMD_ID_DL163B 0x222B222B /* 29DL163B ID (16 M, bottom boot sect) */
wdenk3bbc8992003-12-07 22:27:15 +0000218
wdenked247f42002-10-07 21:58:02 +0000219#define AMD_ID_LV320T 0x22F622F6 /* 29LV320T ID (32 M, top boot sector) */
wdenkefa329c2004-03-23 20:18:25 +0000220#define MX_ID_LV320T 0x22A722A7 /* 29LV320T by Macronix, AMD compatible */
wdenk2abbe072003-06-16 23:50:08 +0000221#define AMD_ID_LV320B 0x22F922F9 /* 29LV320B ID (32 M, bottom boot sect) */
wdenkefa329c2004-03-23 20:18:25 +0000222#define MX_ID_LV320B 0x22A822A8 /* 29LV320B by Macronix, AMD compatible */
wdenked247f42002-10-07 21:58:02 +0000223
224#define AMD_ID_DL322T 0x22552255 /* 29DL322T ID (32 M, top boot sector) */
wdenk2abbe072003-06-16 23:50:08 +0000225#define AMD_ID_DL322B 0x22562256 /* 29DL322B ID (32 M, bottom boot sect) */
wdenked247f42002-10-07 21:58:02 +0000226#define AMD_ID_DL323T 0x22502250 /* 29DL323T ID (32 M, top boot sector) */
wdenk2abbe072003-06-16 23:50:08 +0000227#define AMD_ID_DL323B 0x22532253 /* 29DL323B ID (32 M, bottom boot sect) */
wdenked247f42002-10-07 21:58:02 +0000228#define AMD_ID_DL324T 0x225C225C /* 29DL324T ID (32 M, top boot sector) */
229#define AMD_ID_DL324B 0x225F225F /* 29DL324B ID (32 M, bottom boot sect) */
230
231#define AMD_ID_DL640 0x227E227E /* 29DL640D ID (64 M, dual boot sectors)*/
wdenk2abbe072003-06-16 23:50:08 +0000232#define AMD_ID_MIRROR 0x227E227E /* 1st ID word for MirrorBit family */
Wolfgang Denk8e6f1a82005-09-25 18:59:36 +0200233#define AMD_ID_DL640G_2 0x22022202 /* 2nd ID word for AM29DL640G at 0x38 */
234#define AMD_ID_DL640G_3 0x22012201 /* 3rd ID word for AM29DL640G at 0x3c */
235#define AMD_ID_LV640U_2 0x220C220C /* 2nd ID word for AM29LV640M at 0x38 */
236#define AMD_ID_LV640U_3 0x22012201 /* 3rd ID word for AM29LV640M at 0x3c */
wdenkaa5590b2004-06-09 12:42:26 +0000237#define AMD_ID_LV640MT_2 0x22102210 /* 2nd ID word for AM29LV640MT at 0x38 */
238#define AMD_ID_LV640MT_3 0x22012201 /* 3rd ID word for AM29LV640MT at 0x3c */
239#define AMD_ID_LV640MB_2 0x22102210 /* 2nd ID word for AM29LV640MB at 0x38 */
240#define AMD_ID_LV640MB_3 0x22002200 /* 3rd ID word for AM29LV640MB at 0x3c */
241#define AMD_ID_LV128U_2 0x22122212 /* 2nd ID word for AM29LV128M at 0x38 */
242#define AMD_ID_LV128U_3 0x22002200 /* 3rd ID word for AM29LV128M at 0x3c */
243#define AMD_ID_LV256U_2 0x22122212 /* 2nd ID word for AM29LV256M at 0x38 */
244#define AMD_ID_LV256U_3 0x22012201 /* 3rd ID word for AM29LV256M at 0x3c */
wdenk9d5028c2004-11-21 00:06:33 +0000245#define AMD_ID_GL064M_2 0x22132213 /* 2nd ID word for S29GL064M-R6 */
246#define AMD_ID_GL064M_3 0x22012201 /* 3rd ID word for S29GL064M-R6 */
Wolfgang Denk45237bc2005-10-05 00:03:55 +0200247#define AMD_ID_GL064MT_2 0x22102210 /* 2nd ID word for S29GL064M-R3 (top boot sector) */
248#define AMD_ID_GL064MT_3 0x22012201 /* 3rd ID word for S29GL064M-R3 (top boot sector) */
Marian Balakowicz72997122006-10-03 20:28:38 +0200249#define AMD_ID_GL128N_2 0x22212221 /* 2nd ID word for S29GL128N */
250#define AMD_ID_GL128N_3 0x22012201 /* 3rd ID word for S29GL128N */
251
wdenkd4ca31c2004-01-02 14:00:00 +0000252
Wolfgang Denk8e6f1a82005-09-25 18:59:36 +0200253#define AMD_ID_LV320B_2 0x221A221A /* 2d ID word for AM29LV320MB at 0x38 */
wdenkd4ca31c2004-01-02 14:00:00 +0000254#define AMD_ID_LV320B_3 0x22002200 /* 3d ID word for AM29LV320MB at 0x3c */
wdenk71f95112003-06-15 22:40:42 +0000255
wdenked247f42002-10-07 21:58:02 +0000256#define AMD_ID_LV640U 0x22D722D7 /* 29LV640U ID (64 M, uniform sectors) */
Wolfgang Denk8e6f1a82005-09-25 18:59:36 +0200257#define AMD_ID_LV650U 0x22D722D7 /* 29LV650U ID (64 M, uniform sectors) */
wdenked247f42002-10-07 21:58:02 +0000258
wdenk8b07a112004-07-10 21:45:47 +0000259#define ATM_ID_BV1614 0x000000C0 /* 49BV1614 ID */
wdenk2abbe072003-06-16 23:50:08 +0000260#define ATM_ID_BV1614A 0x000000C8 /* 49BV1614A ID */
wdenk8b07a112004-07-10 21:45:47 +0000261#define ATM_ID_BV6416 0x000000D6 /* 49BV6416 ID */
wdenkdc7c9a12003-03-26 06:55:25 +0000262
wdenk2abbe072003-06-16 23:50:08 +0000263#define FUJI_ID_29F800BA 0x22582258 /* MBM29F800BA ID (8M) */
264#define FUJI_ID_29F800TA 0x22D622D6 /* MBM29F800TA ID (8M) */
wdenkbf9e3b32004-02-12 00:47:09 +0000265#define FUJI_ID_29LV650UE 0x22d722d7 /* MBM29LV650UE/651UE ID (8M = 128 x 32kWord) */
wdenk56f94be2002-11-05 16:35:14 +0000266
wdenk2abbe072003-06-16 23:50:08 +0000267#define SST_ID_xF200A 0x27892789 /* 39xF200A ID ( 2M = 128K x 16 ) */
268#define SST_ID_xF400A 0x27802780 /* 39xF400A ID ( 4M = 256K x 16 ) */
269#define SST_ID_xF800A 0x27812781 /* 39xF800A ID ( 8M = 512K x 16 ) */
270#define SST_ID_xF160A 0x27822782 /* 39xF800A ID (16M = 1M x 16 ) */
stroese4d535b52004-12-16 18:01:48 +0000271#define SST_ID_xF1601 0x234B234B /* 39xF1601 ID (16M = 1M x 16 ) */
272#define SST_ID_xF1602 0x234A234A /* 39xF1602 ID (16M = 1M x 16 ) */
273#define SST_ID_xF3201 0x235B235B /* 39xF3201 ID (32M = 2M x 16 ) */
274#define SST_ID_xF3202 0x235A235A /* 39xF3202 ID (32M = 2M x 16 ) */
275#define SST_ID_xF6401 0x236B236B /* 39xF6401 ID (64M = 4M x 16 ) */
276#define SST_ID_xF6402 0x236A236A /* 39xF6402 ID (64M = 4M x 16 ) */
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200277#define SST_ID_xF020 0xBFD6BFD6 /* 39xF020 ID (256KB = 2Mbit x 8) */
wdenkd1cbe852003-06-28 17:24:46 +0000278#define SST_ID_xF040 0xBFD7BFD7 /* 39xF040 ID (512KB = 4Mbit x 8) */
wdenked247f42002-10-07 21:58:02 +0000279
wdenk2abbe072003-06-16 23:50:08 +0000280#define STM_ID_F040B 0xE2 /* M29F040B ID ( 4M = 512K x 8 ) */
wdenked247f42002-10-07 21:58:02 +0000281 /* 8 64K x 8 uniform sectors */
282
wdenk2abbe072003-06-16 23:50:08 +0000283#define STM_ID_x800AB 0x005B005B /* M29W800AB ID (8M = 512K x 16 ) */
284#define STM_ID_29W320DT 0x22CA22CA /* M29W320DT ID (32 M, top boot sector) */
285#define STM_ID_29W320DB 0x22CB22CB /* M29W320DB ID (32 M, bottom boot sect) */
Aubrey Li8e709bb2007-03-19 01:26:11 +0800286#define STM_ID_29W320ET 0x22562256 /* M29W320ET ID (32 M, top boot sector) */
287#define STM_ID_29W320EB 0x22572257 /* M29W320EB ID (32 M, bottom boot sect)*/
wdenked247f42002-10-07 21:58:02 +0000288#define STM_ID_29W040B 0x00E300E3 /* M29W040B ID (4M = 512K x 8) */
Wolfgang Denk0afe5192006-03-12 02:10:00 +0100289#define FLASH_PSD4256GV 0x00E9 /* PSD4256 Flash and CPLD combination */
wdenked247f42002-10-07 21:58:02 +0000290
291#define INTEL_ID_28F016S 0x66a066a0 /* 28F016S[VS] ID (16M = 512k x 16) */
292#define INTEL_ID_28F800B3T 0x88928892 /* 8M = 512K x 16 top boot sector */
293#define INTEL_ID_28F800B3B 0x88938893 /* 8M = 512K x 16 bottom boot sector */
294#define INTEL_ID_28F160B3T 0x88908890 /* 16M = 1M x 16 top boot sector */
295#define INTEL_ID_28F160B3B 0x88918891 /* 16M = 1M x 16 bottom boot sector */
296#define INTEL_ID_28F320B3T 0x88968896 /* 32M = 2M x 16 top boot sector */
297#define INTEL_ID_28F320B3B 0x88978897 /* 32M = 2M x 16 bottom boot sector */
298#define INTEL_ID_28F640B3T 0x88988898 /* 64M = 4M x 16 top boot sector */
299#define INTEL_ID_28F640B3B 0x88998899 /* 64M = 4M x 16 bottom boot sector */
300#define INTEL_ID_28F160F3B 0x88F488F4 /* 16M = 1M x 16 bottom boot sector */
301
302#define INTEL_ID_28F800C3T 0x88C088C0 /* 8M = 512K x 16 top boot sector */
303#define INTEL_ID_28F800C3B 0x88C188C1 /* 8M = 512K x 16 bottom boot sector */
304#define INTEL_ID_28F160C3T 0x88C288C2 /* 16M = 1M x 16 top boot sector */
305#define INTEL_ID_28F160C3B 0x88C388C3 /* 16M = 1M x 16 bottom boot sector */
306#define INTEL_ID_28F320C3T 0x88C488C4 /* 32M = 2M x 16 top boot sector */
307#define INTEL_ID_28F320C3B 0x88C588C5 /* 32M = 2M x 16 bottom boot sector */
308#define INTEL_ID_28F640C3T 0x88CC88CC /* 64M = 4M x 16 top boot sector */
309#define INTEL_ID_28F640C3B 0x88CD88CD /* 64M = 4M x 16 bottom boot sector */
310
wdenkf6e20fc2004-02-08 19:38:38 +0000311#define INTEL_ID_28F128J3 0x89188918 /* 16M = 8M x 16 x 128 */
wdenk6dd652f2003-06-19 23:40:20 +0000312#define INTEL_ID_28F320J5 0x00140014 /* 32M = 128K x 32 */
313#define INTEL_ID_28F640J5 0x00150015 /* 64M = 128K x 64 */
314#define INTEL_ID_28F320J3A 0x00160016 /* 32M = 128K x 32 */
315#define INTEL_ID_28F640J3A 0x00170017 /* 64M = 128K x 64 */
316#define INTEL_ID_28F128J3A 0x00180018 /* 128M = 128K x 128 */
Wolfgang Denk97c8d0b2005-12-22 01:50:50 +0100317#define INTEL_ID_28F256J3A 0x001D001D /* 256M = 128K x 256 */
wdenk6f213472003-08-29 22:00:43 +0000318#define INTEL_ID_28F256L18T 0x880D880D /* 256M = 128K x 255 + 32k x 4 */
wdenkb54d32b2004-06-10 21:34:36 +0000319#define INTEL_ID_28F64K3 0x88018801 /* 64M = 32K x 255 + 32k x 4 */
320#define INTEL_ID_28F128K3 0x88028802 /* 128M = 64K x 255 + 32k x 4 */
321#define INTEL_ID_28F256K3 0x88038803 /* 256M = 128K x 255 + 32k x 4 */
Stefan Roese79b4cda2006-02-28 15:29:58 +0100322#define INTEL_ID_28F64P30T 0x88178817 /* 64M = 32K x 255 + 32k x 4 */
323#define INTEL_ID_28F64P30B 0x881A881A /* 64M = 32K x 255 + 32k x 4 */
324#define INTEL_ID_28F128P30T 0x88188818 /* 128M = 64K x 255 + 32k x 4 */
325#define INTEL_ID_28F128P30B 0x881B881B /* 128M = 64K x 255 + 32k x 4 */
326#define INTEL_ID_28F256P30T 0x88198819 /* 256M = 128K x 255 + 32k x 4 */
327#define INTEL_ID_28F256P30B 0x881C881C /* 256M = 128K x 255 + 32k x 4 */
wdenked247f42002-10-07 21:58:02 +0000328
329#define INTEL_ID_28F160S3 0x00D000D0 /* 16M = 512K x 32 (64kB x 32) */
330#define INTEL_ID_28F320S3 0x00D400D4 /* 32M = 512K x 64 (64kB x 64) */
331
332/* Note that the Sharp 28F016SC is compatible with the Intel E28F016SC */
333#define SHARP_ID_28F016SCL 0xAAAAAAAA /* LH28F016SCT-L95 2Mx8, 32 64k blocks */
334#define SHARP_ID_28F016SCZ 0xA0A0A0A0 /* LH28F016SCT-Z4 2Mx8, 32 64k blocks */
335#define SHARP_ID_28F008SC 0xA6A6A6A6 /* LH28F008SCT-L12 1Mx8, 16 64k blocks */
336 /* LH28F008SCR-L85 1Mx8, 16 64k blocks */
337
wdenk2abbe072003-06-16 23:50:08 +0000338#define TOSH_ID_FVT160 0xC2 /* TC58FVT160 ID (16 M, top ) */
339#define TOSH_ID_FVB160 0x43 /* TC58FVT160 ID (16 M, bottom ) */
Holger Brunck81316a92012-08-09 10:22:41 +0200340#define NUMONYX_256MBIT 0x8922 /* Numonyx P33/30 256MBit 65nm */
wdenk608c9142003-01-13 23:54:46 +0000341
wdenked247f42002-10-07 21:58:02 +0000342/*-----------------------------------------------------------------------
343 * Internal FLASH identification codes
344 *
345 * Be careful when adding new type! Odd numbers are "bottom boot sector" types!
346 */
347
wdenk2abbe072003-06-16 23:50:08 +0000348#define FLASH_AM040 0x0001 /* AMD Am29F040B, Am29LV040B */
349 /* Bright Micro BM29F040 */
350 /* Fujitsu MBM29F040A */
351 /* STM M29W040B */
352 /* SGS Thomson M29F040B */
353 /* 8 64K x 8 uniform sectors */
wdenked247f42002-10-07 21:58:02 +0000354#define FLASH_AM400T 0x0002 /* AMD AM29LV400 */
355#define FLASH_AM400B 0x0003
356#define FLASH_AM800T 0x0004 /* AMD AM29LV800 */
357#define FLASH_AM800B 0x0005
358#define FLASH_AM116DT 0x0026 /* AMD AM29LV116DT (2Mx8bit) */
wdenk138ff602004-12-16 15:52:40 +0000359#define FLASH_AM116DB 0x0027 /* AMD AM29LV116DB (2Mx8bit) */
wdenked247f42002-10-07 21:58:02 +0000360#define FLASH_AM160T 0x0006 /* AMD AM29LV160 */
wdenk2abbe072003-06-16 23:50:08 +0000361#define FLASH_AM160LV 0x0046 /* AMD29LV160DB (2M = 2Mx8bit ) */
wdenked247f42002-10-07 21:58:02 +0000362#define FLASH_AM160B 0x0007
363#define FLASH_AM320T 0x0008 /* AMD AM29LV320 */
364#define FLASH_AM320B 0x0009
365
wdenk2abbe072003-06-16 23:50:08 +0000366#define FLASH_AM080 0x000A /* AMD Am29F080B */
367 /* 16 64K x 8 uniform sectors */
wdenk5d232d02003-05-22 22:52:13 +0000368
wdenked247f42002-10-07 21:58:02 +0000369#define FLASH_AMDL322T 0x0010 /* AMD AM29DL322 */
370#define FLASH_AMDL322B 0x0011
371#define FLASH_AMDL323T 0x0012 /* AMD AM29DL323 */
372#define FLASH_AMDL323B 0x0013
373#define FLASH_AMDL324T 0x0014 /* AMD AM29DL324 */
374#define FLASH_AMDL324B 0x0015
375
Wolfgang Denk8e6f1a82005-09-25 18:59:36 +0200376#define FLASH_AMDLV033C 0x0018
377#define FLASH_AMDLV065D 0x001A
wdenkd1cbe852003-06-28 17:24:46 +0000378
wdenked247f42002-10-07 21:58:02 +0000379#define FLASH_AMDL640 0x0016 /* AMD AM29DL640D */
380#define FLASH_AMD016 0x0018 /* AMD AM29F016D */
Wolfgang Denk8e6f1a82005-09-25 18:59:36 +0200381#define FLASH_AMDL640MB 0x0019 /* AMD AM29LV640MB (64M, bottom boot sect)*/
382#define FLASH_AMDL640MT 0x001A /* AMD AM29LV640MT (64M, top boot sect) */
wdenked247f42002-10-07 21:58:02 +0000383
384#define FLASH_SST200A 0x0040 /* SST 39xF200A ID ( 2M = 128K x 16 ) */
385#define FLASH_SST400A 0x0042 /* SST 39xF400A ID ( 4M = 256K x 16 ) */
386#define FLASH_SST800A 0x0044 /* SST 39xF800A ID ( 8M = 512K x 16 ) */
387#define FLASH_SST160A 0x0046 /* SST 39xF160A ID ( 16M = 1M x 16 ) */
stroese4d535b52004-12-16 18:01:48 +0000388#define FLASH_SST320 0x0048 /* SST 39xF160A ID ( 16M = 1M x 16 ) */
389#define FLASH_SST640 0x004A /* SST 39xF160A ID ( 16M = 1M x 16 ) */
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200390#define FLASH_SST020 0x0024 /* SST 39xF020 ID (256KB = 2Mbit x 8 ) */
wdenkd1cbe852003-06-28 17:24:46 +0000391#define FLASH_SST040 0x000E /* SST 39xF040 ID (512KB = 4Mbit x 8 ) */
wdenked247f42002-10-07 21:58:02 +0000392
393#define FLASH_STM800AB 0x0051 /* STM M29WF800AB ( 8M = 512K x 16 ) */
wdenk2abbe072003-06-16 23:50:08 +0000394#define FLASH_STMW320DT 0x0052 /* STM M29W320DT (32 M, top boot sector) */
395#define FLASH_STMW320DB 0x0053 /* STM M29W320DB (32 M, bottom boot sect)*/
wdenked247f42002-10-07 21:58:02 +0000396#define FLASH_STM320DB 0x00CB /* STM M29W320DB (4M = 64K x 64, bottom)*/
397#define FLASH_STM800DT 0x00D7 /* STM M29W800DT (1M = 64K x 16, top) */
398#define FLASH_STM800DB 0x005B /* STM M29W800DB (1M = 64K x 16, bottom)*/
399
400#define FLASH_28F400_T 0x0062 /* MT 28F400B3 ID ( 4M = 256K x 16 ) */
401#define FLASH_28F400_B 0x0063 /* MT 28F400B3 ID ( 4M = 256K x 16 ) */
402
403#define FLASH_INTEL800T 0x0074 /* INTEL 28F800B3T ( 8M = 512K x 16 ) */
404#define FLASH_INTEL800B 0x0075 /* INTEL 28F800B3B ( 8M = 512K x 16 ) */
405#define FLASH_INTEL160T 0x0076 /* INTEL 28F160B3T ( 16M = 1 M x 16 ) */
406#define FLASH_INTEL160B 0x0077 /* INTEL 28F160B3B ( 16M = 1 M x 16 ) */
407#define FLASH_INTEL320T 0x0078 /* INTEL 28F320B3T ( 32M = 2 M x 16 ) */
408#define FLASH_INTEL320B 0x0079 /* INTEL 28F320B3B ( 32M = 2 M x 16 ) */
409#define FLASH_INTEL640T 0x007A /* INTEL 28F320B3T ( 64M = 4 M x 16 ) */
410#define FLASH_INTEL640B 0x007B /* INTEL 28F320B3B ( 64M = 4 M x 16 ) */
411
wdenked247f42002-10-07 21:58:02 +0000412#define FLASH_28F008S5 0x0080 /* Intel 28F008S5 ( 1M = 64K x 16 ) */
413#define FLASH_28F016SV 0x0081 /* Intel 28F016SV ( 16M = 512k x 32 ) */
414#define FLASH_28F800_B 0x0083 /* Intel E28F800B ( 1M = ? ) */
wdenk2abbe072003-06-16 23:50:08 +0000415#define FLASH_AM29F800B 0x0084 /* AMD Am29F800BB ( 1M = ? ) */
wdenked247f42002-10-07 21:58:02 +0000416#define FLASH_28F320J5 0x0085 /* Intel 28F320J5 ( 4M = 128K x 32 ) */
417#define FLASH_28F160S3 0x0086 /* Intel 28F160S3 ( 16M = 512K x 32 ) */
418#define FLASH_28F320S3 0x0088 /* Intel 28F320S3 ( 32M = 512K x 64 ) */
419#define FLASH_AM640U 0x0090 /* AMD Am29LV640U ( 64M = 4M x 16 ) */
420#define FLASH_AM033C 0x0091 /* AMD AM29LV033 ( 32M = 4M x 8 ) */
wdenk2abbe072003-06-16 23:50:08 +0000421#define FLASH_LH28F016SCT 0x0092 /* Sharp 28F016SCT ( 8 Meg Flash SIMM ) */
422#define FLASH_28F160F3B 0x0093 /* Intel 28F160F3B ( 16M = 1M x 16 ) */
Wolfgang Denk8e6f1a82005-09-25 18:59:36 +0200423#define FLASH_AM065D 0x0093
wdenked247f42002-10-07 21:58:02 +0000424
wdenk2abbe072003-06-16 23:50:08 +0000425#define FLASH_28F640J5 0x0099 /* INTEL 28F640J5 ( 64M = 128K x 64) */
wdenked247f42002-10-07 21:58:02 +0000426
wdenk2abbe072003-06-16 23:50:08 +0000427#define FLASH_28F800C3T 0x009A /* Intel 28F800C3T ( 8M = 512K x 16 ) */
428#define FLASH_28F800C3B 0x009B /* Intel 28F800C3B ( 8M = 512K x 16 ) */
429#define FLASH_28F160C3T 0x009C /* Intel 28F160C3T ( 16M = 1M x 16 ) */
430#define FLASH_28F160C3B 0x009D /* Intel 28F160C3B ( 16M = 1M x 16 ) */
431#define FLASH_28F320C3T 0x009E /* Intel 28F320C3T ( 32M = 2M x 16 ) */
432#define FLASH_28F320C3B 0x009F /* Intel 28F320C3B ( 32M = 2M x 16 ) */
433#define FLASH_28F640C3T 0x00A0 /* Intel 28F640C3T ( 64M = 4M x 16 ) */
434#define FLASH_28F640C3B 0x00A1 /* Intel 28F640C3B ( 64M = 4M x 16 ) */
Wolfgang Denk8e6f1a82005-09-25 18:59:36 +0200435#define FLASH_AMLV320U 0x00A2 /* AMD 29LV320M ( 32M = 2M x 16 ) */
436
437#define FLASH_AM033 0x00A3 /* AMD AmL033C90V1 (32M = 4M x 8) */
438#define FLASH_AM065 0x0093 /* AMD AmL065DU12RI (64M = 8M x 8) */
439#define FLASH_AT040 0x00A5 /* Amtel AT49LV040 (4M = 512K x 8) */
440
441#define FLASH_AMLV640U 0x00A4 /* AMD 29LV640M ( 64M = 4M x 16 ) */
wdenkf12e5682003-07-07 20:07:54 +0000442#define FLASH_AMLV128U 0x00A6 /* AMD 29LV128M ( 128M = 8M x 16 ) */
Wolfgang Denk8e6f1a82005-09-25 18:59:36 +0200443#define FLASH_AMLV320B 0x00A7 /* AMD 29LV320MB ( 32M = 2M x 16 ) */
wdenkd4ca31c2004-01-02 14:00:00 +0000444#define FLASH_AMLV320T 0x00A8 /* AMD 29LV320MT ( 32M = 2M x 16 ) */
wdenk4d13cba2004-03-14 14:09:05 +0000445#define FLASH_AMLV256U 0x00AA /* AMD 29LV256M ( 256M = 16M x 16 ) */
Wolfgang Denk8e6f1a82005-09-25 18:59:36 +0200446#define FLASH_MXLV320B 0x00AB /* MX 29LV320MB ( 32M = 2M x 16 ) */
wdenkefa329c2004-03-23 20:18:25 +0000447#define FLASH_MXLV320T 0x00AC /* MX 29LV320MT ( 32M = 2M x 16 ) */
wdenkb54d32b2004-06-10 21:34:36 +0000448#define FLASH_28F256L18T 0x00B0 /* Intel 28F256L18T 256M = 128K x 255 + 32k x 4 */
wdenkd4ca31c2004-01-02 14:00:00 +0000449#define FLASH_AMDL163T 0x00B2 /* AMD AM29DL163T (2M x 16 ) */
450#define FLASH_AMDL163B 0x00B3
wdenkb54d32b2004-06-10 21:34:36 +0000451#define FLASH_28F64K3 0x00B4 /* Intel 28F64K3 ( 64M) */
Wolfgang Denk8e6f1a82005-09-25 18:59:36 +0200452#define FLASH_28F128K3 0x00B6 /* Intel 28F128K3 ( 128M = 8M x 16 ) */
453#define FLASH_28F256K3 0x00B8 /* Intel 28F256K3 ( 256M = 16M x 16 ) */
wdenked247f42002-10-07 21:58:02 +0000454
wdenkb54d32b2004-06-10 21:34:36 +0000455#define FLASH_28F320J3A 0x00C0 /* INTEL 28F320J3A ( 32M = 128K x 32) */
456#define FLASH_28F640J3A 0x00C2 /* INTEL 28F640J3A ( 64M = 128K x 64) */
457#define FLASH_28F128J3A 0x00C4 /* INTEL 28F128J3A (128M = 128K x 128) */
Wolfgang Denk97c8d0b2005-12-22 01:50:50 +0100458#define FLASH_28F256J3A 0x00C6 /* INTEL 28F256J3A (256M = 128K x 256) */
wdenkbf9e3b32004-02-12 00:47:09 +0000459
wdenkb54d32b2004-06-10 21:34:36 +0000460#define FLASH_FUJLV650 0x00D0 /* Fujitsu MBM 29LV650UE/651UE */
Wolfgang Denk8e6f1a82005-09-25 18:59:36 +0200461#define FLASH_MT28S4M16LC 0x00E1 /* Micron MT28S4M16LC */
wdenk9d5028c2004-11-21 00:06:33 +0000462#define FLASH_S29GL064M 0x00F0 /* Spansion S29GL064M-R6 */
Marian Balakowicz72997122006-10-03 20:28:38 +0200463#define FLASH_S29GL128N 0x00F1 /* Spansion S29GL128N */
wdenkb54d32b2004-06-10 21:34:36 +0000464
rev13@wp.pleaaa4f72015-03-01 12:44:40 +0100465#define FLASH_STM32F4 0x00F2 /* STM32F4 Embedded Flash */
Matt Porter2d18ef22015-05-05 15:00:24 -0400466#define FLASH_STM32F1 0x00F3 /* STM32F1 Embedded Flash */
rev13@wp.pleaaa4f72015-03-01 12:44:40 +0100467
wdenked247f42002-10-07 21:58:02 +0000468#define FLASH_UNKNOWN 0xFFFF /* unknown flash type */
469
470
471/* manufacturer offsets
472 */
473#define FLASH_MAN_AMD 0x00000000 /* AMD */
474#define FLASH_MAN_FUJ 0x00010000 /* Fujitsu */
475#define FLASH_MAN_BM 0x00020000 /* Bright Microelectronics */
476#define FLASH_MAN_MX 0x00030000 /* MXIC */
477#define FLASH_MAN_STM 0x00040000
wdenk2abbe072003-06-16 23:50:08 +0000478#define FLASH_MAN_TOSH 0x00050000 /* Toshiba */
Wolfgang Denk8e6f1a82005-09-25 18:59:36 +0200479#define FLASH_MAN_EXCEL 0x00060000 /* Excel Semiconductor */
wdenked247f42002-10-07 21:58:02 +0000480#define FLASH_MAN_SST 0x00100000
wdenk2abbe072003-06-16 23:50:08 +0000481#define FLASH_MAN_INTEL 0x00300000
wdenked247f42002-10-07 21:58:02 +0000482#define FLASH_MAN_MT 0x00400000
wdenk2abbe072003-06-16 23:50:08 +0000483#define FLASH_MAN_SHARP 0x00500000
Wolfgang Denk8e6f1a82005-09-25 18:59:36 +0200484#define FLASH_MAN_ATM 0x00600000
Stefan Roese260421a2006-11-13 13:55:24 +0100485#define FLASH_MAN_CFI 0x01000000
wdenked247f42002-10-07 21:58:02 +0000486
487
wdenk2abbe072003-06-16 23:50:08 +0000488#define FLASH_TYPEMASK 0x0000FFFF /* extract FLASH type information */
wdenked247f42002-10-07 21:58:02 +0000489#define FLASH_VENDMASK 0xFFFF0000 /* extract FLASH vendor information */
490
491#define FLASH_AMD_COMP 0x000FFFFF /* Up to this ID, FLASH is compatible */
492 /* with AMD, Fujitsu and SST */
493 /* (JEDEC standard commands ?) */
494
495#define FLASH_BTYPE 0x0001 /* mask for bottom boot sector type */
496
497/*-----------------------------------------------------------------------
498 * Timeout constants:
499 *
500 * We can't find any specifications for maximum chip erase times,
501 * so these values are guestimates.
502 */
503#define FLASH_ERASE_TIMEOUT 120000 /* timeout for erasing in ms */
504#define FLASH_WRITE_TIMEOUT 500 /* timeout for writes in ms */
505
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200506#endif /* !CONFIG_SYS_NO_FLASH */
wdenked247f42002-10-07 21:58:02 +0000507
508#endif /* _FLASH_H_ */