| Ricardo Ribalda Delgado | d865fd0 | 2008-07-17 11:44:12 +0200 | [diff] [blame^] | 1 | /* |
| 2 | * (C) Copyright 2008 |
| 3 | * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es |
| 4 | * This work has been supported by: QTechnology http://qtec.com/ |
| 5 | * Based on interrupts.c Wolfgang Denk-DENX Software Engineering-wd@denx.de |
| 6 | * This program is free software: you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation, either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | #ifndef XILINX_IRQ_H |
| 20 | #define XILINX_IRQ_H |
| 21 | |
| 22 | #define intc XPAR_INTC_0_BASEADDR |
| 23 | #define ISR (intc+(0*4)) /* Interrupt Status Register */ |
| 24 | #define IPR (intc+(1*4)) /* Interrupt Pending Register */ |
| 25 | #define IER (intc+(2*4)) /* Interrupt Enable Register */ |
| 26 | #define IAR (intc+(3*4)) /* Interrupt Acknowledge Register */ |
| 27 | #define SIE (intc+(4*4)) /* Set Interrupt Enable bits */ |
| 28 | #define CIE (intc+(5*4)) /* Clear Interrupt Enable bits */ |
| 29 | #define IVR (intc+(6*4)) /* Interrupt Vector Register */ |
| 30 | #define MER (intc+(7*4)) /* Master Enable Register */ |
| 31 | |
| 32 | #define IRQ_MASK(irq) (1<<(irq&0x1f)) |
| 33 | |
| 34 | #define IRQ_MAX XPAR_INTC_MAX_NUM_INTR_INPUTS |
| 35 | |
| 36 | #endif |