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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Matt Waddel23b93e12011-04-16 11:54:07 +00002/*
3 * ARM PrimeCell MultiMedia Card Interface - PL180
4 *
5 * Copyright (C) ST-Ericsson SA 2010
6 *
7 * Author: Ulf Hansson <ulf.hansson@stericsson.com>
8 * Author: Martin Lundholm <martin.xa.lundholm@stericsson.com>
9 * Ported to drivers/mmc/ by: Matt Waddel <matt.waddel@linaro.org>
Matt Waddel23b93e12011-04-16 11:54:07 +000010 */
11
12#ifndef __ARM_PL180_MMCI_H__
13#define __ARM_PL180_MMCI_H__
14
Pantelis Antoniou93bfd612014-03-11 19:34:20 +020015/* need definition of struct mmc_config */
16#include <mmc.h>
17
Matt Waddel23b93e12011-04-16 11:54:07 +000018#define COMMAND_REG_DELAY 300
19#define DATA_REG_DELAY 1000
20#define CLK_CHANGE_DELAY 2000
21
22#define INIT_PWR 0xBF /* Power on, full power, not open drain */
23#define ARM_MCLK (100*1000*1000)
24
25/* SDI Power Control register bits */
26#define SDI_PWR_PWRCTRL_MASK 0x00000003
27#define SDI_PWR_PWRCTRL_ON 0x00000003
28#define SDI_PWR_PWRCTRL_OFF 0x00000000
29#define SDI_PWR_DAT2DIREN 0x00000004
30#define SDI_PWR_CMDDIREN 0x00000008
31#define SDI_PWR_DAT0DIREN 0x00000010
32#define SDI_PWR_DAT31DIREN 0x00000020
33#define SDI_PWR_OPD 0x00000040
34#define SDI_PWR_FBCLKEN 0x00000080
35#define SDI_PWR_DAT74DIREN 0x00000100
36#define SDI_PWR_RSTEN 0x00000200
37
38#define VOLTAGE_WINDOW_MMC 0x00FF8080
39#define VOLTAGE_WINDOW_SD 0x80010000
40
41/* SDI clock control register bits */
42#define SDI_CLKCR_CLKDIV_MASK 0x000000FF
43#define SDI_CLKCR_CLKEN 0x00000100
44#define SDI_CLKCR_PWRSAV 0x00000200
45#define SDI_CLKCR_BYPASS 0x00000400
46#define SDI_CLKCR_WIDBUS_MASK 0x00001800
47#define SDI_CLKCR_WIDBUS_1 0x00000000
48#define SDI_CLKCR_WIDBUS_4 0x00000800
John Rigby10ed93d2012-07-31 08:59:31 +000049/* V2 only */
50#define SDI_CLKCR_WIDBUS_8 0x00001000
51#define SDI_CLKCR_NEDGE 0x00002000
52#define SDI_CLKCR_HWFC_EN 0x00004000
Matt Waddel23b93e12011-04-16 11:54:07 +000053
John Rigby10ed93d2012-07-31 08:59:31 +000054#define SDI_CLKCR_CLKDIV_INIT_V1 0x000000C6 /* MCLK/(2*(0xC6+1)) => 505KHz */
55#define SDI_CLKCR_CLKDIV_INIT_V2 0x000000FD
Matt Waddel23b93e12011-04-16 11:54:07 +000056
57/* SDI command register bits */
58#define SDI_CMD_CMDINDEX_MASK 0x000000FF
59#define SDI_CMD_WAITRESP 0x00000040
60#define SDI_CMD_LONGRESP 0x00000080
61#define SDI_CMD_WAITINT 0x00000100
62#define SDI_CMD_WAITPEND 0x00000200
63#define SDI_CMD_CPSMEN 0x00000400
64#define SDI_CMD_SDIOSUSPEND 0x00000800
65#define SDI_CMD_ENDCMDCOMPL 0x00001000
66#define SDI_CMD_NIEN 0x00002000
67#define SDI_CMD_CE_ATACMD 0x00004000
68#define SDI_CMD_CBOOTMODEEN 0x00008000
69
70#define SDI_DTIMER_DEFAULT 0xFFFF0000
71
72/* SDI Status register bits */
73#define SDI_STA_CCRCFAIL 0x00000001
74#define SDI_STA_DCRCFAIL 0x00000002
75#define SDI_STA_CTIMEOUT 0x00000004
76#define SDI_STA_DTIMEOUT 0x00000008
77#define SDI_STA_TXUNDERR 0x00000010
78#define SDI_STA_RXOVERR 0x00000020
79#define SDI_STA_CMDREND 0x00000040
80#define SDI_STA_CMDSENT 0x00000080
81#define SDI_STA_DATAEND 0x00000100
82#define SDI_STA_STBITERR 0x00000200
83#define SDI_STA_DBCKEND 0x00000400
84#define SDI_STA_CMDACT 0x00000800
85#define SDI_STA_TXACT 0x00001000
86#define SDI_STA_RXACT 0x00002000
87#define SDI_STA_TXFIFOBW 0x00004000
88#define SDI_STA_RXFIFOBR 0x00008000
89#define SDI_STA_TXFIFOF 0x00010000
90#define SDI_STA_RXFIFOF 0x00020000
91#define SDI_STA_TXFIFOE 0x00040000
92#define SDI_STA_RXFIFOE 0x00080000
93#define SDI_STA_TXDAVL 0x00100000
94#define SDI_STA_RXDAVL 0x00200000
95#define SDI_STA_SDIOIT 0x00400000
96#define SDI_STA_CEATAEND 0x00800000
97#define SDI_STA_CARDBUSY 0x01000000
98#define SDI_STA_BOOTMODE 0x02000000
99#define SDI_STA_BOOTACKERR 0x04000000
100#define SDI_STA_BOOTACKTIMEOUT 0x08000000
101#define SDI_STA_RSTNEND 0x10000000
102
103/* SDI Interrupt Clear register bits */
104#define SDI_ICR_MASK 0x1DC007FF
105#define SDI_ICR_CCRCFAILC 0x00000001
106#define SDI_ICR_DCRCFAILC 0x00000002
107#define SDI_ICR_CTIMEOUTC 0x00000004
108#define SDI_ICR_DTIMEOUTC 0x00000008
109#define SDI_ICR_TXUNDERRC 0x00000010
110#define SDI_ICR_RXOVERRC 0x00000020
111#define SDI_ICR_CMDRENDC 0x00000040
112#define SDI_ICR_CMDSENTC 0x00000080
113#define SDI_ICR_DATAENDC 0x00000100
114#define SDI_ICR_STBITERRC 0x00000200
115#define SDI_ICR_DBCKENDC 0x00000400
116#define SDI_ICR_SDIOITC 0x00400000
117#define SDI_ICR_CEATAENDC 0x00800000
118#define SDI_ICR_BUSYENDC 0x01000000
119#define SDI_ICR_BOOTACKERRC 0x04000000
120#define SDI_ICR_BOOTACKTIMEOUTC 0x08000000
121#define SDI_ICR_RSTNENDC 0x10000000
122
123#define SDI_MASK0_MASK 0x1FFFFFFF
124
125/* SDI Data control register bits */
126#define SDI_DCTRL_DTEN 0x00000001
127#define SDI_DCTRL_DTDIR_IN 0x00000002
128#define SDI_DCTRL_DTMODE_STREAM 0x00000004
129#define SDI_DCTRL_DMAEN 0x00000008
130#define SDI_DCTRL_DBLKSIZE_MASK 0x000000F0
131#define SDI_DCTRL_RWSTART 0x00000100
132#define SDI_DCTRL_RWSTOP 0x00000200
133#define SDI_DCTRL_RWMOD 0x00000200
134#define SDI_DCTRL_SDIOEN 0x00000800
135#define SDI_DCTRL_DMAREQCTL 0x00001000
136#define SDI_DCTRL_DBOOTMODEEN 0x00002000
137#define SDI_DCTRL_BUSYMODE 0x00004000
138#define SDI_DCTRL_DDR_MODE 0x00008000
John Rigby10ed93d2012-07-31 08:59:31 +0000139#define SDI_DCTRL_DBLOCKSIZE_V2_MASK 0x7fff0000
140#define SDI_DCTRL_DBLOCKSIZE_V2_SHIFT 16
Matt Waddel23b93e12011-04-16 11:54:07 +0000141
142#define SDI_FIFO_BURST_SIZE 8
143
Patrice Chotard6f41d1a2018-12-05 14:04:32 +0100144#define STM32_MMCI_ID 0x00880180
Stephan Gerholdd890f232021-07-06 16:54:36 +0200145#define UX500V2_MMCI_ID 0x10480180
Patrice Chotard3c0dbed2017-10-23 10:57:31 +0200146
Matt Waddel23b93e12011-04-16 11:54:07 +0000147struct sdi_registers {
148 u32 power; /* 0x00*/
149 u32 clock; /* 0x04*/
150 u32 argument; /* 0x08*/
151 u32 command; /* 0x0c*/
152 u32 respcommand; /* 0x10*/
153 u32 response0; /* 0x14*/
154 u32 response1; /* 0x18*/
155 u32 response2; /* 0x1c*/
156 u32 response3; /* 0x20*/
157 u32 datatimer; /* 0x24*/
158 u32 datalength; /* 0x28*/
159 u32 datactrl; /* 0x2c*/
160 u32 datacount; /* 0x30*/
161 u32 status; /* 0x34*/
162 u32 status_clear; /* 0x38*/
163 u32 mask0; /* 0x3c*/
164 u32 mask1; /* 0x40*/
165 u32 card_select; /* 0x44*/
166 u32 fifo_count; /* 0x48*/
167 u32 padding1[(0x80-0x4C)>>2];
168 u32 fifo; /* 0x80*/
169 u32 padding2[(0xFE0-0x84)>>2];
170 u32 periph_id0; /* 0xFE0 mmc Peripheral Identifcation Register*/
171 u32 periph_id1; /* 0xFE4*/
172 u32 periph_id2; /* 0xFE8*/
173 u32 periph_id3; /* 0xFEC*/
174 u32 pcell_id0; /* 0xFF0*/
175 u32 pcell_id1; /* 0xFF4*/
176 u32 pcell_id2; /* 0xFF8*/
177 u32 pcell_id3; /* 0xFFC*/
178};
179
John Rigby10ed93d2012-07-31 08:59:31 +0000180struct pl180_mmc_host {
181 struct sdi_registers *base;
182 char name[32];
183 unsigned int b_max;
184 unsigned int voltages;
185 unsigned int caps;
186 unsigned int clock_in;
187 unsigned int clock_min;
188 unsigned int clock_max;
189 unsigned int clkdiv_init;
190 unsigned int pwr_init;
191 int version2;
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200192 struct mmc_config cfg;
Patrice Chotard5829fe22017-10-23 10:57:34 +0200193#ifdef CONFIG_DM_MMC
194 struct gpio_desc cd_gpio;
Patrice Chotard5829fe22017-10-23 10:57:34 +0200195#endif
John Rigby10ed93d2012-07-31 08:59:31 +0000196};
197
Patrice Chotardcb0060e2017-10-23 10:57:30 +0200198int arm_pl180_mmci_init(struct pl180_mmc_host *host, struct mmc **mmc);
John Rigby10ed93d2012-07-31 08:59:31 +0000199
Matt Waddel23b93e12011-04-16 11:54:07 +0000200#endif