blob: 41b779c5ca9ba44d74f0ae0c015d426dc490e8ef [file] [log] [blame]
Dinh Nguyen77754402012-10-04 06:46:02 +00001#
2# (C) Copyright 2000-2003
3# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4#
Ley Foon Tand89e9792017-04-26 02:44:48 +08005# Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
Dinh Nguyen77754402012-10-04 06:46:02 +00006#
Wolfgang Denk1a459662013-07-08 09:37:19 +02007# SPDX-License-Identifier: GPL-2.0+
Dinh Nguyen77754402012-10-04 06:46:02 +00008#
9
Ley Foon Tand89e9792017-04-26 02:44:48 +080010obj-y += board.o
11obj-y += clock_manager.o
12obj-y += fpga_manager.o
13obj-y += misc.o
14obj-y += reset_manager.o
15obj-y += timer.o
Dinh Nguyene5ad7d92015-12-02 13:31:32 -060016
Ley Foon Tand89e9792017-04-26 02:44:48 +080017ifdef CONFIG_TARGET_SOCFPGA_GEN5
18obj-y += clock_manager_gen5.o
19obj-y += misc_gen5.o
20obj-y += reset_manager_gen5.o
21obj-y += scan_manager.o
22obj-y += system_manager_gen5.o
23obj-y += wrap_pll_config.o
24endif
Ley Foon Tan827e6a72017-04-26 02:44:38 +080025
Ley Foon Tand89e9792017-04-26 02:44:48 +080026ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
27obj-y += clock_manager_arria10.o
28obj-y += misc_arria10.o
29obj-y += pinmux_arria10.o
30obj-y += reset_manager_arria10.o
31endif
Marek Vasutca62d2e2015-08-02 21:12:09 +020032
Ley Foon Tand89e9792017-04-26 02:44:48 +080033ifdef CONFIG_SPL_BUILD
34obj-y += spl.o
35ifdef CONFIG_TARGET_SOCFPGA_GEN5
36obj-y += freeze_controller.o
37obj-y += wrap_iocsr_config.o
38obj-y += wrap_pinmux_config.o
39obj-y += wrap_sdram_config.o
40endif
41endif
42
43ifdef CONFIG_TARGET_SOCFPGA_GEN5
Marek Vasutca62d2e2015-08-02 21:12:09 +020044# QTS-generated config file wrappers
Marek Vasutca62d2e2015-08-02 21:12:09 +020045CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR)
46CFLAGS_wrap_pinmux_config.o += -I$(srctree)/board/$(BOARDDIR)
47CFLAGS_wrap_pll_config.o += -I$(srctree)/board/$(BOARDDIR)
48CFLAGS_wrap_sdram_config.o += -I$(srctree)/board/$(BOARDDIR)
Ley Foon Tand89e9792017-04-26 02:44:48 +080049endif