blob: 757b63c256658fad35a68ba7dd8bec5dbce851d4 [file] [log] [blame]
Matthias Kaehlckecf3c1422010-02-01 21:29:48 +01001/*
2 * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
3 *
4 * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <config.h>
26#include <asm/arch/ep93xx.h>
27
28#define SDRAM_BASE_ADDR PHYS_SDRAM_1
29
30#ifdef CONFIG_EDB93XX_SDCS0
31#define SDRAM_DEVCFG_REG devcfg0
32#elif defined(CONFIG_EDB93XX_SDCS3)
33#define SDRAM_DEVCFG_REG devcfg3
34#else
35#error "SDRAM bank configuration"
36#endif
37
38#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) || \
39 defined(CONFIG_EDB9302A)
40/*
41 * 1x Samsung K4S561632C-TC/L75 4M x 16bit x 4 banks SDRAM
42 *
43 * CLK cycle time min:
44 * @ CAS latency = 3: 7.5ns
45 * @ CAS latency = 2: 10ns
46 * We're running at 66MHz (15ns cycle time) external bus speed (HCLK),
47 * so it's safe to use CAS latency = 2
48 *
49 * RAS-to-CAS delay min:
50 * 20ns
51 * At 15ns cycle time, we use RAS-to-CAS delay = 2
52 *
53 * SROMLL = 1: Swap BA[1:0] with A[13:12], making the SDRAM appear
54 * as four blocks of 8MB size, instead of eight blocks of 4MB size:
55 *
56 * EDB9301/EDB9302:
57 *
58 * 0x00000000 - 0x007fffff
59 * 0x01000000 - 0x017fffff
60 * 0x04000000 - 0x047fffff
61 * 0x05000000 - 0x057fffff
62 *
63 *
64 * EDB9302a:
65 *
66 * 0xc0000000 - 0xc07fffff
67 * 0xc1000000 - 0xc17fffff
68 * 0xc4000000 - 0xc47fffff
69 * 0xc5000000 - 0xc57fffff
70 *
71 * BANKCOUNT = 1: This is a device with four banks
72 */
73
74#define SDRAM_DEVCFG_VAL (SDRAM_DEVCFG_BANKCOUNT | \
75 SDRAM_DEVCFG_SROMLL | \
76 SDRAM_DEVCFG_CASLAT_2 | \
77 SDRAM_DEVCFG_RASTOCAS_2 | \
78 SDRAM_DEVCFG_EXTBUSWIDTH)
79
80/*
81 * 16 bit ext. bus
82 *
83 * A[22:09] is output as SYA[13:0]
84 * CAS latency: 2
85 * Burst type: sequential
86 * Burst length: 8 (required for 16 bit ext. bus)
87 * SYA[13:0] = 0x0023
88 */
89#define SDRAM_MODE_REG_VAL 0x4600
90
91#define SDRAM_BANK_SEL_0 0x00000000 /* A[22:21] = b00 */
92#define SDRAM_BANK_SEL_1 0x00200000 /* A[22:21] = b01 */
93#define SDRAM_BANK_SEL_2 0x00400000 /* A[22:21] = b10 */
94#define SDRAM_BANK_SEL_3 0x00600000 /* A[22:21] = b11 */
95
96#elif defined(CONFIG_EDB9307) || defined(CONFIG_EDB9307A) || \
97 defined CONFIG_EDB9312 || defined(CONFIG_EDB9315) || \
98 defined(CONFIG_EDB9315A)
99/*
100 * 2x Samsung K4S561632C-TC/L75 4M x 16bit x 4 banks SDRAM
101 *
102 * CLK cycle time min:
103 * @ CAS latency = 3: 7.5ns
104 * @ CAS latency = 2: 10ns
105 * We're running at 100MHz (10ns cycle time) external bus speed (HCLK),
106 * so it's safe to use CAS latency = 2
107 *
108 * RAS-to-CAS delay min:
109 * 20ns
110 * At 10ns cycle time, we use RAS-to-CAS delay = 2
111 *
112 * EDB9307, EDB9312, EDB9315:
113 *
114 * 0x00000000 - 0x01ffffff
115 * 0x04000000 - 0x05ffffff
116 *
117 *
118 * EDB9307a, EDB9315a:
119 *
120 * 0xc0000000 - 0xc1ffffff
121 * 0xc4000000 - 0xc5ffffff
122 */
123
124#define SDRAM_DEVCFG_VAL (SDRAM_DEVCFG_BANKCOUNT | \
125 SDRAM_DEVCFG_SROMLL | \
126 SDRAM_DEVCFG_CASLAT_2 | \
127 SDRAM_DEVCFG_RASTOCAS_2)
128
129/*
130 * 32 bit ext. bus
131 *
132 * A[23:10] is output as SYA[13:0]
133 * CAS latency: 2
134 * Burst type: sequential
135 * Burst length: 4
136 * SYA[13:0] = 0x0022
137 */
138#define SDRAM_MODE_REG_VAL 0x8800
139
140#define SDRAM_BANK_SEL_0 0x00000000 /* A[23:22] = b00 */
141#define SDRAM_BANK_SEL_1 0x00400000 /* A[23:22] = b01 */
142#define SDRAM_BANK_SEL_2 0x00800000 /* A[23:22] = b10 */
143#define SDRAM_BANK_SEL_3 0x00c00000 /* A[23:22] = b11 */
144#endif