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wdenk945af8d2003-07-16 21:53:01 +00001/*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27/*
28 * High Level Configuration Options
29 * (easy to change)
30 */
31
32#define CONFIG_MPC5XXX 1 /* This is an MPC5xxx CPU */
33#define CONFIG_ICECUBE 1 /* ... on IceCube board */
34
35#define CFG_MPC5XXX_CLKIN 33333333 /* ... running at 33MHz */
36
37#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
38#define BOOTFLAG_WARM 0x02 /* Software reboot */
39
wdenk96e48cf2003-08-05 18:22:44 +000040#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
wdenk945af8d2003-07-16 21:53:01 +000041#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
42# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
43#endif
44
45/*
46 * Serial console configuration
47 */
48#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
49#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
50#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
51
wdenk96e48cf2003-08-05 18:22:44 +000052
53#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */
54/*
55 * PCI Mapping:
56 * 0x40000000 - 0x4fffffff - PCI Memory
57 * 0x50000000 - 0x50ffffff - PCI IO Space
58 */
59#define CONFIG_PCI 1
60#define CONFIG_PCI_PNP 1
61#define CONFIG_PCI_SCAN_SHOW 1
62
63#define CONFIG_PCI_MEM_BUS 0x40000000
64#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
65#define CONFIG_PCI_MEM_SIZE 0x10000000
66
67#define CONFIG_PCI_IO_BUS 0x50000000
68#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
69#define CONFIG_PCI_IO_SIZE 0x01000000
70
71#define CONFIG_NET_MULTI 1
72#define CONFIG_EEPRO100 1
73#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
74
75#define ADD_PCI_CMD CFG_CMD_PCI
76
77#else /* MPC5100 */
78
79#define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */
80
81#endif
82
wdenk945af8d2003-07-16 21:53:01 +000083/*
84 * Supported commands
85 */
wdenk96e48cf2003-08-05 18:22:44 +000086#define CONFIG_COMMANDS (CONFIG_CMD_DFL | ADD_PCI_CMD)
wdenk945af8d2003-07-16 21:53:01 +000087
88/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
89#include <cmd_confdefs.h>
90
91/*
92 * Autobooting
93 */
94#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
95#define CONFIG_BOOTCOMMAND "bootm 100000" /* autoboot command */
96#define CONFIG_BOOTARGS "root=/dev/ram rw"
97
98/*
99 * I2C configuration
100 */
101
102/*
103 * Flash configuration
104 */
105#define CFG_FLASH_BASE 0xff800000
106#define CFG_FLASH_SIZE 0x00800000
107
108/*
109 * Flash organization
110 */
111#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
112#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
113
114#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
115#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
116
wdenk96e48cf2003-08-05 18:22:44 +0000117#undef CONFIG_FLASH_16BIT /* Flash is 8-bit */
wdenk945af8d2003-07-16 21:53:01 +0000118
119
120/*
121 * Environment settings
122 */
wdenk96e48cf2003-08-05 18:22:44 +0000123#define CFG_ENV_IS_IN_FLASH 1
wdenk945af8d2003-07-16 21:53:01 +0000124#define CFG_ENV_SIZE 0x10000
wdenk96e48cf2003-08-05 18:22:44 +0000125#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x740000)
126#define CFG_ENV_SECT_SIZE 0x10000
127#define CONFIG_ENV_OVERWRITE 1
wdenk945af8d2003-07-16 21:53:01 +0000128
129/*
130 * Memory map
131 */
132#define CFG_MBAR 0xf0000000
133#define CFG_SDRAM_BASE 0x00000000
wdenke0ac62d2003-08-17 18:55:18 +0000134#define CFG_DEFAULT_MBAR 0x80000000
wdenk945af8d2003-07-16 21:53:01 +0000135
136/* Use SRAM until RAM will be available */
137#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
138#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
139
140
141#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
142#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
143#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
144
145#define CFG_MONITOR_BASE TEXT_BASE
146#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
wdenk96e48cf2003-08-05 18:22:44 +0000147# define CFG_RAMBOOT 1
wdenk945af8d2003-07-16 21:53:01 +0000148#endif
149
150#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
151#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
152#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
153
154/*
155 * Ethernet configuration
156 */
wdenk945af8d2003-07-16 21:53:01 +0000157#define CONFIG_MPC5XXX_FEC 1
wdenk945af8d2003-07-16 21:53:01 +0000158
159/*
160 * GPIO configuration
161 */
162#define CFG_GPS_PORT_CONFIG 0x00000004
163
164/*
165 * Miscellaneous configurable options
166 */
167#define CFG_LONGHELP /* undef to save memory */
168#define CFG_PROMPT "=> " /* Monitor Command Prompt */
169#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
170#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
171#else
172#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
173#endif
174#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
175#define CFG_MAXARGS 16 /* max number of command args */
176#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
177
178#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
179#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
180
181#define CFG_LOAD_ADDR 0x100000 /* default load address */
182
183#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
184
185/*
186 * Various low-level settings
187 */
188#define CFG_HID0_INIT 0
189#define CFG_HID0_FINAL 0
190
191#define CFG_BOOTCS_START CFG_FLASH_BASE
192#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
193#define CFG_BOOTCS_CFG 0x00047801
194#define CFG_CS0_START CFG_FLASH_BASE
195#define CFG_CS0_SIZE CFG_FLASH_SIZE
196
197#define CFG_CS_BURST 0x00000000
198#define CFG_CS_DEADCYCLE 0x33333333
199
200#define CFG_RESET_ADDRESS 0xff000000
201
202#endif /* __CONFIG_H */