blob: 520f7f7325746484cf4c19936ea1202485de5fd0 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +09002/*
Robert P. J. Day1cc0a9f2016-05-04 04:47:31 -04003 * sh_eth.h - Driver for Renesas SuperH ethernet controller.
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +09004 *
Nobuhiro Iwamatsudcd5a592012-08-02 22:08:40 +00005 * Copyright (C) 2008 - 2012 Renesas Solutions Corp.
6 * Copyright (c) 2008 - 2012 Nobuhiro Iwamatsu
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +09007 * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +09008 */
9
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +090010#include <netdev.h>
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +090011#include <asm/types.h>
12
13#define SHETHER_NAME "sh_eth"
14
Nobuhiro Iwamatsudcd5a592012-08-02 22:08:40 +000015#if defined(CONFIG_SH)
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +090016/* Malloc returns addresses in the P1 area (cacheable). However we need to
17 use area P2 (non-cacheable) */
Marek Vasut7234a282019-07-31 14:48:17 +020018#define ADDR_TO_P2(addr) ((((uintptr_t)(addr) & ~0xe0000000) | 0xa0000000))
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +090019
20/* The ethernet controller needs to use physical addresses */
Marek Vasut7234a282019-07-31 14:48:17 +020021#define ADDR_TO_PHY(addr) ((uintptr_t)(addr) & ~0xe0000000)
Nobuhiro Iwamatsudcd5a592012-08-02 22:08:40 +000022#elif defined(CONFIG_ARM)
Chris Brandt5ad565b2017-11-03 08:30:11 -050023#ifndef inl
24#define inl readl
Nobuhiro Iwamatsudcd5a592012-08-02 22:08:40 +000025#define outl writel
Chris Brandt5ad565b2017-11-03 08:30:11 -050026#endif
Marek Vasut7234a282019-07-31 14:48:17 +020027#define ADDR_TO_PHY(addr) ((uintptr_t)(addr))
Nobuhiro Iwamatsudcd5a592012-08-02 22:08:40 +000028#define ADDR_TO_P2(addr) (addr)
29#endif /* defined(CONFIG_SH) */
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +090030
Nobuhiro Iwamatsuf8b75072013-08-22 13:22:02 +090031/* base padding size is 16 */
32#ifndef CONFIG_SH_ETHER_ALIGNE_SIZE
33#define CONFIG_SH_ETHER_ALIGNE_SIZE 16
34#endif
35
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +090036/* Number of supported ports */
37#define MAX_PORT_NUM 2
38
39/* Buffers must be big enough to hold the largest ethernet frame. Also, rx
40 buffers must be a multiple of 32 bytes */
41#define MAX_BUF_SIZE (48 * 32)
42
43/* The number of tx descriptors must be large enough to point to 5 or more
44 frames. If each frame uses 2 descriptors, at least 10 descriptors are needed.
45 We use one descriptor per frame */
46#define NUM_TX_DESC 8
47
48/* The size of the tx descriptor is determined by how much padding is used.
49 4, 20, or 52 bytes of padding can be used */
Nobuhiro Iwamatsuf8b75072013-08-22 13:22:02 +090050#define TX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +090051
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +090052/* Tx descriptor. We always use 3 bytes of padding */
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +090053struct tx_desc_s {
54 volatile u32 td0;
55 u32 td1;
56 u32 td2; /* Buffer start */
Nobuhiro Iwamatsuf8b75072013-08-22 13:22:02 +090057 u8 padding[TX_DESC_PADDING]; /* aligned cache line size */
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +090058};
59
60/* There is no limitation in the number of rx descriptors */
61#define NUM_RX_DESC 8
62
63/* The size of the rx descriptor is determined by how much padding is used.
64 4, 20, or 52 bytes of padding can be used */
Nobuhiro Iwamatsuf8b75072013-08-22 13:22:02 +090065#define RX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
Nobuhiro Iwamatsuf8b75072013-08-22 13:22:02 +090066/* aligned cache line size */
67#define RX_BUF_ALIGNE_SIZE (CONFIG_SH_ETHER_ALIGNE_SIZE > 32 ? 64 : 32)
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +090068
69/* Rx descriptor. We always use 4 bytes of padding */
70struct rx_desc_s {
71 volatile u32 rd0;
72 volatile u32 rd1;
73 u32 rd2; /* Buffer start */
Nobuhiro Iwamatsuf8b75072013-08-22 13:22:02 +090074 u8 padding[TX_DESC_PADDING]; /* aligned cache line size */
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +090075};
76
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +090077struct sh_eth_info {
Nobuhiro Iwamatsu000889c2014-11-04 09:15:47 +090078 struct tx_desc_s *tx_desc_alloc;
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +090079 struct tx_desc_s *tx_desc_base;
80 struct tx_desc_s *tx_desc_cur;
Nobuhiro Iwamatsu000889c2014-11-04 09:15:47 +090081 struct rx_desc_s *rx_desc_alloc;
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +090082 struct rx_desc_s *rx_desc_base;
83 struct rx_desc_s *rx_desc_cur;
Nobuhiro Iwamatsu000889c2014-11-04 09:15:47 +090084 u8 *rx_buf_alloc;
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +090085 u8 *rx_buf_base;
86 u8 mac_addr[6];
87 u8 phy_addr;
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +090088 struct eth_device *dev;
Yoshihiro Shimodabd1024b2011-10-11 18:10:14 +090089 struct phy_device *phydev;
Nobuhiro Iwamatsufbfb5112017-12-01 08:10:32 +090090 void __iomem *iobase;
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +090091};
92
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +090093struct sh_eth_dev {
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +090094 int port;
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +090095 struct sh_eth_info port_info[MAX_PORT_NUM];
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +090096};
97
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +000098/* from linux/drivers/net/ethernet/renesas/sh_eth.h */
99enum {
100 /* E-DMAC registers */
101 EDSR = 0,
102 EDMR,
103 EDTRR,
104 EDRRR,
105 EESR,
106 EESIPR,
107 TDLAR,
108 TDFAR,
109 TDFXR,
110 TDFFR,
111 RDLAR,
112 RDFAR,
113 RDFXR,
114 RDFFR,
115 TRSCER,
116 RMFCR,
117 TFTR,
118 FDR,
119 RMCR,
120 EDOCR,
121 TFUCR,
122 RFOCR,
123 FCFTR,
124 RPADIR,
125 TRIMD,
126 RBWAR,
127 TBRAR,
128
129 /* Ether registers */
130 ECMR,
131 ECSR,
132 ECSIPR,
133 PIR,
134 PSR,
135 RDMLR,
136 PIPR,
137 RFLR,
138 IPGR,
139 APR,
140 MPR,
141 PFTCR,
142 PFRCR,
143 RFCR,
144 RFCF,
145 TPAUSER,
146 TPAUSECR,
147 BCFR,
148 BCFRR,
149 GECMR,
150 BCULR,
151 MAHR,
152 MALR,
153 TROCR,
154 CDCR,
155 LCCR,
156 CNDCR,
157 CEFCR,
158 FRECR,
159 TSFRCR,
160 TLFRCR,
161 CERCR,
162 CEECR,
Nobuhiro Iwamatsu87076782013-08-22 13:22:04 +0900163 RMIIMR, /* R8A7790 */
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000164 MAFCR,
165 RTRATE,
166 CSMR,
167 RMII_MII,
168
169 /* This value must be written at last. */
170 SH_ETH_MAX_REGISTER_OFFSET,
171};
172
173static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
174 [EDSR] = 0x0000,
175 [EDMR] = 0x0400,
176 [EDTRR] = 0x0408,
177 [EDRRR] = 0x0410,
178 [EESR] = 0x0428,
179 [EESIPR] = 0x0430,
180 [TDLAR] = 0x0010,
181 [TDFAR] = 0x0014,
182 [TDFXR] = 0x0018,
183 [TDFFR] = 0x001c,
184 [RDLAR] = 0x0030,
185 [RDFAR] = 0x0034,
186 [RDFXR] = 0x0038,
187 [RDFFR] = 0x003c,
188 [TRSCER] = 0x0438,
189 [RMFCR] = 0x0440,
190 [TFTR] = 0x0448,
191 [FDR] = 0x0450,
192 [RMCR] = 0x0458,
193 [RPADIR] = 0x0460,
194 [FCFTR] = 0x0468,
195 [CSMR] = 0x04E4,
196
197 [ECMR] = 0x0500,
198 [ECSR] = 0x0510,
199 [ECSIPR] = 0x0518,
200 [PIR] = 0x0520,
201 [PSR] = 0x0528,
202 [PIPR] = 0x052c,
203 [RFLR] = 0x0508,
204 [APR] = 0x0554,
205 [MPR] = 0x0558,
206 [PFTCR] = 0x055c,
207 [PFRCR] = 0x0560,
208 [TPAUSER] = 0x0564,
209 [GECMR] = 0x05b0,
210 [BCULR] = 0x05b4,
211 [MAHR] = 0x05c0,
212 [MALR] = 0x05c8,
213 [TROCR] = 0x0700,
214 [CDCR] = 0x0708,
215 [LCCR] = 0x0710,
216 [CEFCR] = 0x0740,
217 [FRECR] = 0x0748,
218 [TSFRCR] = 0x0750,
219 [TLFRCR] = 0x0758,
220 [RFCR] = 0x0760,
221 [CERCR] = 0x0768,
222 [CEECR] = 0x0770,
223 [MAFCR] = 0x0778,
224 [RMII_MII] = 0x0790,
225};
226
Marek Vasut31650cf2019-05-01 18:20:48 +0200227static const u16 sh_eth_offset_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
228 [EDSR] = 0x0000,
229 [EDMR] = 0x0400,
230 [EDTRR] = 0x0408,
231 [EDRRR] = 0x0410,
232 [EESR] = 0x0428,
233 [EESIPR] = 0x0430,
234 [TDLAR] = 0x0010,
235 [TDFAR] = 0x0014,
236 [TDFXR] = 0x0018,
237 [TDFFR] = 0x001c,
238 [RDLAR] = 0x0030,
239 [RDFAR] = 0x0034,
240 [RDFXR] = 0x0038,
241 [RDFFR] = 0x003c,
242 [TRSCER] = 0x0438,
243 [RMFCR] = 0x0440,
244 [TFTR] = 0x0448,
245 [FDR] = 0x0450,
246 [RMCR] = 0x0458,
247 [RPADIR] = 0x0460,
248 [FCFTR] = 0x0468,
249 [CSMR] = 0x04E4,
250
251 [ECMR] = 0x0500,
252 [ECSR] = 0x0510,
253 [ECSIPR] = 0x0518,
254 [PIR] = 0x0520,
255 [PSR] = 0x0528,
256 [PIPR] = 0x052c,
257 [RFLR] = 0x0508,
258 [APR] = 0x0554,
259 [MPR] = 0x0558,
260 [PFTCR] = 0x055c,
261 [PFRCR] = 0x0560,
262 [TPAUSER] = 0x0564,
263 [GECMR] = 0x05b0,
264 [BCULR] = 0x05b4,
265 [MAHR] = 0x05c0,
266 [MALR] = 0x05c8,
267 [TROCR] = 0x0700,
268 [CDCR] = 0x0708,
269 [LCCR] = 0x0710,
270 [CEFCR] = 0x0740,
271 [FRECR] = 0x0748,
272 [TSFRCR] = 0x0750,
273 [TLFRCR] = 0x0758,
274 [RFCR] = 0x0760,
275 [CERCR] = 0x0768,
276 [CEECR] = 0x0770,
277 [MAFCR] = 0x0778,
278 [RMII_MII] = 0x0790,
279};
280
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000281static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
282 [ECMR] = 0x0100,
283 [RFLR] = 0x0108,
284 [ECSR] = 0x0110,
285 [ECSIPR] = 0x0118,
286 [PIR] = 0x0120,
287 [PSR] = 0x0128,
288 [RDMLR] = 0x0140,
289 [IPGR] = 0x0150,
290 [APR] = 0x0154,
291 [MPR] = 0x0158,
292 [TPAUSER] = 0x0164,
293 [RFCF] = 0x0160,
294 [TPAUSECR] = 0x0168,
295 [BCFRR] = 0x016c,
296 [MAHR] = 0x01c0,
297 [MALR] = 0x01c8,
298 [TROCR] = 0x01d0,
299 [CDCR] = 0x01d4,
300 [LCCR] = 0x01d8,
301 [CNDCR] = 0x01dc,
302 [CEFCR] = 0x01e4,
303 [FRECR] = 0x01e8,
304 [TSFRCR] = 0x01ec,
305 [TLFRCR] = 0x01f0,
306 [RFCR] = 0x01f4,
307 [MAFCR] = 0x01f8,
308 [RTRATE] = 0x01fc,
309
310 [EDMR] = 0x0000,
311 [EDTRR] = 0x0008,
312 [EDRRR] = 0x0010,
313 [TDLAR] = 0x0018,
314 [RDLAR] = 0x0020,
315 [EESR] = 0x0028,
316 [EESIPR] = 0x0030,
317 [TRSCER] = 0x0038,
318 [RMFCR] = 0x0040,
319 [TFTR] = 0x0048,
320 [FDR] = 0x0050,
321 [RMCR] = 0x0058,
322 [TFUCR] = 0x0064,
323 [RFOCR] = 0x0068,
Nobuhiro Iwamatsu87076782013-08-22 13:22:04 +0900324 [RMIIMR] = 0x006C,
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000325 [FCFTR] = 0x0070,
326 [RPADIR] = 0x0078,
327 [TRIMD] = 0x007c,
328 [RBWAR] = 0x00c8,
329 [RDFAR] = 0x00cc,
330 [TBRAR] = 0x00d4,
331 [TDFAR] = 0x00d8,
332};
333
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900334/* Register Address */
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000335#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
Yoshihiro Shimoda26235092012-06-26 16:38:06 +0000336#define SH_ETH_TYPE_GETHER
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900337#define BASE_IO_ADDR 0xfee00000
Yoshihiro Shimoda3067f812013-12-18 16:04:04 +0900338#elif defined(CONFIG_CPU_SH7757) || \
339 defined(CONFIG_CPU_SH7752) || \
340 defined(CONFIG_CPU_SH7753)
Yoshihiro Shimoda631fea82012-06-26 16:38:11 +0000341#if defined(CONFIG_SH_ETHER_USE_GETHER)
342#define SH_ETH_TYPE_GETHER
343#define BASE_IO_ADDR 0xfee00000
344#else
Yoshihiro Shimoda26235092012-06-26 16:38:06 +0000345#define SH_ETH_TYPE_ETHER
Yoshihiro Shimoda903de462011-01-18 17:53:45 +0900346#define BASE_IO_ADDR 0xfef00000
Yoshihiro Shimoda631fea82012-06-26 16:38:11 +0000347#endif
Nobuhiro Iwamatsudcd5a592012-08-02 22:08:40 +0000348#elif defined(CONFIG_R8A7740)
349#define SH_ETH_TYPE_GETHER
350#define BASE_IO_ADDR 0xE9A00000
Marek Vasuteffb7902018-01-22 01:42:32 +0100351#elif defined(CONFIG_RCAR_GEN2)
Nobuhiro Iwamatsu87076782013-08-22 13:22:04 +0900352#define SH_ETH_TYPE_ETHER
353#define BASE_IO_ADDR 0xEE700200
Nobuhiro Iwamatsu62cbddc2014-01-23 07:52:18 +0900354#elif defined(CONFIG_R7S72100)
355#define SH_ETH_TYPE_RZ
356#define BASE_IO_ADDR 0xE8203000
Marek Vasut46c33162019-07-31 12:58:06 +0200357#elif defined(CONFIG_R8A77980)
358#define SH_ETH_TYPE_GETHER
359#define BASE_IO_ADDR 0xE7400000
Yoshihiro Shimoda903de462011-01-18 17:53:45 +0900360#endif
361
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900362/*
363 * Register's bits
364 * Copy from Linux driver source code
365 */
Nobuhiro Iwamatsu62cbddc2014-01-23 07:52:18 +0900366#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900367/* EDSR */
368enum EDSR_BIT {
369 EDSR_ENT = 0x01, EDSR_ENR = 0x02,
370};
371#define EDSR_ENALL (EDSR_ENT|EDSR_ENR)
372#endif
373
374/* EDMR */
375enum DMAC_M_BIT {
Marek Vasut46c33162019-07-31 12:58:06 +0200376 EDMR_NBST = 0x80, /* DMA transfer burst mode */
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900377 EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
Nobuhiro Iwamatsu62cbddc2014-01-23 07:52:18 +0900378#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
Nobuhiro Iwamatsuee6ec5d2012-02-02 21:28:49 +0000379 EDMR_SRST = 0x03, /* Receive/Send reset */
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900380 EMDR_DESC_R = 0x30, /* Descriptor reserve size */
381 EDMR_EL = 0x40, /* Litte endian */
Yoshihiro Shimoda26235092012-06-26 16:38:06 +0000382#elif defined(SH_ETH_TYPE_ETHER)
Yoshihiro Shimoda903de462011-01-18 17:53:45 +0900383 EDMR_SRST = 0x01,
384 EMDR_DESC_R = 0x30, /* Descriptor reserve size */
385 EDMR_EL = 0x40, /* Litte endian */
Yoshihiro Shimoda26235092012-06-26 16:38:06 +0000386#else
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900387 EDMR_SRST = 0x01,
388#endif
389};
390
Nobuhiro Iwamatsuf8b75072013-08-22 13:22:02 +0900391#if CONFIG_SH_ETHER_ALIGNE_SIZE == 64
392# define EMDR_DESC EDMR_DL1
393#elif CONFIG_SH_ETHER_ALIGNE_SIZE == 32
394# define EMDR_DESC EDMR_DL0
395#elif CONFIG_SH_ETHER_ALIGNE_SIZE == 16 /* Default */
396# define EMDR_DESC 0
397#endif
398
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900399/* RFLR */
400#define RFLR_RFL_MIN 0x05EE /* Recv Frame length 1518 byte */
401
402/* EDTRR */
403enum DMAC_T_BIT {
Nobuhiro Iwamatsu62cbddc2014-01-23 07:52:18 +0900404#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900405 EDTRR_TRNS = 0x03,
406#else
407 EDTRR_TRNS = 0x01,
408#endif
409};
410
411/* GECMR */
412enum GECMR_BIT {
Yoshihiro Shimoda3067f812013-12-18 16:04:04 +0900413#if defined(CONFIG_CPU_SH7757) || \
414 defined(CONFIG_CPU_SH7752) || \
415 defined(CONFIG_CPU_SH7753)
Yoshihiro Shimoda631fea82012-06-26 16:38:11 +0000416 GECMR_1000B = 0x20, GECMR_100B = 0x01, GECMR_10B = 0x00,
417#else
Simon Munton09fcc8b2009-02-02 09:44:08 +0000418 GECMR_1000B = 0x01, GECMR_100B = 0x04, GECMR_10B = 0x00,
Yoshihiro Shimoda631fea82012-06-26 16:38:11 +0000419#endif
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900420};
421
422/* EDRRR*/
423enum EDRRR_R_BIT {
424 EDRRR_R = 0x01,
425};
426
427/* TPAUSER */
428enum TPAUSER_BIT {
429 TPAUSER_TPAUSE = 0x0000ffff,
430 TPAUSER_UNLIMITED = 0,
431};
432
433/* BCFR */
434enum BCFR_BIT {
435 BCFR_RPAUSE = 0x0000ffff,
436 BCFR_UNLIMITED = 0,
437};
438
439/* PIR */
440enum PIR_BIT {
441 PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01,
442};
443
444/* PSR */
445enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };
446
447/* EESR */
448enum EESR_BIT {
Yoshihiro Shimoda26235092012-06-26 16:38:06 +0000449#if defined(SH_ETH_TYPE_ETHER)
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900450 EESR_TWB = 0x40000000,
451#else
452 EESR_TWB = 0xC0000000,
453 EESR_TC1 = 0x20000000,
454 EESR_TUC = 0x10000000,
455 EESR_ROC = 0x80000000,
456#endif
457 EESR_TABT = 0x04000000,
458 EESR_RABT = 0x02000000, EESR_RFRMER = 0x01000000,
Yoshihiro Shimoda26235092012-06-26 16:38:06 +0000459#if defined(SH_ETH_TYPE_ETHER)
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900460 EESR_ADE = 0x00800000,
461#endif
462 EESR_ECI = 0x00400000,
463 EESR_FTC = 0x00200000, EESR_TDE = 0x00100000,
464 EESR_TFE = 0x00080000, EESR_FRC = 0x00040000,
465 EESR_RDE = 0x00020000, EESR_RFE = 0x00010000,
Yoshihiro Shimoda26235092012-06-26 16:38:06 +0000466#if defined(SH_ETH_TYPE_ETHER)
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900467 EESR_CND = 0x00000800,
468#endif
469 EESR_DLC = 0x00000400,
470 EESR_CD = 0x00000200, EESR_RTO = 0x00000100,
471 EESR_RMAF = 0x00000080, EESR_CEEF = 0x00000040,
472 EESR_CELF = 0x00000020, EESR_RRF = 0x00000010,
Nobuhiro Iwamatsu1dbd7282014-01-23 07:52:20 +0900473 EESR_RTLF = 0x00000008, EESR_RTSF = 0x00000004,
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900474 EESR_PRE = 0x00000002, EESR_CERF = 0x00000001,
475};
476
477
Nobuhiro Iwamatsu62cbddc2014-01-23 07:52:18 +0900478#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900479# define TX_CHECK (EESR_TC1 | EESR_FTC)
480# define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
481 | EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI)
482# define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE)
483
484#else
485# define TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO)
486# define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
487 | EESR_RFRMER | EESR_ADE | EESR_TFE | EESR_TDE | EESR_ECI)
488# define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE)
489#endif
490
491/* EESIPR */
492enum DMAC_IM_BIT {
493 DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000,
494 DMAC_M_RABT = 0x02000000,
495 DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000,
496 DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000,
497 DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000,
498 DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000,
499 DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800,
500 DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200,
501 DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080,
502 DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008,
503 DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002,
504 DMAC_M_RINT1 = 0x00000001,
505};
506
507/* Receive descriptor bit */
508enum RD_STS_BIT {
509 RD_RACT = 0x80000000, RD_RDLE = 0x40000000,
510 RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000,
511 RD_RFE = 0x08000000, RD_RFS10 = 0x00000200,
512 RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080,
513 RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020,
514 RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008,
515 RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002,
516 RD_RFS1 = 0x00000001,
517};
518#define RDF1ST RD_RFP1
519#define RDFEND RD_RFP0
520#define RD_RFP (RD_RFP1|RD_RFP0)
521
522/* RDFFR*/
523enum RDFFR_BIT {
524 RDFFR_RDLF = 0x01,
525};
526
527/* FCFTR */
528enum FCFTR_BIT {
529 FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000,
530 FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004,
531 FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001,
532};
533#define FIFO_F_D_RFF (FCFTR_RFF2|FCFTR_RFF1|FCFTR_RFF0)
534#define FIFO_F_D_RFD (FCFTR_RFD2|FCFTR_RFD1|FCFTR_RFD0)
535
536/* Transfer descriptor bit */
537enum TD_STS_BIT {
Nobuhiro Iwamatsu62cbddc2014-01-23 07:52:18 +0900538#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_ETHER) || \
539 defined(SH_ETH_TYPE_RZ)
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900540 TD_TACT = 0x80000000,
541#else
542 TD_TACT = 0x7fffffff,
543#endif
544 TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000,
545 TD_TFP0 = 0x10000000,
546};
547#define TDF1ST TD_TFP1
548#define TDFEND TD_TFP0
549#define TD_TFP (TD_TFP1|TD_TFP0)
550
551/* RMCR */
552enum RECV_RST_BIT { RMCR_RST = 0x01, };
553/* ECMR */
554enum FELIC_MODE_BIT {
Nobuhiro Iwamatsu62cbddc2014-01-23 07:52:18 +0900555#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
Nobuhiro Iwamatsue2752db2014-01-23 07:52:19 +0900556 ECMR_TRCCM = 0x04000000, ECMR_RCSC = 0x00800000,
557 ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000,
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900558#endif
559 ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
560 ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
561 ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
562 ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, ECMR_DM = 0x00000002,
563 ECMR_PRM = 0x00000001,
Nobuhiro Iwamatsu3bb4cc32011-11-14 16:56:59 +0900564#ifdef CONFIG_CPU_SH7724
565 ECMR_RTM = 0x00000010,
Marek Vasut46c33162019-07-31 12:58:06 +0200566#elif defined(CONFIG_RCAR_GEN2) || defined (CONFIG_R8A77980)
Nobuhiro Iwamatsu87076782013-08-22 13:22:04 +0900567 ECMR_RTM = 0x00000004,
Nobuhiro Iwamatsu3bb4cc32011-11-14 16:56:59 +0900568#endif
569
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900570};
571
Nobuhiro Iwamatsu62cbddc2014-01-23 07:52:18 +0900572#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
Nobuhiro Iwamatsue2752db2014-01-23 07:52:19 +0900573#define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | \
574 ECMR_RXF | ECMR_TXF | ECMR_MCT)
Yoshihiro Shimoda26235092012-06-26 16:38:06 +0000575#elif defined(SH_ETH_TYPE_ETHER)
Nobuhiro Iwamatsu3bb4cc32011-11-14 16:56:59 +0900576#define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF)
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900577#else
Yoshihiro Shimoda903de462011-01-18 17:53:45 +0900578#define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT)
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900579#endif
580
581/* ECSR */
582enum ECSR_STATUS_BIT {
Yoshihiro Shimoda26235092012-06-26 16:38:06 +0000583#if defined(SH_ETH_TYPE_ETHER)
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900584 ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
585#endif
586 ECSR_LCHNG = 0x04,
587 ECSR_MPD = 0x02, ECSR_ICD = 0x01,
588};
589
Nobuhiro Iwamatsu62cbddc2014-01-23 07:52:18 +0900590#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900591# define ECSR_INIT (ECSR_ICD | ECSIPR_MPDIP)
592#else
593# define ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | \
594 ECSR_LCHNG | ECSR_ICD | ECSIPR_MPDIP)
595#endif
596
597/* ECSIPR */
598enum ECSIPR_STATUS_MASK_BIT {
Yoshihiro Shimoda26235092012-06-26 16:38:06 +0000599#if defined(SH_ETH_TYPE_ETHER)
Nobuhiro Iwamatsua6616ef2012-06-05 16:39:06 +0000600 ECSIPR_BRCRXIP = 0x20,
Nobuhiro Iwamatsuee6ec5d2012-02-02 21:28:49 +0000601 ECSIPR_PSRTOIP = 0x10,
Yoshihiro Shimoda26235092012-06-26 16:38:06 +0000602#elif defined(SH_ETY_TYPE_GETHER)
Nobuhiro Iwamatsuee6ec5d2012-02-02 21:28:49 +0000603 ECSIPR_PSRTOIP = 0x10,
604 ECSIPR_PHYIP = 0x08,
Nobuhiro Iwamatsua6616ef2012-06-05 16:39:06 +0000605#endif
Nobuhiro Iwamatsuee6ec5d2012-02-02 21:28:49 +0000606 ECSIPR_LCHNGIP = 0x04,
607 ECSIPR_MPDIP = 0x02,
608 ECSIPR_ICDIP = 0x01,
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900609};
610
Nobuhiro Iwamatsu62cbddc2014-01-23 07:52:18 +0900611#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900612# define ECSIPR_INIT (ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)
613#else
614# define ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | \
615 ECSIPR_ICDIP | ECSIPR_MPDIP)
616#endif
617
618/* APR */
619enum APR_BIT {
620 APR_AP = 0x00000004,
621};
622
623/* MPR */
624enum MPR_BIT {
625 MPR_MP = 0x00000006,
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900626};
627
628/* TRSCER */
629enum DESC_I_BIT {
630 DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200,
631 DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010,
632 DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002,
633 DESC_I_RINT1 = 0x0001,
634};
635
636/* RPADIR */
637enum RPADIR_BIT {
638 RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000,
639 RPADIR_PADR = 0x0003f,
640};
641
Nobuhiro Iwamatsu62cbddc2014-01-23 07:52:18 +0900642#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900643# define RPADIR_INIT (0x00)
644#else
645# define RPADIR_INIT (RPADIR_PADS1)
646#endif
647
648/* FDR */
649enum FIFO_SIZE_BIT {
650 FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007,
651};
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000652
Nobuhiro Iwamatsufbfb5112017-12-01 08:10:32 +0900653static inline unsigned long sh_eth_reg_addr(struct sh_eth_info *port,
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000654 int enum_index)
655{
Chris Brandtf6ac6262017-11-03 08:30:12 -0500656#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000657 const u16 *reg_offset = sh_eth_offset_gigabit;
658#elif defined(SH_ETH_TYPE_ETHER)
659 const u16 *reg_offset = sh_eth_offset_fast_sh4;
Marek Vasut31650cf2019-05-01 18:20:48 +0200660#elif defined(SH_ETH_TYPE_RZ)
661 const u16 *reg_offset = sh_eth_offset_rz;
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000662#else
663#error
664#endif
Nobuhiro Iwamatsufbfb5112017-12-01 08:10:32 +0900665 return (unsigned long)port->iobase + reg_offset[enum_index];
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000666}
667
Nobuhiro Iwamatsufbfb5112017-12-01 08:10:32 +0900668static inline void sh_eth_write(struct sh_eth_info *port, unsigned long data,
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000669 int enum_index)
670{
Nobuhiro Iwamatsufbfb5112017-12-01 08:10:32 +0900671 outl(data, sh_eth_reg_addr(port, enum_index));
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000672}
673
Nobuhiro Iwamatsufbfb5112017-12-01 08:10:32 +0900674static inline unsigned long sh_eth_read(struct sh_eth_info *port,
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000675 int enum_index)
676{
Nobuhiro Iwamatsufbfb5112017-12-01 08:10:32 +0900677 return inl(sh_eth_reg_addr(port, enum_index));
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000678}