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Wolfgang Denk32cb2c72006-07-21 11:31:42 +02001/*
2 * Memory Setup stuff - taken from blob memsetup.S
3 *
4 * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
5 * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
6 *
7 * Modified for the Samsung SMDK2410 by
8 * (C) Copyright 2002
9 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
10 *
11 * Modified for the friendly-arm SBC-2410X by
12 * (C) Copyright 2005
13 * JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com>
14 *
15 * See file CREDITS for list of people who contributed to this
16 * project.
17 *
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * MA 02111-1307 USA
32 */
33
34#include <config.h>
35#include <version.h>
36
37/*
38 * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S
39 *
40 * Copyright (C) 2002 Samsung Electronics SW.LEE <hitchcar@sec.samsung.com>
41 */
42
43#define BWSCON 0x48000000
44
45/* BWSCON */
Wolfgang Denkb9365a22006-07-21 11:56:05 +020046#define DW8 (0x0)
47#define DW16 (0x1)
48#define DW32 (0x2)
49#define WAIT (0x1<<2)
50#define UBLB (0x1<<3)
Wolfgang Denk32cb2c72006-07-21 11:31:42 +020051
Wolfgang Denkb9365a22006-07-21 11:56:05 +020052#define B1_BWSCON (DW16)
53#define B2_BWSCON (DW16)
54#define B3_BWSCON (DW16 + WAIT + UBLB)
55#define B4_BWSCON (DW16)
56#define B5_BWSCON (DW16)
57#define B6_BWSCON (DW32)
58#define B7_BWSCON (DW32)
Wolfgang Denk32cb2c72006-07-21 11:31:42 +020059
Wolfgang Denkb9365a22006-07-21 11:56:05 +020060#define B0_Tacs 0x0
61#define B0_Tcos 0x0
62#define B0_Tacc 0x7
63#define B0_Tcoh 0x0
64#define B0_Tah 0x0
65#define B0_Tacp 0x0
66#define B0_PMC 0x0
Wolfgang Denk32cb2c72006-07-21 11:31:42 +020067
Wolfgang Denkb9365a22006-07-21 11:56:05 +020068#define B1_Tacs 0x0
69#define B1_Tcos 0x0
70#define B1_Tacc 0x7
71#define B1_Tcoh 0x0
72#define B1_Tah 0x0
73#define B1_Tacp 0x0
74#define B1_PMC 0x0
Wolfgang Denk32cb2c72006-07-21 11:31:42 +020075
Wolfgang Denkb9365a22006-07-21 11:56:05 +020076#define B2_Tacs 0x0
77#define B2_Tcos 0x0
78#define B2_Tacc 0x7
79#define B2_Tcoh 0x0
80#define B2_Tah 0x0
81#define B2_Tacp 0x0
82#define B2_PMC 0x0
Wolfgang Denk32cb2c72006-07-21 11:31:42 +020083
Wolfgang Denkb9365a22006-07-21 11:56:05 +020084#define B3_Tacs 0xc
85#define B3_Tcos 0x7
86#define B3_Tacc 0xf
87#define B3_Tcoh 0x1
88#define B3_Tah 0x0
89#define B3_Tacp 0x0
90#define B3_PMC 0x0
Wolfgang Denk32cb2c72006-07-21 11:31:42 +020091
Wolfgang Denkb9365a22006-07-21 11:56:05 +020092#define B4_Tacs 0x0
93#define B4_Tcos 0x0
94#define B4_Tacc 0x7
95#define B4_Tcoh 0x0
96#define B4_Tah 0x0
97#define B4_Tacp 0x0
98#define B4_PMC 0x0
Wolfgang Denk32cb2c72006-07-21 11:31:42 +020099
Wolfgang Denkb9365a22006-07-21 11:56:05 +0200100#define B5_Tacs 0xc
101#define B5_Tcos 0x7
102#define B5_Tacc 0xf
103#define B5_Tcoh 0x1
104#define B5_Tah 0x0
105#define B5_Tacp 0x0
106#define B5_PMC 0x0
Wolfgang Denk32cb2c72006-07-21 11:31:42 +0200107
Wolfgang Denkb9365a22006-07-21 11:56:05 +0200108#define B6_MT 0x3 /* SDRAM */
109#define B6_Trcd 0x1
110#define B6_SCAN 0x1 /* 9bit */
Wolfgang Denk32cb2c72006-07-21 11:31:42 +0200111
Wolfgang Denkb9365a22006-07-21 11:56:05 +0200112#define B7_MT 0x3 /* SDRAM */
113#define B7_Trcd 0x1 /* 3clk */
114#define B7_SCAN 0x1 /* 9bit */
Wolfgang Denk32cb2c72006-07-21 11:31:42 +0200115
116/* REFRESH parameter */
Wolfgang Denkb9365a22006-07-21 11:56:05 +0200117#define REFEN 0x1 /* Refresh enable */
118#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
119#define Trp 0x0 /* 2clk */
120#define Trc 0x3 /* 7clk */
121#define Tchr 0x2 /* 3clk */
Wolfgang Denk32cb2c72006-07-21 11:31:42 +0200122#define REFCNT 0x0459
123/**************************************/
124
125_TEXT_BASE:
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200126 .word CONFIG_SYS_TEXT_BASE
Wolfgang Denk32cb2c72006-07-21 11:31:42 +0200127
128.globl lowlevel_init
129lowlevel_init:
130 /* memory control configuration */
131 /* make r0 relative the current location so that it */
132 /* reads SMRDATA out of FLASH rather than memory ! */
133 ldr r0, =SMRDATA
134 ldr r1, _TEXT_BASE
135 sub r0, r0, r1
136 ldr r1, =BWSCON /* Bus Width Status Controller */
137 add r2, r0, #13*4
1380:
139 ldr r3, [r0], #4
140 str r3, [r1], #4
141 cmp r2, r0
142 bne 0b
143
144 /* everything is fine now */
145 mov pc, lr
146
147 .ltorg
148/* the literal pools origin */
149
150SMRDATA:
151 .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
152 .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
153 .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
154 .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
155 .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
156 .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
157 .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
158 .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
159 .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
160 .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
161 .word 0xb2
162 .word 0x30
163 .word 0x30