| Christoph Fritz | 730d254 | 2016-11-29 16:13:40 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2016 samtec automotive software & electronics gmbh |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | */ |
| 6 | |
| 7 | #define __ASSEMBLY__ |
| 8 | #include <config.h> |
| 9 | |
| 10 | /* image version */ |
| 11 | |
| 12 | IMAGE_VERSION 2 |
| 13 | |
| 14 | /* |
| 15 | * Boot Device : one of |
| 16 | * spi/sd/nand/onenand, qspi/nor |
| 17 | */ |
| 18 | |
| 19 | BOOT_FROM sd |
| 20 | |
| 21 | /* |
| 22 | * Device Configuration Data (DCD) |
| 23 | * |
| 24 | * Each entry must have the format: |
| 25 | * Addr-type Address Value |
| 26 | * |
| 27 | * where: |
| 28 | * Addr-type register length (1,2 or 4 bytes) |
| 29 | * Address absolute address of the register |
| 30 | * value value to be stored in the register |
| 31 | */ |
| 32 | |
| 33 | /* Enable all clocks */ |
| 34 | DATA 4 0x020c4068 0xffffffff |
| 35 | DATA 4 0x020c406c 0xffffffff |
| 36 | DATA 4 0x020c4070 0xffffffff |
| 37 | DATA 4 0x020c4074 0xffffffff |
| 38 | DATA 4 0x020c4078 0xffffffff |
| 39 | DATA 4 0x020c407c 0xffffffff |
| 40 | DATA 4 0x020c4080 0xffffffff |
| 41 | DATA 4 0x020c4084 0xffffffff |
| 42 | |
| 43 | /* IOMUX - DDR IO Type */ |
| 44 | DATA 4 0x020e0618 0x000c0000 |
| 45 | DATA 4 0x020e05fc 0x00000000 |
| 46 | |
| 47 | /* Clock */ |
| 48 | DATA 4 0x020e032c 0x00000030 |
| 49 | |
| 50 | /* Address */ |
| 51 | DATA 4 0x020e0300 0x00000028 |
| 52 | DATA 4 0x020e02fc 0x00000028 |
| 53 | DATA 4 0x020e05f4 0x00000028 |
| 54 | |
| 55 | /* Control */ |
| 56 | DATA 4 0x020e0340 0x00000028 |
| 57 | |
| 58 | DATA 4 0x020e0320 0x00000000 |
| 59 | DATA 4 0x020e0310 0x00000028 |
| 60 | DATA 4 0x020e0314 0x00000028 |
| 61 | DATA 4 0x020e0614 0x00000028 |
| 62 | |
| 63 | /* Data Strobe */ |
| 64 | DATA 4 0x020e05f8 0x00020000 |
| 65 | DATA 4 0x020e0330 0x00000028 |
| 66 | DATA 4 0x020e0334 0x00000028 |
| 67 | DATA 4 0x020e0338 0x00000028 |
| 68 | DATA 4 0x020e033c 0x00000028 |
| 69 | |
| 70 | /* Data */ |
| 71 | DATA 4 0x020e0608 0x00020000 |
| 72 | DATA 4 0x020e060c 0x00000028 |
| 73 | DATA 4 0x020e0610 0x00000028 |
| 74 | DATA 4 0x020e061c 0x00000028 |
| 75 | DATA 4 0x020e0620 0x00000028 |
| 76 | DATA 4 0x020e02ec 0x00000028 |
| 77 | DATA 4 0x020e02f0 0x00000028 |
| 78 | DATA 4 0x020e02f4 0x00000028 |
| 79 | DATA 4 0x020e02f8 0x00000028 |
| 80 | |
| 81 | /* Calibrations - ZQ */ |
| 82 | DATA 4 0x021b0800 0xa1390003 |
| 83 | |
| 84 | /* Write leveling */ |
| 85 | DATA 4 0x021b080c 0x00290025 |
| 86 | DATA 4 0x021b0810 0x00210022 |
| 87 | |
| 88 | /* DQS Read Gate */ |
| 89 | DATA 4 0x021b083c 0x4142013a |
| 90 | DATA 4 0x021b0840 0x012e0123 |
| 91 | |
| 92 | /* Read/Write Delay */ |
| 93 | DATA 4 0x021b0848 0x43474949 |
| 94 | DATA 4 0x021b0850 0x38383c38 |
| 95 | |
| 96 | /* Read data bit delay */ |
| 97 | DATA 4 0x021b081c 0x33333333 |
| 98 | DATA 4 0x021b0820 0x33333333 |
| 99 | DATA 4 0x021b0824 0x33333333 |
| 100 | DATA 4 0x021b0828 0x33333333 |
| 101 | |
| 102 | /* Complete calibration by forced measurement */ |
| 103 | DATA 4 0x021b08b8 0x00000800 |
| 104 | |
| 105 | /* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */ |
| 106 | DATA 4 0x021b0004 0x0002002d |
| 107 | DATA 4 0x021b0008 0x00333040 |
| 108 | DATA 4 0x021b000c 0x676b52f2 |
| 109 | DATA 4 0x021b0010 0x926e8b63 |
| 110 | DATA 4 0x021b0014 0x01ff00db |
| 111 | DATA 4 0x021b0018 0x00011740 |
| 112 | DATA 4 0x021b001c 0x00008000 |
| 113 | DATA 4 0x021b002c 0x000026d2 |
| 114 | DATA 4 0x021b0030 0x006b1023 |
| 115 | DATA 4 0x021b0040 0x0000005f |
| 116 | DATA 4 0x021b0000 0x84190000 |
| 117 | |
| 118 | /* Initialize MT41K256M16HA-125 - MR2 */ |
| 119 | DATA 4 0x021b001c 0x02008032 |
| 120 | /* MR3 */ |
| 121 | DATA 4 0x021b001c 0x00008033 |
| 122 | /* MR1 */ |
| 123 | DATA 4 0x021b001c 0x00048031 |
| 124 | /* MR0 */ |
| 125 | DATA 4 0x021b001c 0x15108030 |
| 126 | /* DDR device ZQ calibration */ |
| 127 | DATA 4 0x021b001c 0x04008040 |
| 128 | |
| 129 | /* Final DDR setup, before operation start */ |
| 130 | DATA 4 0x021b0020 0x00007800 |
| 131 | DATA 4 0x021b0818 0x00022227 |
| 132 | DATA 4 0x021b001c 0x00000000 |