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wdenkdb2f721f2003-03-06 00:58:30 +00001/*
2 * (C) Copyright 2003
3 * EMK Elektronik GmbH <www.emk-elektronik.de>
4 * Reinhard Meyer <r.meyer@emk-elektronik.de>
5 *
6 * Configuation settings for the TOP860 board.
7 *
8 * -----------------------------------------------------------------
Wolfgang Denk1a459662013-07-08 09:37:19 +02009 * SPDX-License-Identifier: GPL-2.0+
wdenkdb2f721f2003-03-06 00:58:30 +000010 */
11/*
wdenk945af8d2003-07-16 21:53:01 +000012 * TOP860 is a simple module:
13 * 16-bit wide FLASH on CS0 (2MB or more)
14 * 32-bit wide DRAM on CS2 (either 4MB or 16MB)
15 * FEC with Am79C874 100-Base-T and Fiber Optic
16 * Ports available, but we choose SMC1 for Console
wdenkdb2f721f2003-03-06 00:58:30 +000017 * 8k I2C EEPROM at address 0xae, 6k user available, 2k factory set
wdenk945af8d2003-07-16 21:53:01 +000018 * 32768Hz crystal PLL set for 49.152MHz Core and 24.576MHz Bus Clock
19 *
20 * This config has been copied from MBX.h / MBX860T.h
wdenkdb2f721f2003-03-06 00:58:30 +000021 */
22/*
23 * board/config.h - configuration options, board specific
24 */
25
26#ifndef __CONFIG_H
27#define __CONFIG_H
28
29/*
30 * High Level Configuration Options
31 * (easy to change)
32 */
33
34/*-----------------------------------------------------------------------
35 * CPU and BOARD type
36 */
37#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
38#define CONFIG_MPC860T 1 /* even better... an FEC! */
39#define CONFIG_TOP860 1 /* ...on a TOP860 module */
Wolfgang Denk2ae18242010-10-06 09:05:45 +020040
41#define CONFIG_SYS_TEXT_BASE 0x80000000
42
wdenkdb2f721f2003-03-06 00:58:30 +000043#undef CONFIG_WATCHDOG /* watchdog disabled */
wdenk945af8d2003-07-16 21:53:01 +000044#define CONFIG_IDENT_STRING " EMK TOP860"
wdenkdb2f721f2003-03-06 00:58:30 +000045
46/*-----------------------------------------------------------------------
47 * CLOCK settings
48 */
wdenk945af8d2003-07-16 21:53:01 +000049#define CONFIG_SYSCLK 49152000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020050#define CONFIG_SYS_XTAL 32768
wdenk945af8d2003-07-16 21:53:01 +000051#define CONFIG_EBDF 1
52#define CONFIG_COM 3
53#define CONFIG_RTC_MPC8xx
54
wdenkdb2f721f2003-03-06 00:58:30 +000055/*-----------------------------------------------------------------------
56 * Physical memory map as defined by EMK
57 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020058#define CONFIG_SYS_IMMR 0xFFF00000 /* Internal Memory Mapped Register */
59#define CONFIG_SYS_FLASH_BASE 0x80000000 /* FLASH in final mapping */
60#define CONFIG_SYS_DRAM_BASE 0x00000000 /* DRAM in final mapping */
61#define CONFIG_SYS_FLASH_MAX 0x00400000 /* max FLASH to expect */
62#define CONFIG_SYS_DRAM_MAX 0x01000000 /* max DRAM to expect */
wdenk945af8d2003-07-16 21:53:01 +000063
wdenkdb2f721f2003-03-06 00:58:30 +000064/*-----------------------------------------------------------------------
65 * derived values
66 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020067#define CONFIG_SYS_MF (CONFIG_SYSCLK/CONFIG_SYS_XTAL)
68#define CONFIG_SYS_CPUCLOCK CONFIG_SYSCLK
69#define CONFIG_SYS_BRGCLOCK CONFIG_SYSCLK
70#define CONFIG_SYS_BUSCLOCK (CONFIG_SYSCLK >> CONFIG_EBDF)
71#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk945af8d2003-07-16 21:53:01 +000072#define CONFIG_8xx_GCLK_FREQ CONFIG_SYSCLK
73
wdenkdb2f721f2003-03-06 00:58:30 +000074/*-----------------------------------------------------------------------
75 * FLASH organization
76 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020077#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
78#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
wdenkdb2f721f2003-03-06 00:58:30 +000079
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020080#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
81#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenk945af8d2003-07-16 21:53:01 +000082
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020083#define CONFIG_SYS_FLASH_CFI
wdenkdb2f721f2003-03-06 00:58:30 +000084
85/*-----------------------------------------------------------------------
86 * Command interpreter
87 */
88#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
89#undef CONFIG_8xx_CONS_SMC2
90#define CONFIG_BAUDRATE 9600
wdenk945af8d2003-07-16 21:53:01 +000091
wdenkdb2f721f2003-03-06 00:58:30 +000092/*
93 * Allow partial commands to be matched to uniqueness.
94 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020095#define CONFIG_SYS_MATCH_PARTIAL_CMD
wdenkdb2f721f2003-03-06 00:58:30 +000096
Jon Loeligera5562902007-07-08 15:31:57 -050097
wdenkdb2f721f2003-03-06 00:58:30 +000098/*
Jon Loeligera5562902007-07-08 15:31:57 -050099 * Command line configuration.
wdenkdb2f721f2003-03-06 00:58:30 +0000100 */
Jon Loeligera5562902007-07-08 15:31:57 -0500101#include <config_cmd_default.h>
102
103#define CONFIG_CMD_ASKENV
104#define CONFIG_CMD_DHCP
105#define CONFIG_CMD_I2C
106#define CONFIG_CMD_EEPROM
107#define CONFIG_CMD_REGINFO
108#define CONFIG_CMD_IMMAP
109#define CONFIG_CMD_ELF
110#define CONFIG_CMD_DATE
111#define CONFIG_CMD_MII
112#define CONFIG_CMD_BEDBUG
113
wdenkdb2f721f2003-03-06 00:58:30 +0000114
Wolfgang Denk74de7ae2009-04-01 23:34:12 +0200115#define CONFIG_SOURCE 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
wdenkdb2f721f2003-03-06 00:58:30 +0000117#undef CONFIG_LOADS_ECHO /* NO echo on for serial download */
118
wdenkdb2f721f2003-03-06 00:58:30 +0000119
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_LONGHELP /* undef to save memory */
121#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
wdenk945af8d2003-07-16 21:53:01 +0000122
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#undef CONFIG_SYS_HUSH_PARSER /* Hush parse for U-Boot */
wdenk945af8d2003-07-16 21:53:01 +0000124
wdenk945af8d2003-07-16 21:53:01 +0000125
Jon Loeligera5562902007-07-08 15:31:57 -0500126#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkdb2f721f2003-03-06 00:58:30 +0000128#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkdb2f721f2003-03-06 00:58:30 +0000130#endif
wdenk945af8d2003-07-16 21:53:01 +0000131
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
133#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
134#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkdb2f721f2003-03-06 00:58:30 +0000135
136/*-----------------------------------------------------------------------
137 * Memory Test Command
138 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
140#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenk945af8d2003-07-16 21:53:01 +0000141
wdenkdb2f721f2003-03-06 00:58:30 +0000142/*-----------------------------------------------------------------------
143 * Environment handler
144 * only the first 6k in EEPROM are available for user. Of that we use 256b
145 */
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200146#define CONFIG_ENV_IS_IN_EEPROM 1 /* turn on EEPROM env feature */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200147#define CONFIG_ENV_OFFSET 0x1000
148#define CONFIG_ENV_SIZE 0x0700
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
150#define CONFIG_SYS_FACT_OFFSET 0x1800
151#define CONFIG_SYS_FACT_SIZE 0x0800
152#define CONFIG_SYS_I2C_FACT_ADDR 0x57
153#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
154#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
155#define CONFIG_SYS_EEPROM_SIZE 0x2000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12
wdenk945af8d2003-07-16 21:53:01 +0000157#define CONFIG_ENV_OVERWRITE
158#define CONFIG_MISC_INIT_R
159
Heiko Schocherea818db2013-01-29 08:53:15 +0100160#define CONFIG_SYS_I2C
161#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
162#define CONFIG_SYS_I2C_SOFT_SPEED 100000
163#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
164/**/
wdenk945af8d2003-07-16 21:53:01 +0000165#define SDA 0x00010
166#define SCL 0x00020
Wolfgang Denkf57f70a2005-10-13 01:45:54 +0200167#define __I2C_DIR immr->im_cpm.cp_pbdir
168#define __I2C_DAT immr->im_cpm.cp_pbdat
169#define __I2C_PAR immr->im_cpm.cp_pbpar
170#define __I2C_ODR immr->im_cpm.cp_pbodr
171#define I2C_INIT { __I2C_PAR &= ~(SDA|SCL); \
172 __I2C_ODR &= ~(SDA|SCL); \
173 __I2C_DAT |= (SDA|SCL); \
174 __I2C_DIR|=(SDA|SCL); }
175#define I2C_READ ((__I2C_DAT & SDA) ? 1 : 0)
176#define I2C_SDA(x) { if (x) __I2C_DAT |= SDA; else __I2C_DAT &= ~SDA; }
177#define I2C_SCL(x) { if (x) __I2C_DAT |= SCL; else __I2C_DAT &= ~SCL; }
178#define I2C_DELAY { udelay(5); }
179#define I2C_ACTIVE { __I2C_DIR |= SDA; }
180#define I2C_TRISTATE { __I2C_DIR &= ~SDA; }
wdenkdb2f721f2003-03-06 00:58:30 +0000181
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
wdenkdb2f721f2003-03-06 00:58:30 +0000183
184/*-----------------------------------------------------------------------
185 * defines we need to get FEC running
wdenk945af8d2003-07-16 21:53:01 +0000186 */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200187#define CONFIG_FEC_ENET 1 /* Ethernet only via FEC */
188#define FEC_ENET 1 /* eth.c needs it that way... */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#define CONFIG_SYS_DISCOVER_PHY 1
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200190#define CONFIG_MII 1
TsiChung Liew0f3ba7e2008-03-30 01:22:13 -0500191#define CONFIG_MII_INIT 1
wdenkdb2f721f2003-03-06 00:58:30 +0000192#define CONFIG_PHY_ADDR 31
wdenk945af8d2003-07-16 21:53:01 +0000193
wdenkdb2f721f2003-03-06 00:58:30 +0000194/*-----------------------------------------------------------------------
195 * adresses
wdenk945af8d2003-07-16 21:53:01 +0000196 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200198#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenk945af8d2003-07-16 21:53:01 +0000200
wdenkdb2f721f2003-03-06 00:58:30 +0000201/*-----------------------------------------------------------------------
202 * Start addresses for the final memory configuration
203 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkdb2f721f2003-03-06 00:58:30 +0000205 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_SYS_SDRAM_BASE 0x00000000
207#define CONFIG_SYS_FLASH_BASE 0x80000000
wdenk945af8d2003-07-16 21:53:01 +0000208
wdenkdb2f721f2003-03-06 00:58:30 +0000209/*-----------------------------------------------------------------------
210 * Definitions for initial stack pointer and data area (in DPRAM)
211 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200213#define CONFIG_SYS_INIT_RAM_SIZE 0x2f00 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200214#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#define CONFIG_SYS_INIT_VPD_SIZE 256 /* size in bytes reserved for vpd buffer */
216#define CONFIG_SYS_INIT_VPD_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_VPD_SIZE)
217#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_VPD_OFFSET-8)
wdenkdb2f721f2003-03-06 00:58:30 +0000218
219/*-----------------------------------------------------------------------
220 * Cache Configuration
221 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeligera5562902007-07-08 15:31:57 -0500223#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenkdb2f721f2003-03-06 00:58:30 +0000225#endif
226
227/* Interrupt level assignments.
228*/
229#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */
230
wdenkdb2f721f2003-03-06 00:58:30 +0000231/*-----------------------------------------------------------------------
232 * Debug Enable Register
233 *-----------------------------------------------------------------------
234 *
235 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236#define CONFIG_SYS_DER 0 /* used in start.S */
wdenkdb2f721f2003-03-06 00:58:30 +0000237
238/*-----------------------------------------------------------------------
239 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
240 *-----------------------------------------------------------------------
wdenk945af8d2003-07-16 21:53:01 +0000241 * set up PLPRCR (PLL, Low-Power, and Reset Control Register)
242 * 12 MF calculated Multiplication factor
243 * 4 0 0000
244 * 1 SPLSS 0 System PLL lock status sticky
245 * 1 TEXPS 1 Timer expired status
246 * 1 0 0
247 * 1 TMIST 0 Timers interrupt status
248 * 1 0 0
249 * 1 CSRC 0 Clock source (0=DFNH, 1=DFNL)
250 * 2 LPM 00 Low-power modes
251 * 1 CSR 0 Checkstop reset enable
252 * 1 LOLRE 0 Loss-of-lock reset enable
253 * 1 FIOPD 0 Force I/O pull down
wdenk42d1f032003-10-15 23:53:47 +0000254 * 5 0 00000
wdenkdb2f721f2003-03-06 00:58:30 +0000255 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200256#define CONFIG_SYS_PLPRCR (PLPRCR_TEXPS | ((CONFIG_SYS_MF-1)<<20))
wdenk945af8d2003-07-16 21:53:01 +0000257
wdenkdb2f721f2003-03-06 00:58:30 +0000258/*-----------------------------------------------------------------------
259 * SYPCR - System Protection Control 11-9
260 * SYPCR can only be written once after reset!
261 *-----------------------------------------------------------------------
wdenk945af8d2003-07-16 21:53:01 +0000262 * set up SYPCR:
263 * 16 SWTC 0xffff Software watchdog timer count
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200264 * 8 BMT 0xff Bus monitor timing
wdenk945af8d2003-07-16 21:53:01 +0000265 * 1 BME 1 Bus monitor enable
266 * 3 0 000
267 * 1 SWF 1 Software watchdog freeze
268 * 1 SWE 0/1 Software watchdog enable
269 * 1 SWRI 0/1 Software watchdog reset/interrupt select (1=HRESET)
270 * 1 SWP 0/1 Software watchdog prescale (1=/2048)
wdenkdb2f721f2003-03-06 00:58:30 +0000271 */
272#if defined (CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200274 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
wdenkdb2f721f2003-03-06 00:58:30 +0000275#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200276 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
wdenkdb2f721f2003-03-06 00:58:30 +0000277#endif
278
279/*-----------------------------------------------------------------------
280 * SIUMCR - SIU Module Configuration 11-6
281 *-----------------------------------------------------------------------
wdenk945af8d2003-07-16 21:53:01 +0000282 * set up SIUMCR
283 * 1 EARB 0 External arbitration
284 * 3 EARP 000 External arbitration request priority
285 * 4 0 0000
286 * 1 DSHW 0 Data show cycles
287 * 2 DBGC 00 Debug pin configuration
288 * 2 DBPC 00 Debug port pins configuration
289 * 1 0 0
290 * 1 FRC 0 FRZ pin configuration
291 * 1 DLK 0 Debug register lock
292 * 1 OPAR 0 Odd parity
293 * 1 PNCS 0 Parity enable for non memory controller regions
294 * 1 DPC 0 Data parity pins configuration
295 * 1 MPRE 0 Multiprocessor reservation enable
296 * 2 MLRC 11 Multi level reservation control (00=IRQ4, 01=3State, 10=KR/RETRY, 11=SPKROUT)
297 * 1 AEME 0 Async external master enable
298 * 1 SEME 0 Sync external master enable
299 * 1 BSC 0 Byte strobe configuration
300 * 1 GB5E 0 GPL_B5 enable
wdenk42d1f032003-10-15 23:53:47 +0000301 * 1 B2DD 0 Bank 2 double drive
302 * 1 B3DD 0 Bank 3 double drive
wdenk945af8d2003-07-16 21:53:01 +0000303 * 4 0 0000
wdenkdb2f721f2003-03-06 00:58:30 +0000304 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305#define CONFIG_SYS_SIUMCR (SIUMCR_MLRC11)
wdenk945af8d2003-07-16 21:53:01 +0000306
wdenkdb2f721f2003-03-06 00:58:30 +0000307/*-----------------------------------------------------------------------
308 * TBSCR - Time Base Status and Control 11-26
309 *-----------------------------------------------------------------------
310 * Clear Reference Interrupt Status, Timebase freezing enabled
311 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200312#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenkdb2f721f2003-03-06 00:58:30 +0000313
314/*-----------------------------------------------------------------------
315 * PISCR - Periodic Interrupt Status and Control 11-31
316 *-----------------------------------------------------------------------
317 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
318 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200319#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE)
wdenkdb2f721f2003-03-06 00:58:30 +0000320
321/*-----------------------------------------------------------------------
322 * SCCR - System Clock and reset Control Register 15-27
323 *-----------------------------------------------------------------------
wdenk945af8d2003-07-16 21:53:01 +0000324 * set up SCCR (System Clock and Reset Control Register)
325 * 1 0 0
326 * 2 COM 11 Clock output module (00=full, 01=half, 11=off)
327 * 3 0 000
328 * 1 TBS 1 Timebase source (0=OSCCLK, 1=GCLK2)
329 * 1 RTDIV 0 Real-time clock divide (0=/4, 1=/512)
330 * 1 RTSEL 0 Real-time clock select (0=OSCM, 1=EXTCLK)
331 * 1 CRQEN 0 CPM request enable
332 * 1 PRQEN 0 Power management request enable
333 * 2 0 00
334 * 2 EBDF xx External bus division factor
335 * 2 0 00
336 * 2 DFSYNC 00 Division factor for SYNCLK
337 * 2 DFBRG 00 Division factor for BRGCLK
338 * 3 DFNL 000 Division factor low frequency
339 * 3 DFNH 000 Division factor high frequency
340 * 5 0 00000
wdenkdb2f721f2003-03-06 00:58:30 +0000341 */
342#define SCCR_MASK 0
wdenk42dfe7a2004-03-14 22:25:36 +0000343#ifdef CONFIG_EBDF
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200344 #define CONFIG_SYS_SCCR (SCCR_COM11 | SCCR_TBS | SCCR_EBDF01)
wdenk945af8d2003-07-16 21:53:01 +0000345#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200346 #define CONFIG_SYS_SCCR (SCCR_COM11 | SCCR_TBS)
wdenk945af8d2003-07-16 21:53:01 +0000347#endif
wdenkdb2f721f2003-03-06 00:58:30 +0000348
349/*-----------------------------------------------------------------------
350 * Chip Select 0 - FLASH
351 *-----------------------------------------------------------------------
352 * Preliminary Values
353 */
354/* FLASH timing: CSNT=1 ACS=10 BIH=1 SCY=4 SETA=0 TLRX=1 EHTR=1 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200355#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_4_CLK | OR_TRLX | OR_EHTR)
356#define CONFIG_SYS_OR0_PRELIM (-CONFIG_SYS_FLASH_MAX | CONFIG_SYS_OR_TIMING_FLASH)
357#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V )
wdenk945af8d2003-07-16 21:53:01 +0000358
wdenkdb2f721f2003-03-06 00:58:30 +0000359/*-----------------------------------------------------------------------
360 * misc
361 *-----------------------------------------------------------------------
362 *
363 */
364/*
365 * Set the autoboot delay in seconds. A delay of -1 disables autoboot
366 */
367#define CONFIG_BOOTDELAY 5
368
369/*
370 * Pass the clock frequency to the Linux kernel in units of MHz
371 */
372#define CONFIG_CLOCKS_IN_MHZ
373
374#define CONFIG_PREBOOT \
375 "echo;echo"
376
377#undef CONFIG_BOOTARGS
378#define CONFIG_BOOTCOMMAND \
379 "bootp;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100380 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
381 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
wdenkdb2f721f2003-03-06 00:58:30 +0000382 "bootm"
383
384/*
385 * BOOTP options
386 */
Jon Loeliger37d4bb72007-07-09 21:38:02 -0500387#define CONFIG_BOOTP_SUBNETMASK
388#define CONFIG_BOOTP_GATEWAY
389#define CONFIG_BOOTP_HOSTNAME
390#define CONFIG_BOOTP_BOOTPATH
391#define CONFIG_BOOTP_BOOTFILESIZE
wdenk42d1f032003-10-15 23:53:47 +0000392
wdenkdb2f721f2003-03-06 00:58:30 +0000393
394/*
395 * Set default IP stuff just to get bootstrap entries into the
Wolfgang Denk74de7ae2009-04-01 23:34:12 +0200396 * environment so that we can source the full default environment.
wdenkdb2f721f2003-03-06 00:58:30 +0000397 */
398#define CONFIG_ETHADDR 9a:52:63:15:85:25
399#define CONFIG_SERVERIP 10.0.4.200
400#define CONFIG_IPADDR 10.0.4.111
wdenk945af8d2003-07-16 21:53:01 +0000401
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200402#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
wdenk945af8d2003-07-16 21:53:01 +0000403
wdenkdb2f721f2003-03-06 00:58:30 +0000404/*
405 * For booting Linux, the board info and command line data
406 * have to be in the first 8 MB of memory, since this is
407 * the maximum mapped by the Linux kernel during initialization.
408 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200409#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkdb2f721f2003-03-06 00:58:30 +0000410
wdenkdb2f721f2003-03-06 00:58:30 +0000411#endif /* __CONFIG_H */