blob: d31c13796735304756be974703316fbe1863ce70 [file] [log] [blame]
Anatolij Gustschina3921ee2010-04-24 19:27:09 +02001/*
2 * (C) Copyright 2009-2010
3 * Michael Weiß, ifm ecomatic gmbh, michael.weiss@ifm.com
4 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
Anatolij Gustschina3921ee2010-04-24 19:27:09 +02006 */
7
8/*
9 * pdm360ng board configuration file
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15#define CONFIG_PDM360NG 1
16
17/*
18 * Memory map for the PDM360NG board:
19 *
20 * 0x0000_0000 - 0x1FFF_FFFF DDR RAM (512 MB)
21 * 0x2000_0000 - 0x3FFF_FFFF reserved (DDR RAM (512 MB)
22 * 0x5000_0000 - 0x5001_FFFF SRAM (128 KB)
23 * 0x5004_0000 - 0x5005_FFFF MRAM (CS2) (128 KB)
24 * 0x8000_0000 - 0x803F_FFFF IMMR (4 MB)
25 * 0xF000_0000 - 0xF7FF_FFFF NOR FLASH (CS0) (128 MB)
26 * 0xF800_0000 - 0xFFFF_FFFF NOR FLASH (CS1) (128 MB) optional
27 */
28
29/*
30 * High Level Configuration Options
31 */
32#define CONFIG_E300 1 /* E300 Family */
33#define CONFIG_MPC512X 1 /* MPC512X family */
34#define CONFIG_FSL_DIU_FB 1 /* FSL DIU */
35
Wolfgang Denk2ae18242010-10-06 09:05:45 +020036#define CONFIG_SYS_TEXT_BASE 0xF0000000
37
Anatolij Gustschina3921ee2010-04-24 19:27:09 +020038/* Used for silent command in environment */
39#define CONFIG_SYS_DEVICE_NULLDEV
40#define CONFIG_SILENT_CONSOLE
41
42/* Video */
43#define CONFIG_VIDEO
44
45#if defined(CONFIG_VIDEO)
46#define CONFIG_CFB_CONSOLE
47#define CONFIG_VGA_AS_SINGLE_DEVICE
48#define CONFIG_SPLASH_SCREEN
49#define CONFIG_VIDEO_LOGO
50#define CONFIG_VIDEO_BMP_RLE8
Anatolij Gustschina3921ee2010-04-24 19:27:09 +020051#endif
52
53#define CONFIG_SYS_MPC512X_CLKIN 33333333 /* in Hz */
54
Anatolij Gustschina3921ee2010-04-24 19:27:09 +020055#define CONFIG_MISC_INIT_R
56
57#define CONFIG_SYS_IMMR 0x80000000
58#define CONFIG_SYS_DIU_ADDR ((CONFIG_SYS_IMMR) + 0x2100)
59
60/*
61 * DDR Setup
62 */
63
64/* DDR is system memory */
65#define CONFIG_SYS_DDR_BASE 0x00000000
66#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
67#define CONFIG_SYS_MAX_RAM_SIZE 0x40000000
68
69/* DDR pin mux and slew rate */
70#define CONFIG_SYS_IOCTRL_MUX_DDR 0x00000012
71
72/* Manually set all parameters as there's no SPD etc. */
73/*
74 * DDR Controller Configuration for Micron DDR2 SDRAM MT47H128M8-3
75 *
76 * SYS_CFG:
77 * [31:31] MDDRC Soft Reset: Diabled
78 * [30:30] DRAM CKE pin: Enabled
79 * [29:29] DRAM CLK: Enabled
80 * [28:28] Command Mode: Enabled (For initialization only)
81 * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10]
82 * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10]
83 * [20:19] Read Test: DON'T USE
84 * [18:18] Self Refresh: Enabled
85 * [17:17] 16bit Mode: Disabled
86 * [16:13] Read Delay: 3
87 * [12:12] Half DQS Delay: Disabled
88 * [11:11] Quarter DQS Delay: Disabled
89 * [10:08] Write Delay: 2
90 * [07:07] Early ODT: Disabled
91 * [06:06] On DIE Termination: Enabled
92 * [05:05] FIFO Overflow Clear: DON'T USE here
93 * [04:04] FIFO Underflow Clear: DON'T USE here
94 * [03:03] FIFO Overflow Pending: DON'T USE here
95 * [02:02] FIFO Underlfow Pending: DON'T USE here
96 * [01:01] FIFO Overlfow Enabled: Enabled
97 * [00:00] FIFO Underflow Enabled: Enabled
98 * TIME_CFG0
99 * [31:16] DRAM Refresh Time: 0 CSB clocks
100 * [15:8] DRAM Command Time: 0 CSB clocks
101 * [07:00] DRAM Precharge Time: 0 CSB clocks
102 * TIME_CFG1
103 * [31:26] DRAM tRFC:
104 * [25:21] DRAM tWR1:
105 * [20:17] DRAM tWRT1:
106 * [16:11] DRAM tDRR:
107 * [10:05] DRAM tRC:
108 * [04:00] DRAM tRAS:
109 * TIME_CFG2
110 * [31:28] DRAM tRCD:
111 * [27:23] DRAM tFAW:
112 * [22:19] DRAM tRTW1:
113 * [18:15] DRAM tCCD:
114 * [14:10] DRAM tRTP:
115 * [09:05] DRAM tRP:
116 * [04:00] DRAM tRPA
117 */
118#define CONFIG_SYS_MDDRC_SYS_CFG 0xEA804A40
119#define CONFIG_SYS_MDDRC_TIME_CFG0 0x030C3D2E
120#define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168
121#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864
122
123/*
124 * Alternative 1: small RAM (128 MB) configuration
125 */
126#define CONFIG_SYS_MDDRC_SYS_CFG_ALT1 0xE8604A40
127#define CONFIG_SYS_MDDRC_TIME_CFG0_ALT1 0x030C3D2E
128#define CONFIG_SYS_MDDRC_TIME_CFG1_ALT1 0x3CEC1168
129#define CONFIG_SYS_MDDRC_TIME_CFG2_ALT1 0x33310863
130
131#define CONFIG_SYS_MDDRC_SYS_CFG_EN 0xF0000000
132
133#define CONFIG_SYS_DDRCMD_NOP 0x01380000
134#define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400
135#define CONFIG_SYS_DDRCMD_EM2 0x01020000 /* EMR2 */
136#define CONFIG_SYS_DDRCMD_EM3 0x01030000 /* EMR3 */
137/* EMR with 150 ohm ODT todo: verify */
138#define CONFIG_SYS_DDRCMD_EN_DLL 0x01010040
139#define CONFIG_SYS_DDRCMD_RES_DLL 0x01000100
140#define CONFIG_SYS_DDRCMD_RFSH 0x01080000
141#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432
142/* EMR with 150 ohm ODT todo: verify */
143#define CONFIG_SYS_DDRCMD_OCD_DEFAULT 0x010107C0
144/* EMR new command with 150 ohm ODT todo: verify */
145#define CONFIG_SYS_DDRCMD_OCD_EXIT 0x01010440
146
147/* DDR Priority Manager Configuration */
148#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777
149#define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000
150#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001
151#define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC
152#define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA
153#define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666
154#define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555
155#define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444
156#define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444
157#define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555
158#define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558
159#define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111
160#define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122
161#define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa
162#define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa
163#define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666
164#define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666
165#define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111
166#define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111
167#define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111
168#define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111
169#define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111
170#define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111
171
172/*
173 * NOR FLASH on the Local Bus
174 */
175#define CONFIG_SYS_FLASH_CFI /* use Common Flash Interface */
176#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
177#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
178
179#define CONFIG_SYS_FLASH_BASE 0xF0000000 /* start of FLASH-Bank0 */
180#define CONFIG_SYS_FLASH_SIZE 0x08000000 /* max size of a Bank */
181/* start of FLASH-Bank1 */
182#define CONFIG_SYS_FLASH1_BASE (CONFIG_SYS_FLASH_BASE + \
183 CONFIG_SYS_FLASH_SIZE)
184#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */
185#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
186#define CONFIG_SYS_FLASH_BANKS_LIST \
187 {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH1_BASE}
188
189#define CONFIG_SYS_SRAM_BASE 0x50000000
190#define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */
191
Anatolij Gustschin676c6692013-02-08 00:03:44 +0000192#define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH1_BASE
193#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_FLASH_SIZE
194
Anatolij Gustschina3921ee2010-04-24 19:27:09 +0200195/* ALE active low, data size 4 bytes */
196#define CONFIG_SYS_CS0_CFG 0x05059350
197/* ALE active low, data size 4 bytes */
198#define CONFIG_SYS_CS1_CFG 0x05059350
199
200#define CONFIG_SYS_MRAM_BASE 0x50040000
201#define CONFIG_SYS_MRAM_SIZE 0x00020000
Anatolij Gustschin676c6692013-02-08 00:03:44 +0000202#define CONFIG_SYS_CS2_START CONFIG_SYS_MRAM_BASE
203#define CONFIG_SYS_CS2_SIZE CONFIG_SYS_MRAM_SIZE
204
Anatolij Gustschina3921ee2010-04-24 19:27:09 +0200205/* ALE active low, data size 4 bytes */
206#define CONFIG_SYS_CS2_CFG 0x05059110
207
208/* alt. CS timing for CS0, CS1, CS2 */
209#define CONFIG_SYS_CS_ALETIMING 0x00000007
210
211/*
212 * NAND FLASH
213 */
214#define CONFIG_CMD_NAND /* enable NAND support */
215#define CONFIG_NAND_MPC5121_NFC
216#define CONFIG_SYS_NAND_BASE 0x40000000
Anatolij Gustschina3921ee2010-04-24 19:27:09 +0200217#define CONFIG_SYS_MAX_NAND_DEVICE 1
Anatolij Gustschina3921ee2010-04-24 19:27:09 +0200218#define CONFIG_SYS_NAND_SELECT_DEVICE /* driver supports mutipl. chips */
219
220/*
221 * Configuration parameters for MPC5121 NAND driver
222 */
223#define CONFIG_FSL_NFC_WIDTH 1
224#define CONFIG_FSL_NFC_WRITE_SIZE 2048
225#define CONFIG_FSL_NFC_SPARE_SIZE 64
226#define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
227
228/*
229 * Dynamic MTD partition support
230 */
231#define CONFIG_CMD_MTDPARTS
232#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
233#define CONFIG_FLASH_CFI_MTD
234#define MTDIDS_DEFAULT "nor0=f0000000.flash,nor1=f8000000.flash," \
235 "nand0=MPC5121 NAND"
236
237/*
238 * Flash layout
239 */
240#define MTDPARTS_DEFAULT "mtdparts=f0000000.flash:512k(u-boot)," \
241 "256k(environment1)," \
242 "256k(environment2)," \
243 "256k(splash-factory)," \
244 "2m(FIT: recovery)," \
245 "4608k(fs-recovery)," \
246 "256k(splash-customer),"\
247 "5m(FIT: kernel+dtb)," \
248 "64m(rootfs squash)ro," \
249 "51m(userfs ubi);" \
250 "f8000000.flash:-(unused);" \
251 "MPC5121 NAND:1024m(extended-userfs)"
252
253/*
254 * Override partitions in device tree using info
255 * in "mtdparts" environment variable
256 */
257#ifdef CONFIG_CMD_MTDPARTS
258#define CONFIG_FDT_FIXUP_PARTITIONS
259#endif
260
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200261#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of monitor */
Anatolij Gustschina3921ee2010-04-24 19:27:09 +0200262#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* 512 kB for monitor */
263#ifdef CONFIG_FSL_DIU_FB
264#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* for malloc */
265#else
266#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
267#endif
268
269/*
270 * Serial Port
271 */
272#define CONFIG_CONS_INDEX 1
273
274/*
275 * Serial console configuration
276 */
277#define CONFIG_PSC_CONSOLE 6 /* console is on PSC6 */
278#if CONFIG_PSC_CONSOLE != 6
279#error CONFIG_PSC_CONSOLE must be 6
280#endif
281
282#define CONSOLE_FIFO_TX_SIZE FIFOC_PSC6_TX_SIZE
283#define CONSOLE_FIFO_TX_ADDR FIFOC_PSC6_TX_ADDR
284#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC6_RX_SIZE
285#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC6_RX_ADDR
286
287/*
Anatolij Gustschine5f53862013-02-08 00:03:45 +0000288 * Clocks in use
289 */
290#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
291 CLOCK_SCCR1_LPC_EN | \
292 CLOCK_SCCR1_NFC_EN | \
293 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
294 CLOCK_SCCR1_PSCFIFO_EN | \
295 CLOCK_SCCR1_DDR_EN | \
296 CLOCK_SCCR1_FEC_EN | \
297 CLOCK_SCCR1_TPR_EN)
298
299#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
300 CLOCK_SCCR2_SPDIF_EN | \
301 CLOCK_SCCR2_DIU_EN | \
302 CLOCK_SCCR2_I2C_EN)
303
304/*
Anatolij Gustschina3921ee2010-04-24 19:27:09 +0200305 * Used PSC UART devices
306 */
Anatolij Gustschina3921ee2010-04-24 19:27:09 +0200307#define CONFIG_SYS_PSC1
308#define CONFIG_SYS_PSC4
309#define CONFIG_SYS_PSC6
310
311/*
312 * Co-processor communication parameters
313 */
314#define CONFIG_SYS_PDM360NG_COPROC_READ_DELAY 5000
315#define CONFIG_SYS_PDM360NG_COPROC_BAUDRATE 38400
316
317/*
318 * I2C
319 */
320#define CONFIG_HARD_I2C /* I2C with hardware support */
321#define CONFIG_I2C_MULTI_BUS
322#define CONFIG_I2C_CMD_TREE
323/* I2C speed and slave address */
324#define CONFIG_SYS_I2C_SPEED 100000
325#define CONFIG_SYS_I2C_SLAVE 0x7F
326
327/*
Benoît Thébaudeau83306922013-04-23 10:17:42 +0000328 * IIM - IC Identification Module
329 */
330#undef CONFIG_FSL_IIM
331
332/*
Anatolij Gustschina3921ee2010-04-24 19:27:09 +0200333 * EEPROM configuration
334 */
335#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16-bit EEPROM addr */
336#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* ST AT24C01 */
337#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10ms of delay */
338#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16-Byte Write Mode */
339
340/*
341 * MAC addr in EEPROM
342 */
343#define CONFIG_SYS_I2C_EEPROM_BUS_NUM 0
344#define CONFIG_SYS_I2C_EEPROM_MAC_OFFSET 0x10
345/*
346 * Enabled only to delete "ethaddr" before testing
347 * "ethaddr" setting from EEPROM
348 */
349#define CONFIG_ENV_OVERWRITE
350
351/*
352 * Ethernet configuration
353 */
354#define CONFIG_MPC512x_FEC 1
Anatolij Gustschina3921ee2010-04-24 19:27:09 +0200355#define CONFIG_PHY_ADDR 0x1F
356#define CONFIG_MII 1 /* MII PHY management */
357#define CONFIG_FEC_AN_TIMEOUT 1
358#define CONFIG_HAS_ETH0
359
360/*
361 * Configure on-board RTC
362 */
363#define CONFIG_RTC_M41T62 /* use M41T00 rtc via i2c */
364#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
365
366/*
367 * Environment
368 */
369#define CONFIG_ENV_IS_IN_FLASH 1
370/* This has to be a multiple of the Flash sector size */
371#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
372 CONFIG_SYS_MONITOR_LEN)
373#define CONFIG_ENV_SIZE 0x2000
374#define CONFIG_ENV_SECT_SIZE 0x40000 /* one sector (256K) for env */
375
376/* Address and size of Redundant Environment Sector */
377#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
378#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
379
380#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
381#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
382
383#include <config_cmd_default.h>
384
385#define CONFIG_CMD_ASKENV
386#define CONFIG_CMD_DATE
387#define CONFIG_CMD_DHCP
388#define CONFIG_CMD_EEPROM
389#define CONFIG_CMD_I2C
390#define CONFIG_CMD_MII
391#define CONFIG_CMD_PING
392#define CONFIG_CMD_REGINFO
393
Benoît Thébaudeau83306922013-04-23 10:17:42 +0000394#undef CONFIG_CMD_FUSE
395
Anatolij Gustschina3921ee2010-04-24 19:27:09 +0200396#ifdef CONFIG_VIDEO
397#define CONFIG_CMD_BMP
398#endif
399
400/*
401 * Miscellaneous configurable options
402 */
403#define CONFIG_SYS_LONGHELP /* undef to save memory */
404#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
405#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
406
407#ifdef CONFIG_CMD_KGDB
408 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
409#else
410 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
411#endif
412
413/* Print Buffer Size */
414#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
415/* Max number of command args */
416#define CONFIG_SYS_MAXARGS 16
417/* Boot Argument Buffer Size */
418#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
419/* Decrementer freq: 1ms ticks */
420#define CONFIG_SYS_HZ 1000
421
422/*
423 * For booting Linux, the board info and command line data
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700424 * have to be in the first 256 MB of memory, since this is
Anatolij Gustschina3921ee2010-04-24 19:27:09 +0200425 * the maximum mapped by the Linux kernel during initialization.
426 */
427/* Initial Memory map for Linux */
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700428#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
Anatolij Gustschina3921ee2010-04-24 19:27:09 +0200429
430/* Cache Configuration */
431#define CONFIG_SYS_DCACHE_SIZE 32768
432#define CONFIG_SYS_CACHELINE_SIZE 32
433#ifdef CONFIG_CMD_KGDB
434/* log base 2 of the above value */
435#define CONFIG_SYS_CACHELINE_SHIFT 5
436#endif
437
438#define CONFIG_SYS_HID0_INIT 0x000000000
439#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | HID0_ICE)
440#define CONFIG_SYS_HID2 HID2_HBE
441
442#define CONFIG_HIGH_BATS 1 /* High BATs supported */
443
Anatolij Gustschina3921ee2010-04-24 19:27:09 +0200444#ifdef CONFIG_CMD_KGDB
445#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
446#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
447#endif
448
Anatolij Gustschin29fd7ce2010-04-24 19:27:11 +0200449/* POST support */
450#define CONFIG_POST (CONFIG_SYS_POST_COPROC)
Anatolij Gustschin29fd7ce2010-04-24 19:27:11 +0200451
Anatolij Gustschina3921ee2010-04-24 19:27:09 +0200452/*
453 * Environment Configuration
454 */
455#define CONFIG_TIMESTAMP
456
457#define CONFIG_HOSTNAME pdm360ng
458/* default location for tftp and bootm */
459#define CONFIG_LOADADDR 400000
460
461#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
462
463#define CONFIG_PREBOOT "echo;" \
464 "echo PDM360NG SAMPLE;" \
465 "echo"
466
467#define CONFIG_BOOTCOMMAND "run env_cont"
468
469#define CONFIG_OF_LIBFDT 1
470#define CONFIG_OF_BOARD_SETUP 1
471#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1
472#define CONFIG_FIT
473#define CONFIG_FIT_VERBOSE
474
475#define OF_CPU "PowerPC,5121@0"
476#define OF_SOC_COMPAT "fsl,mpc5121-immr"
477#define OF_TBCLK (bd->bi_busfreq / 4)
478#define OF_STDOUT_PATH "/soc@80000000/serial@11600"
479
480/*
481 * Include common options for all mpc5121 boards
482 */
483#include "mpc5121-common.h"
484
485#endif /* __CONFIG_H */