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wdenkfe8c2802002-11-03 00:38:21 +00001/*
wdenk8655b6f2004-10-09 23:25:58 +00002 * MPC823 and PXA LCD Controller
wdenkfe8c2802002-11-03 00:38:21 +00003 *
4 * Modeled after video interface by Paolo Scaffardi
5 *
6 *
7 * (C) Copyright 2001
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +020010 * SPDX-License-Identifier: GPL-2.0+
wdenkfe8c2802002-11-03 00:38:21 +000011 */
12
13#ifndef _LCD_H_
14#define _LCD_H_
15
wdenk682011f2003-06-03 23:54:09 +000016extern char lcd_is_enabled;
17
wdenk8655b6f2004-10-09 23:25:58 +000018extern int lcd_line_length;
wdenk8655b6f2004-10-09 23:25:58 +000019
Alessandro Rubini61117222009-07-19 17:52:27 +020020extern struct vidinfo panel_info;
21
Jeroen Hofstee6b035142013-01-12 12:07:56 +000022void lcd_ctrl_init(void *lcdbase);
23void lcd_enable(void);
Alessandro Rubini61117222009-07-19 17:52:27 +020024
25/* setcolreg used in 8bpp/16bpp; initcolregs used in monochrome */
Jeroen Hofstee6b035142013-01-12 12:07:56 +000026void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue);
27void lcd_initcolregs(void);
Alessandro Rubini61117222009-07-19 17:52:27 +020028
Jeroen Hofstee6b035142013-01-12 12:07:56 +000029int lcd_getfgcolor(void);
Alessandro Rubini61117222009-07-19 17:52:27 +020030
31/* gunzip_bmp used if CONFIG_VIDEO_BMP_GZIP */
Piotr Wilczekf7ef9d62013-06-05 08:14:30 +020032struct bmp_image *gunzip_bmp(unsigned long addr, unsigned long *lenp,
33 void **alloc_addr);
Jeroen Hofstee6b035142013-01-12 12:07:56 +000034int bmp_display(ulong addr, int x, int y);
wdenk8655b6f2004-10-09 23:25:58 +000035
Simon Glass9a8efc42012-10-30 13:40:18 +000036/**
37 * Set whether we need to flush the dcache when changing the LCD image. This
38 * defaults to off.
39 *
40 * @param flush non-zero to flush cache after update, 0 to skip
41 */
42void lcd_set_flush_dcache(int flush);
43
wdenk8655b6f2004-10-09 23:25:58 +000044#if defined CONFIG_MPC823
45/*
46 * LCD controller stucture for MPC823 CPU
47 */
48typedef struct vidinfo {
49 ushort vl_col; /* Number of columns (i.e. 640) */
50 ushort vl_row; /* Number of rows (i.e. 480) */
51 ushort vl_width; /* Width of display area in millimeters */
52 ushort vl_height; /* Height of display area in millimeters */
53
54 /* LCD configuration register */
55 u_char vl_clkp; /* Clock polarity */
56 u_char vl_oep; /* Output Enable polarity */
57 u_char vl_hsp; /* Horizontal Sync polarity */
58 u_char vl_vsp; /* Vertical Sync polarity */
59 u_char vl_dp; /* Data polarity */
60 u_char vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8 */
61 u_char vl_lbw; /* LCD Bus width, 0 = 4, 1 = 8 */
62 u_char vl_splt; /* Split display, 0 = single-scan, 1 = dual-scan */
63 u_char vl_clor; /* Color, 0 = mono, 1 = color */
64 u_char vl_tft; /* 0 = passive, 1 = TFT */
65
66 /* Horizontal control register. Timing from data sheet */
67 ushort vl_wbl; /* Wait between lines */
68
69 /* Vertical control register */
70 u_char vl_vpw; /* Vertical sync pulse width */
71 u_char vl_lcdac; /* LCD AC timing */
72 u_char vl_wbf; /* Wait between frames */
73} vidinfo_t;
74
Marek Vasutabc20ab2011-11-26 07:20:07 +010075#elif defined(CONFIG_CPU_PXA25X) || defined(CONFIG_CPU_PXA27X) || \
76 defined CONFIG_CPU_MONAHANS
wdenk8655b6f2004-10-09 23:25:58 +000077/*
78 * PXA LCD DMA descriptor
79 */
80struct pxafb_dma_descriptor {
81 u_long fdadr; /* Frame descriptor address register */
82 u_long fsadr; /* Frame source address register */
83 u_long fidr; /* Frame ID register */
84 u_long ldcmd; /* Command register */
85};
86
87/*
88 * PXA LCD info
89 */
90struct pxafb_info {
91
92 /* Misc registers */
93 u_long reg_lccr3;
94 u_long reg_lccr2;
95 u_long reg_lccr1;
96 u_long reg_lccr0;
97 u_long fdadr0;
98 u_long fdadr1;
99
100 /* DMA descriptors */
101 struct pxafb_dma_descriptor * dmadesc_fblow;
102 struct pxafb_dma_descriptor * dmadesc_fbhigh;
103 struct pxafb_dma_descriptor * dmadesc_palette;
104
105 u_long screen; /* physical address of frame buffer */
106 u_long palette; /* physical address of palette memory */
107 u_int palette_size;
108};
109
110/*
111 * LCD controller stucture for PXA CPU
112 */
113typedef struct vidinfo {
114 ushort vl_col; /* Number of columns (i.e. 640) */
115 ushort vl_row; /* Number of rows (i.e. 480) */
116 ushort vl_width; /* Width of display area in millimeters */
117 ushort vl_height; /* Height of display area in millimeters */
118
119 /* LCD configuration register */
120 u_char vl_clkp; /* Clock polarity */
121 u_char vl_oep; /* Output Enable polarity */
122 u_char vl_hsp; /* Horizontal Sync polarity */
123 u_char vl_vsp; /* Vertical Sync polarity */
124 u_char vl_dp; /* Data polarity */
125 u_char vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */
126 u_char vl_lbw; /* LCD Bus width, 0 = 4, 1 = 8 */
127 u_char vl_splt; /* Split display, 0 = single-scan, 1 = dual-scan */
128 u_char vl_clor; /* Color, 0 = mono, 1 = color */
129 u_char vl_tft; /* 0 = passive, 1 = TFT */
130
131 /* Horizontal control register. Timing from data sheet */
132 ushort vl_hpw; /* Horz sync pulse width */
133 u_char vl_blw; /* Wait before of line */
134 u_char vl_elw; /* Wait end of line */
135
136 /* Vertical control register. */
137 u_char vl_vpw; /* Vertical sync pulse width */
138 u_char vl_bfw; /* Wait before of frame */
139 u_char vl_efw; /* Wait end of frame */
140
141 /* PXA LCD controller params */
142 struct pxafb_info pxa;
143} vidinfo_t;
144
Bo Shenf6b690e2012-05-25 00:59:58 +0000145#elif defined(CONFIG_ATMEL_LCD) || defined(CONFIG_ATMEL_HLCD)
Stelian Pop39cf4802008-05-09 21:57:18 +0200146
147typedef struct vidinfo {
Marek Vasut78459122011-10-24 23:41:00 +0000148 ushort vl_col; /* Number of columns (i.e. 640) */
149 ushort vl_row; /* Number of rows (i.e. 480) */
Stelian Pop39cf4802008-05-09 21:57:18 +0200150 u_long vl_clk; /* pixel clock in ps */
151
152 /* LCD configuration register */
153 u_long vl_sync; /* Horizontal / vertical sync */
154 u_long vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */
155 u_long vl_tft; /* 0 = passive, 1 = TFT */
Alexander Steincdfcedb2010-07-20 08:55:40 +0200156 u_long vl_cont_pol_low; /* contrast polarity is low */
Bo Shenf6b690e2012-05-25 00:59:58 +0000157 u_long vl_clk_pol; /* clock polarity */
Stelian Pop39cf4802008-05-09 21:57:18 +0200158
159 /* Horizontal control register. */
160 u_long vl_hsync_len; /* Length of horizontal sync */
161 u_long vl_left_margin; /* Time from sync to picture */
162 u_long vl_right_margin; /* Time from picture to sync */
163
164 /* Vertical control register. */
165 u_long vl_vsync_len; /* Length of vertical sync */
166 u_long vl_upper_margin; /* Time from sync to picture */
167 u_long vl_lower_margin; /* Time from picture to sync */
168
169 u_long mmio; /* Memory mapped registers */
170} vidinfo_t;
171
Donghwa Lee559a05c2012-04-05 19:36:15 +0000172#elif defined(CONFIG_EXYNOS_FB)
173
174enum {
175 FIMD_RGB_INTERFACE = 1,
176 FIMD_CPU_INTERFACE = 2,
177};
178
Donghwa Lee90464972012-05-09 19:23:46 +0000179enum exynos_fb_rgb_mode_t {
180 MODE_RGB_P = 0,
181 MODE_BGR_P = 1,
182 MODE_RGB_S = 2,
183 MODE_BGR_S = 3,
184};
185
Donghwa Lee559a05c2012-04-05 19:36:15 +0000186typedef struct vidinfo {
187 ushort vl_col; /* Number of columns (i.e. 640) */
188 ushort vl_row; /* Number of rows (i.e. 480) */
189 ushort vl_width; /* Width of display area in millimeters */
190 ushort vl_height; /* Height of display area in millimeters */
191
192 /* LCD configuration register */
193 u_char vl_freq; /* Frequency */
194 u_char vl_clkp; /* Clock polarity */
195 u_char vl_oep; /* Output Enable polarity */
196 u_char vl_hsp; /* Horizontal Sync polarity */
197 u_char vl_vsp; /* Vertical Sync polarity */
198 u_char vl_dp; /* Data polarity */
199 u_char vl_bpix; /* Bits per pixel */
200
201 /* Horizontal control register. Timing from data sheet */
202 u_char vl_hspw; /* Horz sync pulse width */
203 u_char vl_hfpd; /* Wait before of line */
204 u_char vl_hbpd; /* Wait end of line */
205
206 /* Vertical control register. */
207 u_char vl_vspw; /* Vertical sync pulse width */
208 u_char vl_vfpd; /* Wait before of frame */
209 u_char vl_vbpd; /* Wait end of frame */
210 u_char vl_cmd_allow_len; /* Wait end of frame */
211
Donghwa Lee559a05c2012-04-05 19:36:15 +0000212 unsigned int win_id;
213 unsigned int init_delay;
214 unsigned int power_on_delay;
215 unsigned int reset_delay;
216 unsigned int interface_mode;
217 unsigned int mipi_enabled;
Donghwa Lee5addfcf2012-07-02 01:16:05 +0000218 unsigned int dp_enabled;
Donghwa Lee559a05c2012-04-05 19:36:15 +0000219 unsigned int cs_setup;
220 unsigned int wr_setup;
221 unsigned int wr_act;
222 unsigned int wr_hold;
Donghwa Lee90464972012-05-09 19:23:46 +0000223 unsigned int logo_on;
224 unsigned int logo_width;
225 unsigned int logo_height;
226 unsigned long logo_addr;
227 unsigned int rgb_mode;
228 unsigned int resolution;
Donghwa Lee559a05c2012-04-05 19:36:15 +0000229
230 /* parent clock name(MPLL, EPLL or VPLL) */
231 unsigned int pclk_name;
232 /* ratio value for source clock from parent clock. */
233 unsigned int sclk_div;
234
235 unsigned int dual_lcd_enabled;
Donghwa Lee559a05c2012-04-05 19:36:15 +0000236} vidinfo_t;
237
238void init_panel_info(vidinfo_t *vid);
239
Guennadi Liakhovetskib245e652009-02-06 10:37:53 +0100240#else
241
242typedef struct vidinfo {
243 ushort vl_col; /* Number of columns (i.e. 160) */
244 ushort vl_row; /* Number of rows (i.e. 100) */
245
246 u_char vl_bpix; /* Bits per pixel, 0 = 1 */
247
248 ushort *cmap; /* Pointer to the colormap */
249
250 void *priv; /* Pointer to driver-specific data */
251} vidinfo_t;
252
Marek Vasutabc20ab2011-11-26 07:20:07 +0100253#endif /* CONFIG_MPC823, CONFIG_CPU_PXA25X, CONFIG_MCC200, CONFIG_ATMEL_LCD */
wdenk8655b6f2004-10-09 23:25:58 +0000254
Alessandro Rubini60e97412009-07-21 14:09:45 +0200255extern vidinfo_t panel_info;
256
wdenkfe8c2802002-11-03 00:38:21 +0000257/* Video functions */
258
wdenk8655b6f2004-10-09 23:25:58 +0000259#if defined(CONFIG_RBC823)
Jeroen Hofstee6b035142013-01-12 12:07:56 +0000260void lcd_disable(void);
wdenk8655b6f2004-10-09 23:25:58 +0000261#endif
262
Jeroen Hofstee6b035142013-01-12 12:07:56 +0000263void lcd_putc(const char c);
264void lcd_puts(const char *s);
265void lcd_printf(const char *fmt, ...);
Che-Liang Chiou02110902011-10-20 23:07:03 +0000266void lcd_clear(void);
267int lcd_display_bitmap(ulong bmp_image, int x, int y);
wdenkfe8c2802002-11-03 00:38:21 +0000268
Vadim Bendebury395166c2012-09-28 15:11:13 +0000269/**
270 * Get the width of the LCD in pixels
271 *
272 * @return width of LCD in pixels
273 */
274int lcd_get_pixel_width(void);
275
276/**
277 * Get the height of the LCD in pixels
278 *
279 * @return height of LCD in pixels
280 */
281int lcd_get_pixel_height(void);
282
283/**
284 * Get the number of text lines/rows on the LCD
285 *
286 * @return number of rows
287 */
288int lcd_get_screen_rows(void);
289
290/**
291 * Get the number of text columns on the LCD
292 *
293 * @return number of columns
294 */
295int lcd_get_screen_columns(void);
296
297/**
298 * Set the position of the text cursor
299 *
300 * @param col Column to place cursor (0 = left side)
301 * @param row Row to place cursor (0 = top line)
302 */
303void lcd_position_cursor(unsigned col, unsigned row);
304
Haavard Skinnemoen6b59e032008-09-01 16:21:22 +0200305/* Allow boards to customize the information displayed */
306void lcd_show_board_info(void);
wdenk8655b6f2004-10-09 23:25:58 +0000307
Simon Glass676d3192012-10-17 13:24:54 +0000308/* Return the size of the LCD frame buffer, and the line length */
309int lcd_get_size(int *line_length);
310
Stephen Warren6a195d22013-05-27 18:31:17 +0000311int lcd_dt_simplefb_add_node(void *blob);
312int lcd_dt_simplefb_enable_existing_node(void *blob);
313
wdenk8655b6f2004-10-09 23:25:58 +0000314/************************************************************************/
315/* ** BITMAP DISPLAY SUPPORT */
316/************************************************************************/
Jon Loeliger639221c2007-07-09 17:15:49 -0500317#if defined(CONFIG_CMD_BMP) || defined(CONFIG_SPLASH_SCREEN)
wdenk8655b6f2004-10-09 23:25:58 +0000318# include <bmp_layout.h>
319# include <asm/byteorder.h>
Jon Loeliger639221c2007-07-09 17:15:49 -0500320#endif
wdenk8655b6f2004-10-09 23:25:58 +0000321
wdenk8655b6f2004-10-09 23:25:58 +0000322/*
323 * Information about displays we are using. This is for configuring
324 * the LCD controller and memory allocation. Someone has to know what
325 * is connected, as we can't autodetect anything.
326 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200327#define CONFIG_SYS_HIGH 0 /* Pins are active high */
Jeroen Hofstee6b035142013-01-12 12:07:56 +0000328#define CONFIG_SYS_LOW 1 /* Pins are active low */
wdenk8655b6f2004-10-09 23:25:58 +0000329
330#define LCD_MONOCHROME 0
331#define LCD_COLOR2 1
332#define LCD_COLOR4 2
333#define LCD_COLOR8 3
334#define LCD_COLOR16 4
335
336/*----------------------------------------------------------------------*/
wdenk88804d12005-07-04 00:03:16 +0000337#if defined(CONFIG_LCD_INFO_BELOW_LOGO)
wdenk8655b6f2004-10-09 23:25:58 +0000338# define LCD_INFO_X 0
339# define LCD_INFO_Y (BMP_LOGO_HEIGHT + VIDEO_FONT_HEIGHT)
340#elif defined(CONFIG_LCD_LOGO)
341# define LCD_INFO_X (BMP_LOGO_WIDTH + 4 * VIDEO_FONT_WIDTH)
Jeroen Hofstee6b035142013-01-12 12:07:56 +0000342# define LCD_INFO_Y VIDEO_FONT_HEIGHT
wdenk8655b6f2004-10-09 23:25:58 +0000343#else
Jeroen Hofstee6b035142013-01-12 12:07:56 +0000344# define LCD_INFO_X VIDEO_FONT_WIDTH
345# define LCD_INFO_Y VIDEO_FONT_HEIGHT
wdenk8655b6f2004-10-09 23:25:58 +0000346#endif
347
348/* Default to 8bpp if bit depth not specified */
349#ifndef LCD_BPP
350# define LCD_BPP LCD_COLOR8
351#endif
352#ifndef LCD_DF
353# define LCD_DF 1
354#endif
355
356/* Calculate nr. of bits per pixel and nr. of colors */
357#define NBITS(bit_code) (1 << (bit_code))
358#define NCOLORS(bit_code) (1 << NBITS(bit_code))
359
360/************************************************************************/
361/* ** CONSOLE CONSTANTS */
362/************************************************************************/
363#if LCD_BPP == LCD_MONOCHROME
364
365/*
366 * Simple black/white definitions
367 */
368# define CONSOLE_COLOR_BLACK 0
369# define CONSOLE_COLOR_WHITE 1 /* Must remain last / highest */
370
371#elif LCD_BPP == LCD_COLOR8
372
373/*
374 * 8bpp color definitions
375 */
376# define CONSOLE_COLOR_BLACK 0
377# define CONSOLE_COLOR_RED 1
378# define CONSOLE_COLOR_GREEN 2
379# define CONSOLE_COLOR_YELLOW 3
380# define CONSOLE_COLOR_BLUE 4
381# define CONSOLE_COLOR_MAGENTA 5
382# define CONSOLE_COLOR_CYAN 6
383# define CONSOLE_COLOR_GREY 14
384# define CONSOLE_COLOR_WHITE 15 /* Must remain last / highest */
385
386#else
387
388/*
389 * 16bpp color definitions
390 */
391# define CONSOLE_COLOR_BLACK 0x0000
392# define CONSOLE_COLOR_WHITE 0xffff /* Must remain last / highest */
393
394#endif /* color definitions */
395
wdenk8655b6f2004-10-09 23:25:58 +0000396/************************************************************************/
397#ifndef PAGE_SIZE
398# define PAGE_SIZE 4096
399#endif
400
401/************************************************************************/
wdenk8655b6f2004-10-09 23:25:58 +0000402
403#endif /* _LCD_H_ */