blob: 4a0f5b252454658623c6c1219323ccf965f69d23 [file] [log] [blame]
Shengzhou Liu48c6f322014-11-24 17:11:56 +08001/*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7/*
8 * T1024/T1023 RDB board configuration file
9 */
10
11#ifndef __T1024RDB_H
12#define __T1024RDB_H
13
14/* High Level Configuration Options */
Shengzhou Liu48c6f322014-11-24 17:11:56 +080015#define CONFIG_DISPLAY_BOARDINFO
16#define CONFIG_BOOKE
17#define CONFIG_E500 /* BOOKE e500 family */
18#define CONFIG_E500MC /* BOOKE e500mc family */
19#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
20#define CONFIG_MP /* support multiple processors */
21#define CONFIG_PHYS_64BIT
22#define CONFIG_ENABLE_36BIT_PHYS
23
24#ifdef CONFIG_PHYS_64BIT
25#define CONFIG_ADDR_MAP 1
26#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
27#endif
28
29#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
30#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
31#define CONFIG_FSL_IFC /* Enable IFC Support */
32
33#define CONFIG_FSL_LAW /* Use common FSL init code */
34#define CONFIG_ENV_OVERWRITE
35
36/* support deep sleep */
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +080037#ifdef CONFIG_PPC_T1024
Shengzhou Liu48c6f322014-11-24 17:11:56 +080038#define CONFIG_DEEP_SLEEP
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +080039#endif
tang yuantianf49b8c12014-12-17 15:42:54 +080040#if defined(CONFIG_DEEP_SLEEP)
Shengzhou Liu48c6f322014-11-24 17:11:56 +080041#define CONFIG_SILENT_CONSOLE
tang yuantianf49b8c12014-12-17 15:42:54 +080042#define CONFIG_BOARD_EARLY_INIT_F
43#endif
Shengzhou Liu48c6f322014-11-24 17:11:56 +080044
45#ifdef CONFIG_RAMBOOT_PBL
46#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +080047#if defined(CONFIG_T1024RDB)
Shengzhou Liu48c6f322014-11-24 17:11:56 +080048#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_rcw.cfg
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +080049#elif defined(CONFIG_T1023RDB)
50#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_rcw.cfg
51#endif
Shengzhou Liu48c6f322014-11-24 17:11:56 +080052#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
53#define CONFIG_SPL_ENV_SUPPORT
54#define CONFIG_SPL_SERIAL_SUPPORT
55#define CONFIG_SPL_FLUSH_IMAGE
56#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
57#define CONFIG_SPL_LIBGENERIC_SUPPORT
58#define CONFIG_SPL_LIBCOMMON_SUPPORT
59#define CONFIG_SPL_I2C_SUPPORT
60#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
61#define CONFIG_FSL_LAW /* Use common FSL init code */
tang yuantianf49b8c12014-12-17 15:42:54 +080062#define CONFIG_SYS_TEXT_BASE 0x30001000
Shengzhou Liu48c6f322014-11-24 17:11:56 +080063#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
64#define CONFIG_SPL_PAD_TO 0x40000
65#define CONFIG_SPL_MAX_SIZE 0x28000
66#define RESET_VECTOR_OFFSET 0x27FFC
67#define BOOT_PAGE_OFFSET 0x27000
68#ifdef CONFIG_SPL_BUILD
69#define CONFIG_SPL_SKIP_RELOCATE
70#define CONFIG_SPL_COMMON_INIT_DDR
71#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
72#define CONFIG_SYS_NO_FLASH
73#endif
74
75#ifdef CONFIG_NAND
76#define CONFIG_SPL_NAND_SUPPORT
77#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
tang yuantianf49b8c12014-12-17 15:42:54 +080078#define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
79#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
Shengzhou Liu48c6f322014-11-24 17:11:56 +080080#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
81#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
82#define CONFIG_SPL_NAND_BOOT
83#endif
84
85#ifdef CONFIG_SPIFLASH
tang yuantianf49b8c12014-12-17 15:42:54 +080086#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
Shengzhou Liu48c6f322014-11-24 17:11:56 +080087#define CONFIG_SPL_SPI_SUPPORT
88#define CONFIG_SPL_SPI_FLASH_SUPPORT
89#define CONFIG_SPL_SPI_FLASH_MINIMAL
90#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
tang yuantianf49b8c12014-12-17 15:42:54 +080091#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
92#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
Shengzhou Liu48c6f322014-11-24 17:11:56 +080093#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
94#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
95#ifndef CONFIG_SPL_BUILD
96#define CONFIG_SYS_MPC85XX_NO_RESETVEC
97#endif
98#define CONFIG_SPL_SPI_BOOT
99#endif
100
101#ifdef CONFIG_SDCARD
tang yuantianf49b8c12014-12-17 15:42:54 +0800102#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800103#define CONFIG_SPL_MMC_SUPPORT
104#define CONFIG_SPL_MMC_MINIMAL
105#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
tang yuantianf49b8c12014-12-17 15:42:54 +0800106#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
107#define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800108#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
109#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
110#ifndef CONFIG_SPL_BUILD
111#define CONFIG_SYS_MPC85XX_NO_RESETVEC
112#endif
113#define CONFIG_SPL_MMC_BOOT
114#endif
115
116#endif /* CONFIG_RAMBOOT_PBL */
117
118#ifndef CONFIG_SYS_TEXT_BASE
119#define CONFIG_SYS_TEXT_BASE 0xeff40000
120#endif
121
122#ifndef CONFIG_RESET_VECTOR_ADDRESS
123#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
124#endif
125
126#ifndef CONFIG_SYS_NO_FLASH
127#define CONFIG_FLASH_CFI_DRIVER
128#define CONFIG_SYS_FLASH_CFI
129#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
130#endif
131
132/* PCIe Boot - Master */
133#define CONFIG_SRIO_PCIE_BOOT_MASTER
134/*
135 * for slave u-boot IMAGE instored in master memory space,
136 * PHYS must be aligned based on the SIZE
137 */
138#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
139#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
140#ifdef CONFIG_PHYS_64BIT
141#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
142#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
143#else
144#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
145#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
146#endif
147/*
148 * for slave UCODE and ENV instored in master memory space,
149 * PHYS must be aligned based on the SIZE
150 */
151#ifdef CONFIG_PHYS_64BIT
152#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
153#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
154#else
155#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
156#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000
157#endif
158#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
159/* slave core release by master*/
160#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
161#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
162
163/* PCIe Boot - Slave */
164#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
165#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
166#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
167 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
168/* Set 1M boot space for PCIe boot */
169#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
170#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
171 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
172#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
173#define CONFIG_SYS_NO_FLASH
174#endif
175
176#if defined(CONFIG_SPIFLASH)
177#define CONFIG_SYS_EXTRA_ENV_RELOC
178#define CONFIG_ENV_IS_IN_SPI_FLASH
179#define CONFIG_ENV_SPI_BUS 0
180#define CONFIG_ENV_SPI_CS 0
181#define CONFIG_ENV_SPI_MAX_HZ 10000000
182#define CONFIG_ENV_SPI_MODE 0
183#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
184#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800185#if defined(CONFIG_T1024RDB)
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800186#define CONFIG_ENV_SECT_SIZE 0x10000
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800187#elif defined(CONFIG_T1023RDB)
188#define CONFIG_ENV_SECT_SIZE 0x40000
189#endif
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800190#elif defined(CONFIG_SDCARD)
191#define CONFIG_SYS_EXTRA_ENV_RELOC
192#define CONFIG_ENV_IS_IN_MMC
193#define CONFIG_SYS_MMC_ENV_DEV 0
194#define CONFIG_ENV_SIZE 0x2000
195#define CONFIG_ENV_OFFSET (512 * 0x800)
196#elif defined(CONFIG_NAND)
197#define CONFIG_SYS_EXTRA_ENV_RELOC
198#define CONFIG_ENV_IS_IN_NAND
199#define CONFIG_ENV_SIZE 0x2000
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800200#if defined(CONFIG_T1024RDB)
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800201#define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800202#elif defined(CONFIG_T1023RDB)
203#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
204#endif
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800205#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
206#define CONFIG_ENV_IS_IN_REMOTE
207#define CONFIG_ENV_ADDR 0xffe20000
208#define CONFIG_ENV_SIZE 0x2000
209#elif defined(CONFIG_ENV_IS_NOWHERE)
210#define CONFIG_ENV_SIZE 0x2000
211#else
212#define CONFIG_ENV_IS_IN_FLASH
213#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
214#define CONFIG_ENV_SIZE 0x2000
215#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
216#endif
217
218
219#ifndef __ASSEMBLY__
220unsigned long get_board_sys_clk(void);
221unsigned long get_board_ddr_clk(void);
222#endif
223
224#define CONFIG_SYS_CLK_FREQ 100000000
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800225#define CONFIG_DDR_CLK_FREQ 100000000
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800226
227/*
228 * These can be toggled for performance analysis, otherwise use default.
229 */
230#define CONFIG_SYS_CACHE_STASHING
231#define CONFIG_BACKSIDE_L2_CACHE
232#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
233#define CONFIG_BTB /* toggle branch predition */
234#define CONFIG_DDR_ECC
235#ifdef CONFIG_DDR_ECC
236#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
237#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
238#endif
239
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800240#define CONFIG_CMD_MEMTEST
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800241#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
242#define CONFIG_SYS_MEMTEST_END 0x00400000
243#define CONFIG_SYS_ALT_MEMTEST
244#define CONFIG_PANIC_HANG /* do not reset board on panic */
245
246/*
247 * Config the L3 Cache as L3 SRAM
248 */
249#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
250#define CONFIG_SYS_L3_SIZE (256 << 10)
251#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
252#ifdef CONFIG_RAMBOOT_PBL
253#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
254#endif
255#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
256#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
257#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
258#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
259
260#ifdef CONFIG_PHYS_64BIT
261#define CONFIG_SYS_DCSRBAR 0xf0000000
262#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
263#endif
264
265/* EEPROM */
266#define CONFIG_ID_EEPROM
267#define CONFIG_SYS_I2C_EEPROM_NXID
268#define CONFIG_SYS_EEPROM_BUS_NUM 0
269#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
270#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
271#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
272#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
273
274/*
275 * DDR Setup
276 */
277#define CONFIG_VERY_BIG_RAM
278#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
279#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
280#define CONFIG_DIMM_SLOTS_PER_CTLR 1
281#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800282#define CONFIG_FSL_DDR_INTERACTIVE
283#if defined(CONFIG_T1024RDB)
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800284#define CONFIG_DDR_SPD
285#define CONFIG_SYS_FSL_DDR3
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800286#define CONFIG_SYS_SPD_BUS_NUM 0
287#define SPD_EEPROM_ADDRESS 0x51
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800288#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800289#elif defined(CONFIG_T1023RDB)
290#define CONFIG_SYS_FSL_DDR4
291#define CONFIG_SYS_DDR_RAW_TIMING
292#define CONFIG_SYS_SDRAM_SIZE 2048
293#endif
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800294
295/*
296 * IFC Definitions
297 */
298#define CONFIG_SYS_FLASH_BASE 0xe8000000
299#ifdef CONFIG_PHYS_64BIT
300#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
301#else
302#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
303#endif
304
305#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
306#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
307 CSPR_PORT_SIZE_16 | \
308 CSPR_MSEL_NOR | \
309 CSPR_V)
310#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
311
312/* NOR Flash Timing Params */
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800313#if defined(CONFIG_T1024RDB)
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800314#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800315#elif defined(CONFIG_T1023RDB)
Shengzhou Liuff7ea2d2015-06-17 16:37:01 +0800316#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800317 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
318#endif
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800319#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
320 FTIM0_NOR_TEADC(0x5) | \
321 FTIM0_NOR_TEAHC(0x5))
322#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
323 FTIM1_NOR_TRAD_NOR(0x1A) |\
324 FTIM1_NOR_TSEQRAD_NOR(0x13))
325#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
326 FTIM2_NOR_TCH(0x4) | \
327 FTIM2_NOR_TWPH(0x0E) | \
328 FTIM2_NOR_TWP(0x1c))
329#define CONFIG_SYS_NOR_FTIM3 0x0
330
331#define CONFIG_SYS_FLASH_QUIET_TEST
332#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
333
334#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
335#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
336#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
337#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
338
339#define CONFIG_SYS_FLASH_EMPTY_INFO
340#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
341
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800342#ifdef CONFIG_T1024RDB
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800343/* CPLD on IFC */
344#define CONFIG_SYS_CPLD_BASE 0xffdf0000
345#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
346#define CONFIG_SYS_CSPR2_EXT (0xf)
347#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
348 | CSPR_PORT_SIZE_8 \
349 | CSPR_MSEL_GPCM \
350 | CSPR_V)
351#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
352#define CONFIG_SYS_CSOR2 0x0
353
354/* CPLD Timing parameters for IFC CS2 */
355#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
356 FTIM0_GPCM_TEADC(0x0e) | \
357 FTIM0_GPCM_TEAHC(0x0e))
358#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
359 FTIM1_GPCM_TRAD(0x1f))
360#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
361 FTIM2_GPCM_TCH(0x8) | \
362 FTIM2_GPCM_TWP(0x1f))
363#define CONFIG_SYS_CS2_FTIM3 0x0
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800364#endif
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800365
366/* NAND Flash on IFC */
367#define CONFIG_NAND_FSL_IFC
368#define CONFIG_SYS_NAND_BASE 0xff800000
369#ifdef CONFIG_PHYS_64BIT
370#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
371#else
372#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
373#endif
374#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
375#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
376 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
377 | CSPR_MSEL_NAND /* MSEL = NAND */ \
378 | CSPR_V)
379#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
380
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800381#if defined(CONFIG_T1024RDB)
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800382#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
383 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
384 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
385 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
386 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
387 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
388 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800389#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
390#elif defined(CONFIG_T1023RDB)
Jaiprakash Singh78429502015-05-22 15:21:07 +0530391#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
392 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
393 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800394 | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \
395 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
396 | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \
397 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
398#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
399#endif
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800400
401#define CONFIG_SYS_NAND_ONFI_DETECTION
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800402/* ONFI NAND Flash mode0 Timing Params */
403#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
404 FTIM0_NAND_TWP(0x18) | \
405 FTIM0_NAND_TWCHT(0x07) | \
406 FTIM0_NAND_TWH(0x0a))
407#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
408 FTIM1_NAND_TWBE(0x39) | \
409 FTIM1_NAND_TRR(0x0e) | \
410 FTIM1_NAND_TRP(0x18))
411#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
412 FTIM2_NAND_TREH(0x0a) | \
413 FTIM2_NAND_TWHRE(0x1e))
414#define CONFIG_SYS_NAND_FTIM3 0x0
415
416#define CONFIG_SYS_NAND_DDR_LAW 11
417#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
418#define CONFIG_SYS_MAX_NAND_DEVICE 1
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800419#define CONFIG_CMD_NAND
420
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800421#if defined(CONFIG_NAND)
422#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
423#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
424#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
425#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
426#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
427#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
428#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
429#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
430#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
431#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
432#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
433#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
434#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
435#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
436#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
437#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
438#else
439#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
440#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
441#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
442#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
443#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
444#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
445#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
446#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
447#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
448#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
449#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
450#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
451#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
452#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
453#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
454#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
455#endif
456
457#ifdef CONFIG_SPL_BUILD
458#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
459#else
460#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
461#endif
462
463#if defined(CONFIG_RAMBOOT_PBL)
464#define CONFIG_SYS_RAMBOOT
465#endif
466
467#define CONFIG_BOARD_EARLY_INIT_R
468#define CONFIG_MISC_INIT_R
469
470#define CONFIG_HWCONFIG
471
472/* define to use L1 as initial stack */
473#define CONFIG_L1_INIT_RAM
474#define CONFIG_SYS_INIT_RAM_LOCK
475#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
476#ifdef CONFIG_PHYS_64BIT
477#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
York Sunb3142e22015-08-17 13:31:51 -0700478#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800479/* The assembler doesn't like typecast */
480#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
481 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
482 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
483#else
York Sunb3142e22015-08-17 13:31:51 -0700484#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800485#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
486#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
487#endif
488#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
489
490#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
491 GENERATED_GBL_DATA_SIZE)
492#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
493
494#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
495#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
496
497/* Serial Port */
498#define CONFIG_CONS_INDEX 1
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800499#define CONFIG_SYS_NS16550_SERIAL
500#define CONFIG_SYS_NS16550_REG_SIZE 1
501#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
502
503#define CONFIG_SYS_BAUDRATE_TABLE \
504 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
505
506#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
507#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
508#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
509#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
510#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
511
512/* Use the HUSH parser */
513#define CONFIG_SYS_HUSH_PARSER
514#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
515
516/* Video */
517#undef CONFIG_FSL_DIU_FB /* RDB doesn't support DIU */
518#ifdef CONFIG_FSL_DIU_FB
519#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
520#define CONFIG_VIDEO
521#define CONFIG_CMD_BMP
522#define CONFIG_CFB_CONSOLE
523#define CONFIG_VIDEO_SW_CURSOR
524#define CONFIG_VGA_AS_SINGLE_DEVICE
525#define CONFIG_VIDEO_LOGO
526#define CONFIG_VIDEO_BMP_LOGO
527#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
528/*
529 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
530 * disable empty flash sector detection, which is I/O-intensive.
531 */
532#undef CONFIG_SYS_FLASH_EMPTY_INFO
533#endif
534
535/* pass open firmware flat tree */
536#define CONFIG_OF_LIBFDT
537#define CONFIG_OF_BOARD_SETUP
538#define CONFIG_OF_STDOUT_VIA_ALIAS
539
540/* new uImage format support */
541#define CONFIG_FIT
542#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
543
544/* I2C */
545#define CONFIG_SYS_I2C
546#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
547#define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
548#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
549#define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */
550#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
551#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
552#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
553
Shengzhou Liuff7ea2d2015-06-17 16:37:01 +0800554#define I2C_PCA6408_BUS_NUM 1
555#define I2C_PCA6408_ADDR 0x20
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800556
557/* I2C bus multiplexer */
558#define I2C_MUX_CH_DEFAULT 0x8
559
560/*
561 * RTC configuration
562 */
563#define RTC
564#define CONFIG_RTC_DS1337 1
565#define CONFIG_SYS_I2C_RTC_ADDR 0x68
566
567/*
568 * eSPI - Enhanced SPI
569 */
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800570#if defined(CONFIG_T1024RDB)
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800571#elif defined(CONFIG_T1023RDB)
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800572#endif
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800573#define CONFIG_CMD_SF
574#define CONFIG_SPI_FLASH_BAR
575#define CONFIG_SF_DEFAULT_SPEED 10000000
576#define CONFIG_SF_DEFAULT_MODE 0
577
578/*
579 * General PCIe
580 * Memory space is mapped 1-1, but I/O space must start from 0.
581 */
582#define CONFIG_PCI /* Enable PCI/PCIE */
583#define CONFIG_PCIE1 /* PCIE controler 1 */
584#define CONFIG_PCIE2 /* PCIE controler 2 */
585#define CONFIG_PCIE3 /* PCIE controler 3 */
586#ifdef CONFIG_PPC_T1040
587#define CONFIG_PCIE4 /* PCIE controler 4 */
588#endif
589#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
590#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
591#define CONFIG_PCI_INDIRECT_BRIDGE
592
593#ifdef CONFIG_PCI
594/* controller 1, direct to uli, tgtid 3, Base address 20000 */
595#ifdef CONFIG_PCIE1
596#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
597#ifdef CONFIG_PHYS_64BIT
598#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
599#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
600#else
601#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
602#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
603#endif
604#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
605#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
606#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
607#ifdef CONFIG_PHYS_64BIT
608#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
609#else
610#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
611#endif
612#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
613#endif
614
615/* controller 2, Slot 2, tgtid 2, Base address 201000 */
616#ifdef CONFIG_PCIE2
617#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
618#ifdef CONFIG_PHYS_64BIT
619#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
620#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
621#else
622#define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000
623#define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000
624#endif
625#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
626#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
627#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
628#ifdef CONFIG_PHYS_64BIT
629#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
630#else
631#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
632#endif
633#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
634#endif
635
636/* controller 3, Slot 1, tgtid 1, Base address 202000 */
637#ifdef CONFIG_PCIE3
638#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
639#ifdef CONFIG_PHYS_64BIT
640#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
641#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
642#else
643#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
644#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
645#endif
646#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
647#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
648#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
649#ifdef CONFIG_PHYS_64BIT
650#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
651#else
652#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
653#endif
654#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
655#endif
656
657/* controller 4, Base address 203000, to be removed */
658#ifdef CONFIG_PCIE4
659#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
660#ifdef CONFIG_PHYS_64BIT
661#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
662#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
663#else
664#define CONFIG_SYS_PCIE4_MEM_BUS 0xb0000000
665#define CONFIG_SYS_PCIE4_MEM_PHYS 0xb0000000
666#endif
667#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
668#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
669#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
670#ifdef CONFIG_PHYS_64BIT
671#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
672#else
673#define CONFIG_SYS_PCIE4_IO_PHYS 0xf8030000
674#endif
675#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
676#endif
677
678#define CONFIG_PCI_PNP /* do pci plug-and-play */
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800679#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
680#define CONFIG_DOS_PARTITION
681#endif /* CONFIG_PCI */
682
683/*
684 * USB
685 */
686#define CONFIG_HAS_FSL_DR_USB
687
688#ifdef CONFIG_HAS_FSL_DR_USB
689#define CONFIG_USB_EHCI
690#define CONFIG_CMD_USB
691#define CONFIG_USB_STORAGE
692#define CONFIG_USB_EHCI_FSL
693#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
694#define CONFIG_CMD_EXT2
695#endif
696
697/*
698 * SDHC
699 */
700#define CONFIG_MMC
701#ifdef CONFIG_MMC
702#define CONFIG_FSL_ESDHC
703#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
704#define CONFIG_CMD_MMC
705#define CONFIG_GENERIC_MMC
706#define CONFIG_CMD_EXT2
707#define CONFIG_CMD_FAT
708#define CONFIG_DOS_PARTITION
709#endif
710
711/* Qman/Bman */
712#ifndef CONFIG_NOBQFMAN
713#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
Jeffrey Ladouceur2a8b3422014-12-03 18:08:43 -0500714#define CONFIG_SYS_BMAN_NUM_PORTALS 10
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800715#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
716#ifdef CONFIG_PHYS_64BIT
717#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
718#else
719#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
720#endif
721#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500722#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
723#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
724#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
725#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
726#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
727 CONFIG_SYS_BMAN_CENA_SIZE)
728#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
729#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
Jeffrey Ladouceur2a8b3422014-12-03 18:08:43 -0500730#define CONFIG_SYS_QMAN_NUM_PORTALS 10
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800731#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
732#ifdef CONFIG_PHYS_64BIT
733#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
734#else
735#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
736#endif
737#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500738#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
739#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
740#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
741#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
742#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
743 CONFIG_SYS_QMAN_CENA_SIZE)
744#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
745#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800746
747#define CONFIG_SYS_DPAA_FMAN
748
Shengzhou Liuff7ea2d2015-06-17 16:37:01 +0800749#ifdef CONFIG_T1024RDB
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800750#define CONFIG_QE
751#define CONFIG_U_QE
Shengzhou Liuff7ea2d2015-06-17 16:37:01 +0800752#endif
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800753/* Default address of microcode for the Linux FMan driver */
754#if defined(CONFIG_SPIFLASH)
755/*
756 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
757 * env, so we got 0x110000.
758 */
759#define CONFIG_SYS_QE_FW_IN_SPIFLASH
760#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
761#define CONFIG_SYS_QE_FW_ADDR 0x130000
762#elif defined(CONFIG_SDCARD)
763/*
764 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
765 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
766 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
767 */
768#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
769#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
770#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
771#elif defined(CONFIG_NAND)
772#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800773#if defined(CONFIG_T1024RDB)
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800774#define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
775#define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800776#elif defined(CONFIG_T1023RDB)
777#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
778#define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
779#endif
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800780#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
781/*
782 * Slave has no ucode locally, it can fetch this from remote. When implementing
783 * in two corenet boards, slave's ucode could be stored in master's memory
784 * space, the address can be mapped from slave TLB->slave LAW->
785 * slave SRIO or PCIE outbound window->master inbound window->
786 * master LAW->the ucode address in master's memory space.
787 */
788#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
789#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
790#else
791#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
792#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
793#define CONFIG_SYS_QE_FW_ADDR 0xEFE00000
794#endif
795#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
796#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
797#endif /* CONFIG_NOBQFMAN */
798
799#ifdef CONFIG_SYS_DPAA_FMAN
800#define CONFIG_FMAN_ENET
801#define CONFIG_PHYLIB_10G
802#define CONFIG_PHY_REALTEK
Shengzhou Liue26416a2014-12-17 16:51:08 +0800803#define CONFIG_PHY_AQUANTIA
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800804#if defined(CONFIG_T1024RDB)
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800805#define RGMII_PHY1_ADDR 0x2
806#define RGMII_PHY2_ADDR 0x6
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800807#define SGMII_AQR_PHY_ADDR 0x2
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800808#define FM1_10GEC1_PHY_ADDR 0x1
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800809#elif defined(CONFIG_T1023RDB)
810#define RGMII_PHY1_ADDR 0x1
811#define SGMII_RTK_PHY_ADDR 0x3
812#define SGMII_AQR_PHY_ADDR 0x2
813#endif
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800814#endif
815
816#ifdef CONFIG_FMAN_ENET
817#define CONFIG_MII /* MII PHY management */
818#define CONFIG_ETHPRIME "FM1@DTSEC4"
819#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
820#endif
821
822/*
823 * Dynamic MTD Partition support with mtdparts
824 */
825#ifndef CONFIG_SYS_NO_FLASH
826#define CONFIG_MTD_DEVICE
827#define CONFIG_MTD_PARTITIONS
828#define CONFIG_CMD_MTDPARTS
829#define CONFIG_FLASH_CFI_MTD
830#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
831 "spi0=spife110000.1"
832#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
833 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \
834 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \
835 "1m(uboot),5m(kernel),128k(dtb),-(user)"
836#endif
837
838/*
839 * Environment
840 */
841#define CONFIG_LOADS_ECHO /* echo on for serial download */
842#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
843
844/*
845 * Command line configuration.
846 */
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800847#define CONFIG_CMD_DATE
848#define CONFIG_CMD_DHCP
849#define CONFIG_CMD_EEPROM
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800850#define CONFIG_CMD_ERRATA
851#define CONFIG_CMD_GREPENV
852#define CONFIG_CMD_IRQ
853#define CONFIG_CMD_I2C
854#define CONFIG_CMD_MII
855#define CONFIG_CMD_PING
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800856#define CONFIG_CMD_REGINFO
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800857
858#ifdef CONFIG_PCI
859#define CONFIG_CMD_PCI
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800860#endif
861
862/*
863 * Miscellaneous configurable options
864 */
865#define CONFIG_SYS_LONGHELP /* undef to save memory */
866#define CONFIG_CMDLINE_EDITING /* Command-line editing */
867#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
868#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800869#ifdef CONFIG_CMD_KGDB
870#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
871#else
872#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
873#endif
874#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
875#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
876#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
877
878/*
879 * For booting Linux, the board info and command line data
880 * have to be in the first 64 MB of memory, since this is
881 * the maximum mapped by the Linux kernel during initialization.
882 */
883#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
884#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
885
886#ifdef CONFIG_CMD_KGDB
887#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
888#endif
889
890/*
891 * Environment Configuration
892 */
893#define CONFIG_ROOTPATH "/opt/nfsroot"
894#define CONFIG_BOOTFILE "uImage"
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800895#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800896#define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */
897#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
898#define CONFIG_BAUDRATE 115200
899#define __USB_PHY_TYPE utmi
900
901#ifdef CONFIG_PPC_T1024
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800902#define CONFIG_BOARDNAME t1024rdb
903#define BANK_INTLV cs0_cs1
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800904#else
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800905#define CONFIG_BOARDNAME t1023rdb
906#define BANK_INTLV null
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800907#endif
908
909#define CONFIG_EXTRA_ENV_SETTINGS \
910 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
Shengzhou Liue8a7f1c2015-03-27 15:48:34 +0800911 "bank_intlv=" __stringify(BANK_INTLV) "\0" \
Shengzhou Liu48c6f322014-11-24 17:11:56 +0800912 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
913 "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \
914 "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \
915 __stringify(CONFIG_BOARDNAME) ".dtb\0" \
916 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
917 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
918 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
919 "netdev=eth0\0" \
920 "tftpflash=tftpboot $loadaddr $uboot && " \
921 "protect off $ubootaddr +$filesize && " \
922 "erase $ubootaddr +$filesize && " \
923 "cp.b $loadaddr $ubootaddr $filesize && " \
924 "protect on $ubootaddr +$filesize && " \
925 "cmp.b $loadaddr $ubootaddr $filesize\0" \
926 "consoledev=ttyS0\0" \
927 "ramdiskaddr=2000000\0" \
928 "fdtaddr=c00000\0" \
929 "bdev=sda3\0"
930
931#define CONFIG_LINUX \
932 "setenv bootargs root=/dev/ram rw " \
933 "console=$consoledev,$baudrate $othbootargs;" \
934 "setenv ramdiskaddr 0x02000000;" \
935 "setenv fdtaddr 0x00c00000;" \
936 "setenv loadaddr 0x1000000;" \
937 "bootm $loadaddr $ramdiskaddr $fdtaddr"
938
939
940#define CONFIG_NFSBOOTCOMMAND \
941 "setenv bootargs root=/dev/nfs rw " \
942 "nfsroot=$serverip:$rootpath " \
943 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
944 "console=$consoledev,$baudrate $othbootargs;" \
945 "tftp $loadaddr $bootfile;" \
946 "tftp $fdtaddr $fdtfile;" \
947 "bootm $loadaddr - $fdtaddr"
948
949#define CONFIG_BOOTCOMMAND CONFIG_LINUX
950
951#ifdef CONFIG_SECURE_BOOT
952#include <asm/fsl_secure_boot.h>
953#endif
954
955#endif /* __T1024RDB_H */