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Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +09001/*
Yoshihiro Shimoda26235092012-06-26 16:38:06 +00002 * sh_eth.c - Driver for Renesas ethernet controler.
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +09003 *
Nobuhiro Iwamatsu3bb4cc32011-11-14 16:56:59 +09004 * Copyright (C) 2008, 2011 Renesas Solutions Corp.
Nobuhiro Iwamatsuf7ca1f72014-11-04 09:15:48 +09005 * Copyright (c) 2008, 2011, 2014 2014 Nobuhiro Iwamatsu
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +09006 * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
Nobuhiro Iwamatsuf7ca1f72014-11-04 09:15:48 +09007 * Copyright (C) 2013, 2014 Renesas Electronics Corporation
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +09008 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02009 * SPDX-License-Identifier: GPL-2.0+
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +090010 */
11
12#include <config.h>
13#include <common.h>
14#include <malloc.h>
15#include <net.h>
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +090016#include <netdev.h>
Yoshihiro Shimodabd1024b2011-10-11 18:10:14 +090017#include <miiphy.h>
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +090018#include <asm/errno.h>
19#include <asm/io.h>
20
21#include "sh_eth.h"
22
23#ifndef CONFIG_SH_ETHER_USE_PORT
24# error "Please define CONFIG_SH_ETHER_USE_PORT"
25#endif
26#ifndef CONFIG_SH_ETHER_PHY_ADDR
27# error "Please define CONFIG_SH_ETHER_PHY_ADDR"
28#endif
Nobuhiro Iwamatsu870cc232013-08-22 13:22:01 +090029
Nobuhiro Iwamatsu92f07132013-08-22 13:22:03 +090030#if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && !defined(CONFIG_SYS_DCACHE_OFF)
31#define flush_cache_wback(addr, len) \
32 flush_dcache_range((u32)addr, (u32)(addr + len - 1))
Yoshihiro Shimoda68260aa2011-01-27 10:06:08 +090033#else
34#define flush_cache_wback(...)
35#endif
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +090036
Nobuhiro Iwamatsu92f07132013-08-22 13:22:03 +090037#if defined(CONFIG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM)
38#define invalidate_cache(addr, len) \
39 { \
40 u32 line_size = CONFIG_SH_ETHER_ALIGNE_SIZE; \
41 u32 start, end; \
42 \
43 start = (u32)addr; \
44 end = start + len; \
45 start &= ~(line_size - 1); \
46 end = ((end + line_size - 1) & ~(line_size - 1)); \
47 \
48 invalidate_dcache_range(start, end); \
49 }
50#else
51#define invalidate_cache(...)
52#endif
53
Nobuhiro Iwamatsu4ba62c72012-01-11 10:23:51 +090054#define TIMEOUT_CNT 1000
55
Joe Hershberger10cbe3b2012-05-22 18:36:19 +000056int sh_eth_send(struct eth_device *dev, void *packet, int len)
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +090057{
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +090058 struct sh_eth_dev *eth = dev->priv;
59 int port = eth->port, ret = 0, timeout;
60 struct sh_eth_info *port_info = &eth->port_info[port];
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +090061
62 if (!packet || len > 0xffff) {
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +090063 printf(SHETHER_NAME ": %s: Invalid argument\n", __func__);
64 ret = -EINVAL;
65 goto err;
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +090066 }
67
68 /* packet must be a 4 byte boundary */
Nobuhiro Iwamatsuee6ec5d2012-02-02 21:28:49 +000069 if ((int)packet & 3) {
Nobuhiro Iwamatsue2752db2014-01-23 07:52:19 +090070 printf(SHETHER_NAME ": %s: packet not 4 byte alligned\n"
71 , __func__);
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +090072 ret = -EFAULT;
73 goto err;
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +090074 }
75
76 /* Update tx descriptor */
Yoshihiro Shimoda68260aa2011-01-27 10:06:08 +090077 flush_cache_wback(packet, len);
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +090078 port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet);
79 port_info->tx_desc_cur->td1 = len << 16;
80 /* Must preserve the end of descriptor list indication */
81 if (port_info->tx_desc_cur->td0 & TD_TDLE)
82 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP | TD_TDLE;
83 else
84 port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP;
85
Nobuhiro Iwamatsuf7ca1f72014-11-04 09:15:48 +090086 flush_cache_wback(port_info->tx_desc_cur, sizeof(struct tx_desc_s));
87
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +090088 /* Restart the transmitter if disabled */
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +000089 if (!(sh_eth_read(eth, EDTRR) & EDTRR_TRNS))
90 sh_eth_write(eth, EDTRR_TRNS, EDTRR);
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +090091
92 /* Wait until packet is transmitted */
Nobuhiro Iwamatsu4ba62c72012-01-11 10:23:51 +090093 timeout = TIMEOUT_CNT;
Nobuhiro Iwamatsu92f07132013-08-22 13:22:03 +090094 do {
95 invalidate_cache(port_info->tx_desc_cur,
96 sizeof(struct tx_desc_s));
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +090097 udelay(100);
Nobuhiro Iwamatsu92f07132013-08-22 13:22:03 +090098 } while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--);
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +090099
100 if (timeout < 0) {
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900101 printf(SHETHER_NAME ": transmit timeout\n");
102 ret = -ETIMEDOUT;
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900103 goto err;
104 }
105
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900106 port_info->tx_desc_cur++;
107 if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC)
108 port_info->tx_desc_cur = port_info->tx_desc_base;
109
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900110err:
111 return ret;
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900112}
113
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900114int sh_eth_recv(struct eth_device *dev)
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900115{
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900116 struct sh_eth_dev *eth = dev->priv;
117 int port = eth->port, len = 0;
118 struct sh_eth_info *port_info = &eth->port_info[port];
Joe Hershberger10cbe3b2012-05-22 18:36:19 +0000119 uchar *packet;
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900120
121 /* Check if the rx descriptor is ready */
Nobuhiro Iwamatsu92f07132013-08-22 13:22:03 +0900122 invalidate_cache(port_info->rx_desc_cur, sizeof(struct rx_desc_s));
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900123 if (!(port_info->rx_desc_cur->rd0 & RD_RACT)) {
124 /* Check for errors */
125 if (!(port_info->rx_desc_cur->rd0 & RD_RFE)) {
126 len = port_info->rx_desc_cur->rd1 & 0xffff;
Joe Hershberger10cbe3b2012-05-22 18:36:19 +0000127 packet = (uchar *)
128 ADDR_TO_P2(port_info->rx_desc_cur->rd2);
Nobuhiro Iwamatsu92f07132013-08-22 13:22:03 +0900129 invalidate_cache(packet, len);
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500130 net_process_received_packet(packet, len);
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900131 }
132
133 /* Make current descriptor available again */
134 if (port_info->rx_desc_cur->rd0 & RD_RDLE)
135 port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE;
136 else
137 port_info->rx_desc_cur->rd0 = RD_RACT;
Nobuhiro Iwamatsuf7ca1f72014-11-04 09:15:48 +0900138
139 flush_cache_wback(port_info->rx_desc_cur,
140 sizeof(struct rx_desc_s));
141
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900142 /* Point to the next descriptor */
143 port_info->rx_desc_cur++;
144 if (port_info->rx_desc_cur >=
145 port_info->rx_desc_base + NUM_RX_DESC)
146 port_info->rx_desc_cur = port_info->rx_desc_base;
147 }
148
149 /* Restart the receiver if disabled */
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000150 if (!(sh_eth_read(eth, EDRRR) & EDRRR_R))
151 sh_eth_write(eth, EDRRR_R, EDRRR);
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900152
153 return len;
154}
155
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900156static int sh_eth_reset(struct sh_eth_dev *eth)
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900157{
Nobuhiro Iwamatsu62cbddc2014-01-23 07:52:18 +0900158#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900159 int ret = 0, i;
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900160
161 /* Start e-dmac transmitter and receiver */
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000162 sh_eth_write(eth, EDSR_ENALL, EDSR);
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900163
164 /* Perform a software reset and wait for it to complete */
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000165 sh_eth_write(eth, EDMR_SRST, EDMR);
Nobuhiro Iwamatsue2752db2014-01-23 07:52:19 +0900166 for (i = 0; i < TIMEOUT_CNT; i++) {
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000167 if (!(sh_eth_read(eth, EDMR) & EDMR_SRST))
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900168 break;
169 udelay(1000);
170 }
171
Nobuhiro Iwamatsu4ba62c72012-01-11 10:23:51 +0900172 if (i == TIMEOUT_CNT) {
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900173 printf(SHETHER_NAME ": Software reset timeout\n");
174 ret = -EIO;
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900175 }
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900176
177 return ret;
Yoshihiro Shimoda903de462011-01-18 17:53:45 +0900178#else
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000179 sh_eth_write(eth, sh_eth_read(eth, EDMR) | EDMR_SRST, EDMR);
Yoshihiro Shimoda903de462011-01-18 17:53:45 +0900180 udelay(3000);
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000181 sh_eth_write(eth, sh_eth_read(eth, EDMR) & ~EDMR_SRST, EDMR);
Yoshihiro Shimoda903de462011-01-18 17:53:45 +0900182
183 return 0;
184#endif
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900185}
186
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900187static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900188{
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900189 int port = eth->port, i, ret = 0;
Nobuhiro Iwamatsu000889c2014-11-04 09:15:47 +0900190 u32 alloc_desc_size = NUM_TX_DESC * sizeof(struct tx_desc_s);
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900191 struct sh_eth_info *port_info = &eth->port_info[port];
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900192 struct tx_desc_s *cur_tx_desc;
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900193
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900194 /*
Nobuhiro Iwamatsu703949e2014-11-04 09:15:46 +0900195 * Allocate rx descriptors. They must be aligned to size of struct
196 * tx_desc_s.
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900197 */
Nobuhiro Iwamatsu000889c2014-11-04 09:15:47 +0900198 port_info->tx_desc_alloc =
199 memalign(sizeof(struct tx_desc_s), alloc_desc_size);
200 if (!port_info->tx_desc_alloc) {
201 printf(SHETHER_NAME ": memalign failed\n");
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900202 ret = -ENOMEM;
203 goto err;
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900204 }
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900205
Nobuhiro Iwamatsu000889c2014-11-04 09:15:47 +0900206 flush_cache_wback((u32)port_info->tx_desc_alloc, alloc_desc_size);
207
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900208 /* Make sure we use a P2 address (non-cacheable) */
Nobuhiro Iwamatsu000889c2014-11-04 09:15:47 +0900209 port_info->tx_desc_base =
210 (struct tx_desc_s *)ADDR_TO_P2((u32)port_info->tx_desc_alloc);
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900211 port_info->tx_desc_cur = port_info->tx_desc_base;
212
213 /* Initialize all descriptors */
214 for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC;
215 cur_tx_desc++, i++) {
216 cur_tx_desc->td0 = 0x00;
217 cur_tx_desc->td1 = 0x00;
218 cur_tx_desc->td2 = 0x00;
219 }
220
221 /* Mark the end of the descriptors */
222 cur_tx_desc--;
223 cur_tx_desc->td0 |= TD_TDLE;
224
225 /* Point the controller to the tx descriptor list. Must use physical
226 addresses */
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000227 sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR);
Nobuhiro Iwamatsu62cbddc2014-01-23 07:52:18 +0900228#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000229 sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR);
230 sh_eth_write(eth, ADDR_TO_PHY(cur_tx_desc), TDFXR);
231 sh_eth_write(eth, 0x01, TDFFR);/* Last discriptor bit */
Yoshihiro Shimoda903de462011-01-18 17:53:45 +0900232#endif
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900233
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900234err:
235 return ret;
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900236}
237
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900238static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900239{
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900240 int port = eth->port, i , ret = 0;
Nobuhiro Iwamatsu000889c2014-11-04 09:15:47 +0900241 u32 alloc_desc_size = NUM_RX_DESC * sizeof(struct rx_desc_s);
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900242 struct sh_eth_info *port_info = &eth->port_info[port];
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900243 struct rx_desc_s *cur_rx_desc;
244 u8 *rx_buf;
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900245
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900246 /*
Nobuhiro Iwamatsu703949e2014-11-04 09:15:46 +0900247 * Allocate rx descriptors. They must be aligned to size of struct
248 * rx_desc_s.
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900249 */
Nobuhiro Iwamatsu000889c2014-11-04 09:15:47 +0900250 port_info->rx_desc_alloc =
251 memalign(sizeof(struct rx_desc_s), alloc_desc_size);
252 if (!port_info->rx_desc_alloc) {
253 printf(SHETHER_NAME ": memalign failed\n");
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900254 ret = -ENOMEM;
255 goto err;
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900256 }
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900257
Nobuhiro Iwamatsu000889c2014-11-04 09:15:47 +0900258 flush_cache_wback(port_info->rx_desc_alloc, alloc_desc_size);
259
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900260 /* Make sure we use a P2 address (non-cacheable) */
Nobuhiro Iwamatsu000889c2014-11-04 09:15:47 +0900261 port_info->rx_desc_base =
262 (struct rx_desc_s *)ADDR_TO_P2((u32)port_info->rx_desc_alloc);
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900263
264 port_info->rx_desc_cur = port_info->rx_desc_base;
265
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900266 /*
Nobuhiro Iwamatsu000889c2014-11-04 09:15:47 +0900267 * Allocate rx data buffers. They must be RX_BUF_ALIGNE_SIZE bytes
268 * aligned and in P2 area.
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900269 */
Nobuhiro Iwamatsu000889c2014-11-04 09:15:47 +0900270 port_info->rx_buf_alloc =
271 memalign(RX_BUF_ALIGNE_SIZE, NUM_RX_DESC * MAX_BUF_SIZE);
272 if (!port_info->rx_buf_alloc) {
273 printf(SHETHER_NAME ": alloc failed\n");
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900274 ret = -ENOMEM;
Nobuhiro Iwamatsu000889c2014-11-04 09:15:47 +0900275 goto err_buf_alloc;
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900276 }
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900277
Nobuhiro Iwamatsu000889c2014-11-04 09:15:47 +0900278 port_info->rx_buf_base = (u8 *)ADDR_TO_P2((u32)port_info->rx_buf_alloc);
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900279
280 /* Initialize all descriptors */
281 for (cur_rx_desc = port_info->rx_desc_base,
282 rx_buf = port_info->rx_buf_base, i = 0;
283 i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) {
284 cur_rx_desc->rd0 = RD_RACT;
285 cur_rx_desc->rd1 = MAX_BUF_SIZE << 16;
286 cur_rx_desc->rd2 = (u32) ADDR_TO_PHY(rx_buf);
287 }
288
289 /* Mark the end of the descriptors */
290 cur_rx_desc--;
291 cur_rx_desc->rd0 |= RD_RDLE;
292
293 /* Point the controller to the rx descriptor list */
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000294 sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR);
Nobuhiro Iwamatsu62cbddc2014-01-23 07:52:18 +0900295#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000296 sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR);
297 sh_eth_write(eth, ADDR_TO_PHY(cur_rx_desc), RDFXR);
298 sh_eth_write(eth, RDFFR_RDLF, RDFFR);
Yoshihiro Shimoda903de462011-01-18 17:53:45 +0900299#endif
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900300
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900301 return ret;
302
Nobuhiro Iwamatsu000889c2014-11-04 09:15:47 +0900303err_buf_alloc:
304 free(port_info->rx_desc_alloc);
305 port_info->rx_desc_alloc = NULL;
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900306
307err:
308 return ret;
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900309}
310
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900311static void sh_eth_tx_desc_free(struct sh_eth_dev *eth)
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900312{
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900313 int port = eth->port;
314 struct sh_eth_info *port_info = &eth->port_info[port];
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900315
Nobuhiro Iwamatsu000889c2014-11-04 09:15:47 +0900316 if (port_info->tx_desc_alloc) {
317 free(port_info->tx_desc_alloc);
318 port_info->tx_desc_alloc = NULL;
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900319 }
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900320}
321
322static void sh_eth_rx_desc_free(struct sh_eth_dev *eth)
323{
324 int port = eth->port;
325 struct sh_eth_info *port_info = &eth->port_info[port];
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900326
Nobuhiro Iwamatsu000889c2014-11-04 09:15:47 +0900327 if (port_info->rx_desc_alloc) {
328 free(port_info->rx_desc_alloc);
329 port_info->rx_desc_alloc = NULL;
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900330 }
331
Nobuhiro Iwamatsu000889c2014-11-04 09:15:47 +0900332 if (port_info->rx_buf_alloc) {
333 free(port_info->rx_buf_alloc);
334 port_info->rx_buf_alloc = NULL;
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900335 }
336}
337
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900338static int sh_eth_desc_init(struct sh_eth_dev *eth)
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900339{
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900340 int ret = 0;
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900341
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900342 ret = sh_eth_tx_desc_init(eth);
343 if (ret)
344 goto err_tx_init;
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900345
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900346 ret = sh_eth_rx_desc_init(eth);
347 if (ret)
348 goto err_rx_init;
349
350 return ret;
351err_rx_init:
352 sh_eth_tx_desc_free(eth);
353
354err_tx_init:
355 return ret;
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900356}
357
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900358static int sh_eth_phy_config(struct sh_eth_dev *eth)
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900359{
Yoshihiro Shimodabd1024b2011-10-11 18:10:14 +0900360 int port = eth->port, ret = 0;
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900361 struct sh_eth_info *port_info = &eth->port_info[port];
Yoshihiro Shimodabd1024b2011-10-11 18:10:14 +0900362 struct eth_device *dev = port_info->dev;
363 struct phy_device *phydev;
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900364
Nobuhiro Iwamatsuee6ec5d2012-02-02 21:28:49 +0000365 phydev = phy_connect(
366 miiphy_get_dev_by_name(dev->name),
Nobuhiro Iwamatsu4398d552012-05-15 15:49:39 +0000367 port_info->phy_addr, dev, CONFIG_SH_ETHER_PHY_MODE);
Yoshihiro Shimodabd1024b2011-10-11 18:10:14 +0900368 port_info->phydev = phydev;
369 phy_config(phydev);
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900370
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900371 return ret;
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900372}
373
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900374static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900375{
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900376 int port = eth->port, ret = 0;
Yoshihiro Shimodabd1024b2011-10-11 18:10:14 +0900377 u32 val;
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900378 struct sh_eth_info *port_info = &eth->port_info[port];
Mike Frysingerc527ce92009-02-11 19:14:09 -0500379 struct eth_device *dev = port_info->dev;
Yoshihiro Shimodabd1024b2011-10-11 18:10:14 +0900380 struct phy_device *phy;
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900381
382 /* Configure e-dmac registers */
Nobuhiro Iwamatsuf8b75072013-08-22 13:22:02 +0900383 sh_eth_write(eth, (sh_eth_read(eth, EDMR) & ~EMDR_DESC_R) |
384 (EMDR_DESC | EDMR_EL), EDMR);
385
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000386 sh_eth_write(eth, 0, EESIPR);
387 sh_eth_write(eth, 0, TRSCER);
388 sh_eth_write(eth, 0, TFTR);
389 sh_eth_write(eth, (FIFO_SIZE_T | FIFO_SIZE_R), FDR);
390 sh_eth_write(eth, RMCR_RST, RMCR);
Nobuhiro Iwamatsu62cbddc2014-01-23 07:52:18 +0900391#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000392 sh_eth_write(eth, 0, RPADIR);
Yoshihiro Shimoda903de462011-01-18 17:53:45 +0900393#endif
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000394 sh_eth_write(eth, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR);
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900395
396 /* Configure e-mac registers */
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000397 sh_eth_write(eth, 0, ECSIPR);
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900398
399 /* Set Mac address */
Mike Frysingerc527ce92009-02-11 19:14:09 -0500400 val = dev->enetaddr[0] << 24 | dev->enetaddr[1] << 16 |
401 dev->enetaddr[2] << 8 | dev->enetaddr[3];
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000402 sh_eth_write(eth, val, MAHR);
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900403
Mike Frysingerc527ce92009-02-11 19:14:09 -0500404 val = dev->enetaddr[4] << 8 | dev->enetaddr[5];
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000405 sh_eth_write(eth, val, MALR);
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900406
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000407 sh_eth_write(eth, RFLR_RFL_MIN, RFLR);
Yoshihiro Shimoda26235092012-06-26 16:38:06 +0000408#if defined(SH_ETH_TYPE_GETHER)
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000409 sh_eth_write(eth, 0, PIPR);
Nobuhiro Iwamatsu62cbddc2014-01-23 07:52:18 +0900410#endif
411#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000412 sh_eth_write(eth, APR_AP, APR);
413 sh_eth_write(eth, MPR_MP, MPR);
414 sh_eth_write(eth, TPAUSER_TPAUSE, TPAUSER);
Nobuhiro Iwamatsu3bb4cc32011-11-14 16:56:59 +0900415#endif
416
Nobuhiro Iwamatsudcd5a592012-08-02 22:08:40 +0000417#if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000418 sh_eth_write(eth, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
Nobuhiro Iwamatsu17243742014-06-24 17:01:08 +0900419#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
Nobuhiro Iwamatsua341b7e2014-11-04 09:13:40 +0900420 defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
Nobuhiro Iwamatsu87076782013-08-22 13:22:04 +0900421 sh_eth_write(eth, sh_eth_read(eth, RMIIMR) | 0x1, RMIIMR);
Nobuhiro Iwamatsu4398d552012-05-15 15:49:39 +0000422#endif
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900423 /* Configure phy */
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900424 ret = sh_eth_phy_config(eth);
425 if (ret) {
Nobuhiro Iwamatsu88a4c2e2009-06-25 16:33:04 +0900426 printf(SHETHER_NAME ": phy config timeout\n");
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900427 goto err_phy_cfg;
428 }
Yoshihiro Shimodabd1024b2011-10-11 18:10:14 +0900429 phy = port_info->phydev;
Timur Tabi11af8d62012-07-09 08:52:43 +0000430 ret = phy_startup(phy);
431 if (ret) {
432 printf(SHETHER_NAME ": phy startup failure\n");
433 return ret;
434 }
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900435
Nobuhiro Iwamatsu3bb4cc32011-11-14 16:56:59 +0900436 val = 0;
437
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900438 /* Set the transfer speed */
Yoshihiro Shimodabd1024b2011-10-11 18:10:14 +0900439 if (phy->speed == 100) {
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900440 printf(SHETHER_NAME ": 100Base/");
Yoshihiro Shimoda26235092012-06-26 16:38:06 +0000441#if defined(SH_ETH_TYPE_GETHER)
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000442 sh_eth_write(eth, GECMR_100B, GECMR);
Yoshihiro Shimodae3bb3252012-11-04 15:54:30 +0000443#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000444 sh_eth_write(eth, 1, RTRATE);
Nobuhiro Iwamatsu47ce8892013-09-24 15:38:33 +0900445#elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_R8A7790) || \
Nobuhiro Iwamatsua341b7e2014-11-04 09:13:40 +0900446 defined(CONFIG_R8A7791) || defined(CONFIG_R8A7793) || \
447 defined(CONFIG_R8A7794)
Nobuhiro Iwamatsu3bb4cc32011-11-14 16:56:59 +0900448 val = ECMR_RTM;
449#endif
Yoshihiro Shimodabd1024b2011-10-11 18:10:14 +0900450 } else if (phy->speed == 10) {
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900451 printf(SHETHER_NAME ": 10Base/");
Yoshihiro Shimoda26235092012-06-26 16:38:06 +0000452#if defined(SH_ETH_TYPE_GETHER)
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000453 sh_eth_write(eth, GECMR_10B, GECMR);
Yoshihiro Shimodae3bb3252012-11-04 15:54:30 +0000454#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000455 sh_eth_write(eth, 0, RTRATE);
Yoshihiro Shimoda903de462011-01-18 17:53:45 +0900456#endif
Nobuhiro Iwamatsu3bb4cc32011-11-14 16:56:59 +0900457 }
Yoshihiro Shimoda26235092012-06-26 16:38:06 +0000458#if defined(SH_ETH_TYPE_GETHER)
Nobuhiro Iwamatsu4398d552012-05-15 15:49:39 +0000459 else if (phy->speed == 1000) {
460 printf(SHETHER_NAME ": 1000Base/");
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000461 sh_eth_write(eth, GECMR_1000B, GECMR);
Nobuhiro Iwamatsu4398d552012-05-15 15:49:39 +0000462 }
463#endif
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900464
465 /* Check if full duplex mode is supported by the phy */
Yoshihiro Shimodabd1024b2011-10-11 18:10:14 +0900466 if (phy->duplex) {
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900467 printf("Full\n");
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000468 sh_eth_write(eth, val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM),
469 ECMR);
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900470 } else {
471 printf("Half\n");
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000472 sh_eth_write(eth, val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE), ECMR);
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900473 }
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900474
475 return ret;
476
477err_phy_cfg:
478 return ret;
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900479}
480
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900481static void sh_eth_start(struct sh_eth_dev *eth)
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900482{
483 /*
484 * Enable the e-dmac receiver only. The transmitter will be enabled when
485 * we have something to transmit
486 */
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000487 sh_eth_write(eth, EDRRR_R, EDRRR);
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900488}
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900489
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900490static void sh_eth_stop(struct sh_eth_dev *eth)
491{
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000492 sh_eth_write(eth, ~EDRRR_R, EDRRR);
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900493}
494
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900495int sh_eth_init(struct eth_device *dev, bd_t *bd)
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900496{
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900497 int ret = 0;
498 struct sh_eth_dev *eth = dev->priv;
499
500 ret = sh_eth_reset(eth);
501 if (ret)
502 goto err;
503
504 ret = sh_eth_desc_init(eth);
505 if (ret)
506 goto err;
507
508 ret = sh_eth_config(eth, bd);
509 if (ret)
510 goto err_config;
511
512 sh_eth_start(eth);
513
514 return ret;
515
516err_config:
517 sh_eth_tx_desc_free(eth);
518 sh_eth_rx_desc_free(eth);
519
520err:
521 return ret;
522}
523
524void sh_eth_halt(struct eth_device *dev)
525{
526 struct sh_eth_dev *eth = dev->priv;
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900527 sh_eth_stop(eth);
528}
529
530int sh_eth_initialize(bd_t *bd)
531{
Nobuhiro Iwamatsue2752db2014-01-23 07:52:19 +0900532 int ret = 0;
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900533 struct sh_eth_dev *eth = NULL;
Nobuhiro Iwamatsue2752db2014-01-23 07:52:19 +0900534 struct eth_device *dev = NULL;
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900535
Nobuhiro Iwamatsue2752db2014-01-23 07:52:19 +0900536 eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev));
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900537 if (!eth) {
538 printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
539 ret = -ENOMEM;
540 goto err;
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900541 }
542
Nobuhiro Iwamatsue2752db2014-01-23 07:52:19 +0900543 dev = (struct eth_device *)malloc(sizeof(struct eth_device));
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900544 if (!dev) {
545 printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
546 ret = -ENOMEM;
547 goto err;
548 }
Nobuhiro Iwamatsue2752db2014-01-23 07:52:19 +0900549 memset(dev, 0, sizeof(struct eth_device));
550 memset(eth, 0, sizeof(struct sh_eth_dev));
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900551
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900552 eth->port = CONFIG_SH_ETHER_USE_PORT;
553 eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
554
Nobuhiro Iwamatsue2752db2014-01-23 07:52:19 +0900555 dev->priv = (void *)eth;
556 dev->iobase = 0;
557 dev->init = sh_eth_init;
558 dev->halt = sh_eth_halt;
559 dev->send = sh_eth_send;
560 dev->recv = sh_eth_recv;
561 eth->port_info[eth->port].dev = dev;
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900562
563 sprintf(dev->name, SHETHER_NAME);
564
Nobuhiro Iwamatsue2752db2014-01-23 07:52:19 +0900565 /* Register Device to EtherNet subsystem */
566 eth_register(dev);
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900567
Yoshihiro Shimodabd1024b2011-10-11 18:10:14 +0900568 bb_miiphy_buses[0].priv = eth;
569 miiphy_register(dev->name, bb_miiphy_read, bb_miiphy_write);
570
Mike Frysingerc527ce92009-02-11 19:14:09 -0500571 if (!eth_getenv_enetaddr("ethaddr", dev->enetaddr))
572 puts("Please set MAC address\n");
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900573
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900574 return ret;
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900575
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900576err:
Nobuhiro Iwamatsubd3980c2008-11-21 12:04:18 +0900577 if (dev)
578 free(dev);
579
580 if (eth)
581 free(eth);
582
583 printf(SHETHER_NAME ": Failed\n");
584 return ret;
Nobuhiro Iwamatsu9751ee02008-06-11 21:05:00 +0900585}
Yoshihiro Shimodabd1024b2011-10-11 18:10:14 +0900586
587/******* for bb_miiphy *******/
588static int sh_eth_bb_init(struct bb_miiphy_bus *bus)
589{
590 return 0;
591}
592
593static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
594{
595 struct sh_eth_dev *eth = bus->priv;
Yoshihiro Shimodabd1024b2011-10-11 18:10:14 +0900596
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000597 sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MMD, PIR);
Yoshihiro Shimodabd1024b2011-10-11 18:10:14 +0900598
599 return 0;
600}
601
602static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
603{
604 struct sh_eth_dev *eth = bus->priv;
Yoshihiro Shimodabd1024b2011-10-11 18:10:14 +0900605
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000606 sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MMD, PIR);
Yoshihiro Shimodabd1024b2011-10-11 18:10:14 +0900607
608 return 0;
609}
610
611static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
612{
613 struct sh_eth_dev *eth = bus->priv;
Yoshihiro Shimodabd1024b2011-10-11 18:10:14 +0900614
615 if (v)
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000616 sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MDO, PIR);
Yoshihiro Shimodabd1024b2011-10-11 18:10:14 +0900617 else
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000618 sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MDO, PIR);
Yoshihiro Shimodabd1024b2011-10-11 18:10:14 +0900619
620 return 0;
621}
622
623static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
624{
625 struct sh_eth_dev *eth = bus->priv;
Yoshihiro Shimodabd1024b2011-10-11 18:10:14 +0900626
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000627 *v = (sh_eth_read(eth, PIR) & PIR_MDI) >> 3;
Yoshihiro Shimodabd1024b2011-10-11 18:10:14 +0900628
629 return 0;
630}
631
632static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
633{
634 struct sh_eth_dev *eth = bus->priv;
Yoshihiro Shimodabd1024b2011-10-11 18:10:14 +0900635
636 if (v)
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000637 sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MDC, PIR);
Yoshihiro Shimodabd1024b2011-10-11 18:10:14 +0900638 else
Yoshihiro Shimoda49afb8c2012-06-26 16:38:09 +0000639 sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MDC, PIR);
Yoshihiro Shimodabd1024b2011-10-11 18:10:14 +0900640
641 return 0;
642}
643
644static int sh_eth_bb_delay(struct bb_miiphy_bus *bus)
645{
646 udelay(10);
647
648 return 0;
649}
650
651struct bb_miiphy_bus bb_miiphy_buses[] = {
652 {
653 .name = "sh_eth",
654 .init = sh_eth_bb_init,
655 .mdio_active = sh_eth_bb_mdio_active,
656 .mdio_tristate = sh_eth_bb_mdio_tristate,
657 .set_mdio = sh_eth_bb_set_mdio,
658 .get_mdio = sh_eth_bb_get_mdio,
659 .set_mdc = sh_eth_bb_set_mdc,
660 .delay = sh_eth_bb_delay,
661 }
662};
663int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);