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Wang Huan550e3dc2014-09-05 13:52:44 +08001/*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <i2c.h>
9#include <asm/io.h>
10#include <asm/arch/immap_ls102xa.h>
11#include <asm/arch/clock.h>
12#include <asm/arch/fsl_serdes.h>
Minghuan Lianda419022014-10-31 13:43:44 +080013#include <asm/pcie_layerscape.h>
Wang Huan550e3dc2014-09-05 13:52:44 +080014#include <mmc.h>
15#include <fsl_esdhc.h>
16#include <fsl_ifc.h>
Ruchika Gupta4ba4a092014-10-15 11:39:06 +053017#include <fsl_sec.h>
Wang Huan550e3dc2014-09-05 13:52:44 +080018
19#include "../common/qixis.h"
20#include "ls1021aqds_qixis.h"
Zhao Qiang63e75fd2014-09-26 16:25:32 +080021#ifdef CONFIG_U_QE
22#include "../../../drivers/qe/qe.h"
23#endif
Wang Huan550e3dc2014-09-05 13:52:44 +080024
25DECLARE_GLOBAL_DATA_PTR;
26
27enum {
28 MUX_TYPE_SD_PCI4,
29 MUX_TYPE_SD_PC_SA_SG_SG,
30 MUX_TYPE_SD_PC_SA_PC_SG,
31 MUX_TYPE_SD_PC_SG_SG,
32};
33
34int checkboard(void)
35{
36 char buf[64];
37 u8 sw;
38
39 puts("Board: LS1021AQDS\n");
40
41 sw = QIXIS_READ(brdcfg[0]);
42 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
43
44 if (sw < 0x8)
45 printf("vBank: %d\n", sw);
46 else if (sw == 0x8)
47 puts("PromJet\n");
48 else if (sw == 0x9)
49 puts("NAND\n");
50 else if (sw == 0x15)
51 printf("IFCCard\n");
52 else
53 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
54
55 printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n",
56 QIXIS_READ(id), QIXIS_READ(arch));
57
58 printf("FPGA: v%d (%s), build %d\n",
59 (int)QIXIS_READ(scver), qixis_read_tag(buf),
60 (int)qixis_read_minor());
61
62 return 0;
63}
64
65unsigned long get_board_sys_clk(void)
66{
67 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
68
69 switch (sysclk_conf & 0x0f) {
70 case QIXIS_SYSCLK_64:
71 return 64000000;
72 case QIXIS_SYSCLK_83:
73 return 83333333;
74 case QIXIS_SYSCLK_100:
75 return 100000000;
76 case QIXIS_SYSCLK_125:
77 return 125000000;
78 case QIXIS_SYSCLK_133:
79 return 133333333;
80 case QIXIS_SYSCLK_150:
81 return 150000000;
82 case QIXIS_SYSCLK_160:
83 return 160000000;
84 case QIXIS_SYSCLK_166:
85 return 166666666;
86 }
87 return 66666666;
88}
89
90unsigned long get_board_ddr_clk(void)
91{
92 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
93
94 switch ((ddrclk_conf & 0x30) >> 4) {
95 case QIXIS_DDRCLK_100:
96 return 100000000;
97 case QIXIS_DDRCLK_125:
98 return 125000000;
99 case QIXIS_DDRCLK_133:
100 return 133333333;
101 }
102 return 66666666;
103}
104
105int dram_init(void)
106{
107 gd->ram_size = initdram(0);
108
109 return 0;
110}
111
112#ifdef CONFIG_FSL_ESDHC
113struct fsl_esdhc_cfg esdhc_cfg[1] = {
114 {CONFIG_SYS_FSL_ESDHC_ADDR},
115};
116
117int board_mmc_init(bd_t *bis)
118{
119 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
120
121 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
122}
123#endif
124
125int select_i2c_ch_pca9547(u8 ch)
126{
127 int ret;
128
129 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
130 if (ret) {
131 puts("PCA: failed to select proper channel\n");
132 return ret;
133 }
134
135 return 0;
136}
137
138int board_early_init_f(void)
139{
140 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
141 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
142
143#ifdef CONFIG_TSEC_ENET
Wang Huan550e3dc2014-09-05 13:52:44 +0800144 out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
Alison Wang0ab17232014-10-17 15:26:36 +0800145 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
Wang Huan550e3dc2014-09-05 13:52:44 +0800146#endif
147
148#ifdef CONFIG_FSL_IFC
149 init_early_memctl_regs();
150#endif
151
152 /* Workaround for the issue that DDR could not respond to
153 * barrier transaction which is generated by executing DSB/ISB
154 * instruction. Set CCI-400 control override register to
155 * terminate the barrier transaction. After DDR is initialized,
156 * allow barrier transaction to DDR again */
157 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
158
159 return 0;
160}
161
162int config_board_mux(int ctrl_type)
163{
164 u8 reg12;
165
166 reg12 = QIXIS_READ(brdcfg[12]);
167
168 switch (ctrl_type) {
169 case MUX_TYPE_SD_PCI4:
170 reg12 = 0x38;
171 break;
172 case MUX_TYPE_SD_PC_SA_SG_SG:
173 reg12 = 0x01;
174 break;
175 case MUX_TYPE_SD_PC_SA_PC_SG:
176 reg12 = 0x01;
177 break;
178 case MUX_TYPE_SD_PC_SG_SG:
179 reg12 = 0x21;
180 break;
181 default:
182 printf("Wrong mux interface type\n");
183 return -1;
184 }
185
186 QIXIS_WRITE(brdcfg[12], reg12);
187
188 return 0;
189}
190
191int config_serdes_mux(void)
192{
193 struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
194 u32 cfg;
195
196 cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
197 cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT;
198
199 switch (cfg) {
200 case 0x0:
201 config_board_mux(MUX_TYPE_SD_PCI4);
202 break;
203 case 0x30:
204 config_board_mux(MUX_TYPE_SD_PC_SA_SG_SG);
205 break;
206 case 0x60:
207 config_board_mux(MUX_TYPE_SD_PC_SG_SG);
208 break;
209 case 0x70:
210 config_board_mux(MUX_TYPE_SD_PC_SA_PC_SG);
211 break;
212 default:
213 printf("SRDS1 prtcl:0x%x\n", cfg);
214 break;
215 }
216
217 return 0;
218}
219
Ruchika Gupta4ba4a092014-10-15 11:39:06 +0530220#if defined(CONFIG_MISC_INIT_R)
221int misc_init_r(void)
222{
223#ifdef CONFIG_FSL_CAAM
224 return sec_init();
225#endif
226}
227#endif
228
Wang Huan550e3dc2014-09-05 13:52:44 +0800229int board_init(void)
230{
231 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
232
233 /* Set CCI-400 control override register to
234 * enable barrier transaction */
235 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
Jason Jin644bc7e2014-10-17 15:26:32 +0800236 /*
237 * Set CCI-400 Slave interface S0, S1, S2 Shareable Override Register
238 * All transactions are treated as non-shareable
239 */
240 out_le32(&cci->slave[0].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
241 out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
242 out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
Wang Huan550e3dc2014-09-05 13:52:44 +0800243
244 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
245
246#ifndef CONFIG_SYS_FSL_NO_SERDES
247 fsl_serdes_init();
248 config_serdes_mux();
249#endif
Zhao Qiang63e75fd2014-09-26 16:25:32 +0800250
251#ifdef CONFIG_U_QE
252 u_qe_init();
253#endif
254
Wang Huan550e3dc2014-09-05 13:52:44 +0800255 return 0;
256}
257
Simon Glasse895a4b2014-10-23 18:58:47 -0600258int ft_board_setup(void *blob, bd_t *bd)
Wang Huan550e3dc2014-09-05 13:52:44 +0800259{
260 ft_cpu_setup(blob, bd);
Simon Glasse895a4b2014-10-23 18:58:47 -0600261
Minghuan Lianda419022014-10-31 13:43:44 +0800262#ifdef CONFIG_PCIE_LAYERSCAPE
263 ft_pcie_setup(blob, bd);
264#endif
265
Simon Glasse895a4b2014-10-23 18:58:47 -0600266 return 0;
Wang Huan550e3dc2014-09-05 13:52:44 +0800267}
268
269u8 flash_read8(void *addr)
270{
271 return __raw_readb(addr + 1);
272}
273
274void flash_write16(u16 val, void *addr)
275{
276 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
277
278 __raw_writew(shftval, addr);
279}
280
281u16 flash_read16(void *addr)
282{
283 u16 val = __raw_readw(addr);
284
285 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
286}