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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Veli-Pekka Peltolac1393bb2012-07-09 03:14:50 +00002/*
3 * Bluegiga APX4 Development Kit
4 *
5 * Copyright (C) 2012 Bluegiga Technologies Oy
6 *
7 * Authors:
8 * Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
9 * Lauri Hintsala <lauri.hintsala@bluegiga.com>
10 *
11 * Based on m28evk.c:
12 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
13 * on behalf of DENX Software Engineering GmbH
Veli-Pekka Peltolac1393bb2012-07-09 03:14:50 +000014 */
15
16#include <common.h>
Simon Glass691d7192020-05-10 11:40:02 -060017#include <init.h>
Simon Glass90526e92020-05-10 11:39:56 -060018#include <net.h>
Veli-Pekka Peltolac1393bb2012-07-09 03:14:50 +000019#include <asm/gpio.h>
20#include <asm/io.h>
Simon Glass5d982852017-05-17 08:23:00 -060021#include <asm/setup.h>
Veli-Pekka Peltolac1393bb2012-07-09 03:14:50 +000022#include <asm/arch/imx-regs.h>
23#include <asm/arch/iomux-mx28.h>
24#include <asm/arch/clock.h>
25#include <asm/arch/sys_proto.h>
Simon Glass7b51b572019-08-01 09:46:52 -060026#include <env.h>
Veli-Pekka Peltolac1393bb2012-07-09 03:14:50 +000027#include <linux/mii.h>
28#include <miiphy.h>
29#include <netdev.h>
30#include <errno.h>
31
32DECLARE_GLOBAL_DATA_PTR;
33
34/* Functions */
35int board_early_init_f(void)
36{
37 /* IO0 clock at 480MHz */
Otavio Salvadorbf48fcb2013-01-11 03:19:03 +000038 mxs_set_ioclk(MXC_IOCLK0, 480000);
Veli-Pekka Peltolac1393bb2012-07-09 03:14:50 +000039 /* IO1 clock at 480MHz */
Otavio Salvadorbf48fcb2013-01-11 03:19:03 +000040 mxs_set_ioclk(MXC_IOCLK1, 480000);
Veli-Pekka Peltolac1393bb2012-07-09 03:14:50 +000041
42 /* SSP0 clock at 96MHz */
Otavio Salvadorbf48fcb2013-01-11 03:19:03 +000043 mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
Veli-Pekka Peltolac1393bb2012-07-09 03:14:50 +000044
45 return 0;
46}
47
48int dram_init(void)
49{
Otavio Salvador72f8ebf2012-08-19 04:58:30 +000050 return mxs_dram_init();
Veli-Pekka Peltolac1393bb2012-07-09 03:14:50 +000051}
52
53int board_init(void)
54{
55 /* Adress of boot parameters */
56 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
57
58 return 0;
59}
60
61#ifdef CONFIG_CMD_MMC
Masahiro Yamadab75d8dc2020-06-26 15:13:33 +090062int board_mmc_init(struct bd_info *bis)
Veli-Pekka Peltolac1393bb2012-07-09 03:14:50 +000063{
Marek Vasut90bc2bf2013-01-22 15:01:03 +000064 return mxsmmc_initialize(bis, 0, NULL, NULL);
Veli-Pekka Peltolac1393bb2012-07-09 03:14:50 +000065}
66#endif
67
68
69#ifdef CONFIG_CMD_NET
70
71#define MII_PHY_CTRL2 0x1f
72int fecmxc_mii_postcall(int phy)
73{
74 /* change PHY RMII clock to 50MHz */
75 miiphy_write("FEC", 0, MII_PHY_CTRL2, 0x8180);
76
77 return 0;
78}
79
Masahiro Yamadab75d8dc2020-06-26 15:13:33 +090080int board_eth_init(struct bd_info *bis)
Veli-Pekka Peltolac1393bb2012-07-09 03:14:50 +000081{
82 int ret;
83 struct eth_device *dev;
84
85 ret = cpu_eth_init(bis);
86 if (ret) {
87 printf("FEC MXS: Unable to init FEC clocks\n");
88 return ret;
89 }
90
91 ret = fecmxc_initialize(bis);
92 if (ret) {
93 printf("FEC MXS: Unable to init FEC\n");
94 return ret;
95 }
96
97 dev = eth_get_dev_by_name("FEC");
98 if (!dev) {
99 printf("FEC MXS: Unable to get FEC device entry\n");
100 return -EINVAL;
101 }
102
103 ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
104 if (ret) {
105 printf("FEC MXS: Unable to register FEC MII postcall\n");
106 return ret;
107 }
108
109 return ret;
110}
111#endif
112
113#ifdef CONFIG_SERIAL_TAG
114#define MXS_OCOTP_MAX_TIMEOUT 1000000
115void get_board_serial(struct tag_serialnr *serialnr)
116{
Otavio Salvador9c471142012-08-05 09:05:31 +0000117 struct mxs_ocotp_regs *ocotp_regs =
118 (struct mxs_ocotp_regs *)MXS_OCOTP_BASE;
Veli-Pekka Peltolac1393bb2012-07-09 03:14:50 +0000119
120 serialnr->high = 0;
121 serialnr->low = 0;
122
123 writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set);
124
Otavio Salvadorfa7a51c2012-08-13 09:53:12 +0000125 if (mxs_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
Veli-Pekka Peltolac1393bb2012-07-09 03:14:50 +0000126 MXS_OCOTP_MAX_TIMEOUT)) {
127 printf("MXS: Can't get serial number from OCOTP\n");
128 return;
129 }
130
131 serialnr->low = readl(&ocotp_regs->hw_ocotp_cust3);
132}
133#endif
134
135#ifdef CONFIG_REVISION_TAG
136u32 get_board_rev(void)
137{
Simon Glass00caae62017-08-03 12:22:12 -0600138 if (env_get("revision#") != NULL)
139 return simple_strtoul(env_get("revision#"), NULL, 10);
Veli-Pekka Peltolac1393bb2012-07-09 03:14:50 +0000140 return 0;
141}
142#endif