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Kumar Gala9490a7f2008-07-25 13:31:05 -05001/*
2 * Copyright 2008 Freescale Semiconductor, Inc.
3 *
4 * (C) Copyright 2000
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#include <common.h>
27#include <asm/mmu.h>
28
29struct fsl_e_tlb_entry tlb_table[] = {
30 /* TLB 0 - for temp stack in cache */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020031 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
Kumar Gala9490a7f2008-07-25 13:31:05 -050032 MAS3_SX|MAS3_SW|MAS3_SR, 0,
33 0, 0, BOOKE_PAGESZ_4K, 0),
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020034 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
Kumar Gala9490a7f2008-07-25 13:31:05 -050035 MAS3_SX|MAS3_SW|MAS3_SR, 0,
36 0, 0, BOOKE_PAGESZ_4K, 0),
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020037 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
Kumar Gala9490a7f2008-07-25 13:31:05 -050038 MAS3_SX|MAS3_SW|MAS3_SR, 0,
39 0, 0, BOOKE_PAGESZ_4K, 0),
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020040 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
Kumar Gala9490a7f2008-07-25 13:31:05 -050041 MAS3_SX|MAS3_SW|MAS3_SR, 0,
42 0, 0, BOOKE_PAGESZ_4K, 0),
43
Kumar Gala52b565f2008-12-02 14:19:33 -060044 SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE_PHYS,
Kumar Gala9490a7f2008-07-25 13:31:05 -050045 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
46 0, 0, BOOKE_PAGESZ_4K, 0),
47
48 /* TLB 1 */
49 /* *I*G* - CCSRBAR */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020050 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
Kumar Gala9490a7f2008-07-25 13:31:05 -050051 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
52 0, 0, BOOKE_PAGESZ_1M, 1),
53
54 /* W**G* - Flash/promjet, localbus */
55 /* This will be changed to *I*G* after relocation to RAM. */
Kumar Galac953ddf2008-12-02 14:19:34 -060056 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
Kumar Gala7c0d4a72008-09-22 14:11:11 -050057 MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
Kumar Gala9490a7f2008-07-25 13:31:05 -050058 0, 1, BOOKE_PAGESZ_256M, 1),
59
60 /* *I*G* - PCI */
Kumar Gala5af0fdd2008-12-02 16:08:39 -060061 SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
Kumar Gala9490a7f2008-07-25 13:31:05 -050062 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
63 0, 2, BOOKE_PAGESZ_1G, 1),
64
65 /* *I*G* - PCI I/O */
Kumar Galaaca5f012008-12-02 16:08:40 -060066 SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_VIRT, CONFIG_SYS_PCI1_IO_PHYS,
Kumar Gala9490a7f2008-07-25 13:31:05 -050067 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
68 0, 3, BOOKE_PAGESZ_256K, 1),
Jason Jinc57fc282008-10-31 05:07:04 -050069
70 /* *I*G - NAND */
71 SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
72 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
73 0, 4, BOOKE_PAGESZ_1M, 1),
Kumar Gala9490a7f2008-07-25 13:31:05 -050074};
75
76int num_tlb_entries = ARRAY_SIZE(tlb_table);