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Stefan Roese16c0cc12007-03-21 13:39:57 +01001/*
2 * (C) Copyright 2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/************************************************************************
25 * acadia.h - configuration for AMCC Acadia (405EZ)
26 ***********************************************************************/
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*-----------------------------------------------------------------------
32 * High Level Configuration Options
33 *----------------------------------------------------------------------*/
Stefan Roese3cb86f32007-03-24 15:45:34 +010034#define CONFIG_ACADIA 1 /* Board is Acadia */
35#define CONFIG_4xx 1 /* ... PPC4xx family */
36#define CONFIG_405EZ 1 /* Specifc 405EZ support*/
Stefan Roese490f2042008-06-06 15:55:03 +020037
Wolfgang Denk2ae18242010-10-06 09:05:45 +020038#ifndef CONFIG_SYS_TEXT_BASE
39#define CONFIG_SYS_TEXT_BASE 0xFFF80000
40#endif
41
Stefan Roese490f2042008-06-06 15:55:03 +020042/*
43 * Include common defines/options for all AMCC eval boards
44 */
45#define CONFIG_HOSTNAME acadia
46#include "amcc-common.h"
47
Stefan Roese5d4a1792007-05-24 08:22:09 +020048/* Detect Acadia PLL input clock automatically via CPLD bit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020049#define CONFIG_SYS_CLK_FREQ ((in8(CONFIG_SYS_CPLD_BASE + 0) == 0x0c) ? \
Stefan Roese5d4a1792007-05-24 08:22:09 +020050 66666666 : 33333000)
Stefan Roese16c0cc12007-03-21 13:39:57 +010051
Stefan Roese3cb86f32007-03-24 15:45:34 +010052#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
53#define CONFIG_MISC_INIT_F 1 /* Call misc_init_f */
Stefan Roese16c0cc12007-03-21 13:39:57 +010054
55#define CONFIG_NO_SERIAL_EEPROM
56/*#undef CONFIG_NO_SERIAL_EEPROM*/
57
58#ifdef CONFIG_NO_SERIAL_EEPROM
Stefan Roese16c0cc12007-03-21 13:39:57 +010059/*----------------------------------------------------------------------------
60 * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
61 * assuming a 66MHz input clock to the 405EZ.
62 *---------------------------------------------------------------------------*/
63/* #define PLLMR0_100_100_12 */
64#define PLLMR0_200_133_66
65/* #define PLLMR0_266_160_80 */
66/* #define PLLMR0_333_166_83 */
67#endif
68
69/*-----------------------------------------------------------------------
70 * Base addresses -- Note these are effective addresses where the
71 * actual resources get mapped (not physical addresses)
72 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020073#define CONFIG_SYS_FLASH_BASE 0xfe000000
74#define CONFIG_SYS_CPLD_BASE 0x80000000
75#define CONFIG_SYS_NAND_ADDR 0xd0000000
76#define CONFIG_SYS_USB_HOST 0xef603000 /* USB OHCI 1.1 controller */
Stefan Roese16c0cc12007-03-21 13:39:57 +010077
Stefan Roese3cb86f32007-03-24 15:45:34 +010078/*-----------------------------------------------------------------------
79 * Initial RAM & stack pointer
80 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020081#define CONFIG_SYS_TEMP_STACK_OCM 1 /* OCM as init ram */
Stefan Roese3cb86f32007-03-24 15:45:34 +010082
83/* On Chip Memory location */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020084#define CONFIG_SYS_OCM_DATA_ADDR 0xf8000000
85#define CONFIG_SYS_OCM_DATA_SIZE 0x4000 /* 16K of onchip SRAM */
86#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SRAM */
Wolfgang Denk553f0982010-10-26 13:32:32 +020087#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
Stefan Roese3cb86f32007-03-24 15:45:34 +010088
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +020089#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Stefan Roese3cb86f32007-03-24 15:45:34 +010091
92/*-----------------------------------------------------------------------
93 * Serial Port
94 *----------------------------------------------------------------------*/
Stefan Roese550650d2010-09-20 16:05:31 +020095#define CONFIG_CONS_INDEX 1 /* Use UART0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
97#define CONFIG_SYS_BASE_BAUD 691200
Stefan Roese3cb86f32007-03-24 15:45:34 +010098
99/*-----------------------------------------------------------------------
100 * Environment
101 *----------------------------------------------------------------------*/
Stefan Roese16c0cc12007-03-21 13:39:57 +0100102#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200103#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
Stefan Roese16c0cc12007-03-21 13:39:57 +0100104#else
Jean-Christophe PLAGNIOL-VILLARD51bfee12008-09-10 22:47:58 +0200105#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200106#define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */
Stefan Roese16c0cc12007-03-21 13:39:57 +0100107#endif
108
Stefan Roese3cb86f32007-03-24 15:45:34 +0100109/*-----------------------------------------------------------------------
110 * FLASH related
111 *----------------------------------------------------------------------*/
Stefan Roesec440bfe2007-06-06 11:42:13 +0200112#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200114#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
Stefan Roese3cb86f32007-03-24 15:45:34 +0100115
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
117#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
118#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
Stefan Roese3cb86f32007-03-24 15:45:34 +0100119
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
121#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
Stefan Roese3cb86f32007-03-24 15:45:34 +0100122
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
124#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
Stefan Roese3cb86f32007-03-24 15:45:34 +0100125
Stefan Roesec440bfe2007-06-06 11:42:13 +0200126#else
Stefan Roese8a805df2010-09-16 14:01:53 +0200127/*
128 * No NOR-flash on Acadia when NAND-booting. We need to undef the
129 * NOR device-tree fixup code as well, since flash_info is not defined
130 * in this case.
131 */
132#define CONFIG_SYS_NO_FLASH 1
133#undef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
Stefan Roesec440bfe2007-06-06 11:42:13 +0200134#endif
135
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200136#ifdef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200137#define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200139#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
Stefan Roese3cb86f32007-03-24 15:45:34 +0100140
141/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200142#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
143#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Stefan Roese3cb86f32007-03-24 15:45:34 +0100144#endif
145
Stefan Roesec440bfe2007-06-06 11:42:13 +0200146/*
147 * IPL (Initial Program Loader, integrated inside CPU)
148 * Will load first 4k from NAND (SPL) into cache and execute it from there.
149 *
150 * SPL (Secondary Program Loader)
151 * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
152 * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
153 * controller and the NAND controller so that the special U-Boot image can be
154 * loaded from NAND to SDRAM.
155 *
156 * NUB (NAND U-Boot)
157 * This NAND U-Boot (NUB) is a special U-Boot version which can be started
158 * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
159 *
160 * On 440EPx the SPL is copied to SDRAM before the NAND controller is
161 * set up. While still running from cache, I experienced problems accessing
162 * the NAND controller. sr - 2006-08-25
163 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
165#define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
166#define CONFIG_SYS_NAND_BOOT_SPL_DST (CONFIG_SYS_OCM_DATA_ADDR + (16 << 10)) /* Copy SPL here*/
167#define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
168#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr */
169#define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
Stefan Roesec440bfe2007-06-06 11:42:13 +0200170
171/*
172 * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
173 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
175#define CONFIG_SYS_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
Stefan Roesec440bfe2007-06-06 11:42:13 +0200176
177/*
178 * Now the NAND chip has to be defined (no autodetection used!)
179 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */
181#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
182#define CONFIG_SYS_NAND_PAGE_COUNT 32 /* NAND chip page count */
183#define CONFIG_SYS_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
184#undef CONFIG_SYS_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */
Stefan Roesec440bfe2007-06-06 11:42:13 +0200185
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_NAND_ECCSIZE 256
187#define CONFIG_SYS_NAND_ECCBYTES 3
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_NAND_OOBSIZE 16
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#define CONFIG_SYS_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
Stefan Roesec440bfe2007-06-06 11:42:13 +0200190
Jean-Christophe PLAGNIOL-VILLARD51bfee12008-09-10 22:47:58 +0200191#ifdef CONFIG_ENV_IS_IN_NAND
Stefan Roesec440bfe2007-06-06 11:42:13 +0200192/*
193 * For NAND booting the environment is embedded in the U-Boot image. Please take
194 * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
195 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
197#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200198#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
Stefan Roesec440bfe2007-06-06 11:42:13 +0200199#endif
200
Stefan Roese3cb86f32007-03-24 15:45:34 +0100201/*-----------------------------------------------------------------------
202 * RAM (CRAM)
203 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_MBYTES_RAM 64 /* 64MB */
Stefan Roese3cb86f32007-03-24 15:45:34 +0100205
206/*-----------------------------------------------------------------------
207 * I2C
208 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
Stefan Roese3cb86f32007-03-24 15:45:34 +0100210
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#define CONFIG_SYS_I2C_MULTI_EEPROMS
212#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
213#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
214#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
215#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
Stefan Roese3cb86f32007-03-24 15:45:34 +0100216
217/* I2C SYSMON (LM75, AD7414 is almost compatible) */
218#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
219#define CONFIG_DTT_AD7414 1 /* use AD7414 */
220#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_DTT_MAX_TEMP 70
222#define CONFIG_SYS_DTT_LOW_TEMP -30
223#define CONFIG_SYS_DTT_HYSTERESIS 3
Stefan Roese3cb86f32007-03-24 15:45:34 +0100224
Stefan Roese3cb86f32007-03-24 15:45:34 +0100225/*-----------------------------------------------------------------------
226 * Ethernet
227 *----------------------------------------------------------------------*/
Stefan Roese3cb86f32007-03-24 15:45:34 +0100228#define CONFIG_PHY_ADDR 0 /* PHY address */
Stefan Roesed1c1ba82008-05-08 10:48:58 +0200229#define CONFIG_HAS_ETH0 1
Stefan Roese3cb86f32007-03-24 15:45:34 +0100230
Stefan Roese490f2042008-06-06 15:55:03 +0200231/*
232 * Default environment variables
233 */
Stefan Roese16c0cc12007-03-21 13:39:57 +0100234#define CONFIG_EXTRA_ENV_SETTINGS \
Stefan Roese490f2042008-06-06 15:55:03 +0200235 CONFIG_AMCC_DEF_ENV \
Stefan Roese84a45d32009-09-11 17:09:45 +0200236 CONFIG_AMCC_DEF_ENV_POWERPC \
237 CONFIG_AMCC_DEF_ENV_PPC_OLD \
Stefan Roese490f2042008-06-06 15:55:03 +0200238 CONFIG_AMCC_DEF_ENV_NOR_UPD \
239 CONFIG_AMCC_DEF_ENV_NAND_UPD \
Stefan Roese16c0cc12007-03-21 13:39:57 +0100240 "kernel_addr=fff10000\0" \
241 "ramdisk_addr=fff20000\0" \
Stefan Roese16c0cc12007-03-21 13:39:57 +0100242 "kozio=bootm ffc60000\0" \
243 ""
Stefan Roese16c0cc12007-03-21 13:39:57 +0100244
Stefan Roese16c0cc12007-03-21 13:39:57 +0100245#define CONFIG_USB_OHCI
246#define CONFIG_USB_STORAGE
247
Stefan Roese16c0cc12007-03-21 13:39:57 +0100248/* Partitions */
249#define CONFIG_MAC_PARTITION
250#define CONFIG_DOS_PARTITION
251#define CONFIG_ISO_PARTITION
252
253#define CONFIG_SUPPORT_VFAT
254
Jon Loeliger0b361c92007-07-04 22:31:42 -0500255/*
Stefan Roese490f2042008-06-06 15:55:03 +0200256 * Commands additional to the ones defined in amcc-common.h
Jon Loeliger079a1362007-07-10 10:12:10 -0500257 */
Jon Loeliger0b361c92007-07-04 22:31:42 -0500258#define CONFIG_CMD_DTT
Jon Loeliger0b361c92007-07-04 22:31:42 -0500259#define CONFIG_CMD_NAND
Jon Loeliger0b361c92007-07-04 22:31:42 -0500260#define CONFIG_CMD_USB
261
262/*
263 * No NOR on Acadia when NAND-booting
264 */
265#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
266#undef CONFIG_CMD_FLASH
267#undef CONFIG_CMD_IMLS
268#endif
269
Stefan Roese16c0cc12007-03-21 13:39:57 +0100270/*-----------------------------------------------------------------------
271 * NAND FLASH
272 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273#define CONFIG_SYS_MAX_NAND_DEVICE 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200274#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
275#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
Stefan Roese16c0cc12007-03-21 13:39:57 +0100276
277/*-----------------------------------------------------------------------
Stefan Roese16c0cc12007-03-21 13:39:57 +0100278 * External Bus Controller (EBC) Setup
Stefan Roese3cb86f32007-03-24 15:45:34 +0100279 *----------------------------------------------------------------------*/
Stefan Roesec440bfe2007-06-06 11:42:13 +0200280#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281#define CONFIG_SYS_NAND_CS 3
Stefan Roese3cb86f32007-03-24 15:45:34 +0100282/* Memory Bank 0 (Flash) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283#define CONFIG_SYS_EBC_PB0AP 0x03337200
284#define CONFIG_SYS_EBC_PB0CR 0xfe0bc000
Stefan Roese16c0cc12007-03-21 13:39:57 +0100285
Stefan Roesec440bfe2007-06-06 11:42:13 +0200286/* Memory Bank 3 (NAND-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200287#define CONFIG_SYS_EBC_PB3AP 0x018003c0
288#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_NAND_ADDR | 0x1c000)
Stefan Roesec440bfe2007-06-06 11:42:13 +0200289
Stefan Roese3cb86f32007-03-24 15:45:34 +0100290/* Just initial configuration for CRAM. Will be changed in memory.c to sync mode*/
291/* Memory Bank 1 (CRAM) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200292#define CONFIG_SYS_EBC_PB1AP 0x030400c0
293#define CONFIG_SYS_EBC_PB1CR 0x000bc000
Stefan Roese16c0cc12007-03-21 13:39:57 +0100294
Stefan Roese3cb86f32007-03-24 15:45:34 +0100295/* Memory Bank 2 (CRAM) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200296#define CONFIG_SYS_EBC_PB2AP 0x030400c0
297#define CONFIG_SYS_EBC_PB2CR 0x020bc000
Stefan Roesec440bfe2007-06-06 11:42:13 +0200298#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200299#define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */
Stefan Roesec440bfe2007-06-06 11:42:13 +0200300/* Memory Bank 0 (NAND-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200301#define CONFIG_SYS_EBC_PB0AP 0x018003c0
302#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1c000)
Stefan Roese16c0cc12007-03-21 13:39:57 +0100303
Stefan Roesec440bfe2007-06-06 11:42:13 +0200304/*
305 * When NAND-booting the CRAM EBC setup must be done in sync mode, since the
306 * NAND-SPL already initialized the CRAM and EBC to sync mode.
307 */
308/* Memory Bank 1 (CRAM) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200309#define CONFIG_SYS_EBC_PB1AP 0x9C0201C0
310#define CONFIG_SYS_EBC_PB1CR 0x000bc000
Stefan Roesec440bfe2007-06-06 11:42:13 +0200311
312/* Memory Bank 2 (CRAM) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313#define CONFIG_SYS_EBC_PB2AP 0x9C0201C0
314#define CONFIG_SYS_EBC_PB2CR 0x020bc000
Stefan Roesec440bfe2007-06-06 11:42:13 +0200315#endif
Stefan Roese16c0cc12007-03-21 13:39:57 +0100316
Stefan Roese3cb86f32007-03-24 15:45:34 +0100317/* Memory Bank 4 (CPLD) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200318#define CONFIG_SYS_EBC_PB4AP 0x04006000
319#define CONFIG_SYS_EBC_PB4CR (CONFIG_SYS_CPLD_BASE | 0x18000)
Stefan Roese16c0cc12007-03-21 13:39:57 +0100320
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200321#define CONFIG_SYS_EBC_CFG 0xf8400000
Stefan Roese16c0cc12007-03-21 13:39:57 +0100322
323/*-----------------------------------------------------------------------
Stefan Roese3cb86f32007-03-24 15:45:34 +0100324 * GPIO Setup
325 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#define CONFIG_SYS_GPIO_CRAM_CLK 8
327#define CONFIG_SYS_GPIO_CRAM_WAIT 9 /* GPIO-In */
328#define CONFIG_SYS_GPIO_CRAM_ADV 10
329#define CONFIG_SYS_GPIO_CRAM_CRE (32 + 21) /* GPIO-Out */
Stefan Roese3cb86f32007-03-24 15:45:34 +0100330
331/*-----------------------------------------------------------------------
Stefan Roese16c0cc12007-03-21 13:39:57 +0100332 * Definitions for GPIO_0 setup (PPC405EZ specific)
333 *
Stefan Roese5d4a1792007-05-24 08:22:09 +0200334 * GPIO0[0-2] - External Bus Controller CS_4 - CS_6 Outputs
335 * GPIO0[3] - NAND FLASH Controller CE3 (NFCE3) Output
Stefan Roese16c0cc12007-03-21 13:39:57 +0100336 * GPIO0[4] - External Bus Controller Hold Input
337 * GPIO0[5] - External Bus Controller Priority Input
338 * GPIO0[6] - External Bus Controller HLDA Output
339 * GPIO0[7] - External Bus Controller Bus Request Output
340 * GPIO0[8] - CRAM Clk Output
341 * GPIO0[9] - External Bus Controller Ready Input
342 * GPIO0[10] - CRAM Adv Output
343 * GPIO0[11-24] - NAND Flash Control Data -> Bypasses GPIO when enabled
344 * GPIO0[25] - External DMA Request Input
345 * GPIO0[26] - External DMA EOT I/O
346 * GPIO0[25] - External DMA Ack_n Output
347 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
348 * GPIO0[28-30] - Trace Outputs / PWM Inputs
349 * GPIO0[31] - PWM_8 I/O
350 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200351#define CONFIG_SYS_GPIO0_TCR 0xC0A00000
352#define CONFIG_SYS_GPIO0_OSRL 0x50004400
353#define CONFIG_SYS_GPIO0_OSRH 0x02000055
354#define CONFIG_SYS_GPIO0_ISR1L 0x00001000
355#define CONFIG_SYS_GPIO0_ISR1H 0x00000055
356#define CONFIG_SYS_GPIO0_TSRL 0x02000000
357#define CONFIG_SYS_GPIO0_TSRH 0x00000055
Stefan Roese16c0cc12007-03-21 13:39:57 +0100358
359/*-----------------------------------------------------------------------
360 * Definitions for GPIO_1 setup (PPC405EZ specific)
361 *
362 * GPIO1[0-6] - PWM_9 to PWM_15 I/O
363 * GPIO1[7] - PWM_DIV_CLK (Out) / IRQ4 Input
364 * GPIO1[8] - TS5 Output / DAC_IP_TRIG Input
365 * GPIO1[9] - TS6 Output / ADC_IP_TRIG Input
366 * GPIO1[10-12] - UART0 Control Inputs
367 * GPIO1[13] - UART0_DTR_N Output/IEEE_1588_TS Output/TMRCLK Input
368 * GPIO1[14] - UART0_RTS_N Output/SPI_SS_2_N Output
369 * GPIO1[15] - SPI_SS_3_N Output/UART0_RI_N Input
370 * GPIO1[16] - SPI_SS_1_N Output
371 * GPIO1[17-20] - Trace Output/External Interrupts IRQ0 - IRQ3 inputs
372 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200373#define CONFIG_SYS_GPIO1_TCR 0xFFFF8414
374#define CONFIG_SYS_GPIO1_OSRL 0x40000110
375#define CONFIG_SYS_GPIO1_OSRH 0x55455555
376#define CONFIG_SYS_GPIO1_ISR1L 0x15555445
377#define CONFIG_SYS_GPIO1_ISR1H 0x00000000
378#define CONFIG_SYS_GPIO1_TSRL 0x00000000
379#define CONFIG_SYS_GPIO1_TSRH 0x00000000
Stefan Roese16c0cc12007-03-21 13:39:57 +0100380
Stefan Roese16c0cc12007-03-21 13:39:57 +0100381#endif /* __CONFIG_H */