blob: f5c3d750cee634d9dae12b316ace5260d5a1b87a [file] [log] [blame]
Dan Malek35171dc2007-01-05 09:15:34 +01001/*
2 * (C) Copyright 2005, Embedded Alley Solutions, Inc.
3 * Dan Malek, <dan@embeddedalley.com>
4 * Copied from STx GP3.
5 * Updates for Silicon Tx GP3 SSA
6 *
7 * (C) Copyright 2003,Motorola Inc.
8 * Xianghua Xiao, (X.Xiao@motorola.com)
9 *
10 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
11 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +020012 * SPDX-License-Identifier: GPL-2.0+
Dan Malek35171dc2007-01-05 09:15:34 +010013 */
14
15
Dan Malek35171dc2007-01-05 09:15:34 +010016#include <common.h>
17#include <pci.h>
18#include <asm/processor.h>
Kumar Gala0e7927d2008-08-27 01:04:07 -050019#include <asm/mmu.h>
Dan Malek35171dc2007-01-05 09:15:34 +010020#include <asm/immap_85xx.h>
Wolfgang Denk28415b62011-07-25 15:15:44 +020021#include <asm/fsl_pci.h>
York Sun5614e712013-09-30 09:22:09 -070022#include <fsl_ddr_sdram.h>
Dan Malek35171dc2007-01-05 09:15:34 +010023#include <ioports.h>
24#include <asm/io.h>
Jon Loeligera30a5492008-03-04 10:03:03 -060025#include <spd_sdram.h>
Dan Malek35171dc2007-01-05 09:15:34 +010026#include <miiphy.h>
Ben Warren8ca0b3f2008-08-31 10:45:44 -070027#include <netdev.h>
Dan Malek35171dc2007-01-05 09:15:34 +010028
Dan Malek35171dc2007-01-05 09:15:34 +010029/*
30 * I/O Port configuration table
31 *
32 * if conf is 1, then that port pin will be configured at boot time
33 * according to the five values podr/pdir/ppar/psor/pdat for that entry
34 */
35
36const iop_conf_t iop_conf_tab[4][32] = {
37
38 /* Port A configuration */
Wolfgang Denkf1152f82007-07-06 02:50:19 +020039 { /* conf ppar psor pdir podr pdat */
40 /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
41 /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
42 /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
43 /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
44 /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
45 /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
46 /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
47 /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
48 /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
49 /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
50 /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
51 /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
52 /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
53 /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
54 /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
55 /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
56 /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
57 /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
58 /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
59 /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
60 /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
61 /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
62 /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
63 /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
64 /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
65 /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
66 /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
67 /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
68 /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
69 /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
70 /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
71 /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
Dan Malek35171dc2007-01-05 09:15:34 +010072 },
73
74 /* Port B configuration */
Wolfgang Denkf1152f82007-07-06 02:50:19 +020075 { /* conf ppar psor pdir podr pdat */
76 /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
77 /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
78 /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
79 /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
80 /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
81 /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
82 /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
83 /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
84 /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
85 /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
86 /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
87 /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
88 /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
89 /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
90 /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
91 /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
92 /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
93 /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
94 /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
95 /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
96 /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
97 /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
98 /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
99 /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
100 /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
101 /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
102 /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
103 /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
104 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
105 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
106 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
107 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
Dan Malek35171dc2007-01-05 09:15:34 +0100108 },
109
110 /* Port C */
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200111 { /* conf ppar psor pdir podr pdat */
112 /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
113 /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
114 /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
115 /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
116 /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
117 /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
118 /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
119 /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
120 /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
121 /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
122 /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
123 /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
124 /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
125 /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
126 /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
127 /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
128 /* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */
129 /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
130 /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
131 /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
132 /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
133 /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FETHMDC */
134 /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FETHMDIO */
135 /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
136 /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
137 /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
138 /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
139 /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
140 /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
141 /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
142 /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
143 /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
Dan Malek35171dc2007-01-05 09:15:34 +0100144 },
145
146 /* Port D */
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200147 { /* conf ppar psor pdir podr pdat */
148 /* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
149 /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
150 /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
151 /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RxD */
152 /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TxD */
153 /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
154 /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
155 /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
156 /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
157 /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
158 /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
159 /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
160 /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
161 /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
162 /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
163 /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
164 /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
165 /* PD14 */ { 1, 1, 1, 0, 0, 0 }, /* I2C CLK */
166 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
167 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
168 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
169 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
170 /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
171 /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
172 /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
173 /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
174 /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
175 /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
176 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
177 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
178 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
179 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
Dan Malek35171dc2007-01-05 09:15:34 +0100180 }
181};
182
183static uint64_t next_led_update;
184static uint led_bit;
185
186void
187reset_phy(void)
188{
189 volatile uint *blatch;
Wolfgang Denk2c6fb192007-04-24 14:37:49 +0200190#if 0
Dan Malek35171dc2007-01-05 09:15:34 +0100191 int i;
Wolfgang Denk2c6fb192007-04-24 14:37:49 +0200192#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193 blatch = (volatile uint *)CONFIG_SYS_LBC_CFGLATCH_BASE;
Dan Malek35171dc2007-01-05 09:15:34 +0100194
195 /* reset Giga bit Ethernet port if needed here */
196
197#if 1
198 *blatch &= ~0x000000c0;
199 udelay(100);
200#else
201 *blatch = 0;
202 asm("eieio");
203 for (i=0; i<1000; i++)
204 udelay(1000);
205#endif
206 *blatch = 0x000000c1; /* Light one led, too */
207 udelay(1000);
208
209#if 0 /* This is the port we really want to use for debugging. */
210 /* reset the CPM FEC port */
211#if (CONFIG_ETHER_INDEX == 2)
212 bcsr->bcsr2 &= ~FETH2_RST;
213 udelay(2);
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200214 bcsr->bcsr2 |= FETH2_RST;
Dan Malek35171dc2007-01-05 09:15:34 +0100215 udelay(1000);
216#elif (CONFIG_ETHER_INDEX == 3)
217 bcsr->bcsr3 &= ~FETH3_RST;
218 udelay(2);
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200219 bcsr->bcsr3 |= FETH3_RST;
Dan Malek35171dc2007-01-05 09:15:34 +0100220 udelay(1000);
221#endif
222#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
223 /* reset PHY */
Heiko Schocher48690d82010-07-20 17:45:02 +0200224 miiphy_reset("FCC1", 0x0);
Dan Malek35171dc2007-01-05 09:15:34 +0100225
226 /* change PHY address to 0x02 */
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500227 bb_miiphy_write(NULL, 0, MII_MIPSCR, 0xf028);
Dan Malek35171dc2007-01-05 09:15:34 +0100228
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500229 bb_miiphy_write(NULL, 0x02, MII_BMCR,
230 BMCR_ANENABLE | BMCR_ANRESTART);
Dan Malek35171dc2007-01-05 09:15:34 +0100231#endif /* CONFIG_MII */
232#endif
233}
234
Wolfgang Denk28415b62011-07-25 15:15:44 +0200235#ifdef CONFIG_OF_BOARD_SETUP
236void ft_board_setup(void *blob, bd_t *bd)
237{
238 ft_cpu_setup (blob, bd);
239}
240#endif /* CONFIG_OF_BOARD_SETUP */
241
Dan Malek35171dc2007-01-05 09:15:34 +0100242int
243board_early_init_f(void)
244{
245#if defined(CONFIG_PCI)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246 volatile ccsr_pcix_t *pci = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR);
Dan Malek35171dc2007-01-05 09:15:34 +0100247
Wolfgang Denkf1152f82007-07-06 02:50:19 +0200248 pci->peer &= 0xffffffdf; /* disable master abort */
Dan Malek35171dc2007-01-05 09:15:34 +0100249#endif
250
251 /* Why is the phy reset done _after_ the ethernet
Stefan Roesea47a12b2010-04-15 16:07:28 +0200252 * initialization in arch/powerpc/lib/board.c?
Dan Malek35171dc2007-01-05 09:15:34 +0100253 * Do it here so it's done before the TSECs are used.
254 */
255 reset_phy();
256
257 return 0;
258}
259
260int
261checkboard(void)
262{
263 printf ("Board: Silicon Tx GPPP SSA Board\n");
264 return (0);
265}
266
267/* Blinkin' LEDS for Robert.
268*/
269void
270show_activity(int flag)
271{
272 volatile uint *blatch;
273
274 if (next_led_update > get_ticks())
275 return;
276
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277 blatch = (volatile uint *)CONFIG_SYS_LBC_CFGLATCH_BASE;
Dan Malek35171dc2007-01-05 09:15:34 +0100278
279 led_bit >>= 1;
280 if (led_bit == 0)
281 led_bit = 0x08;
282 *blatch = (0xc0 | led_bit);
283 eieio();
284 next_led_update += (get_tbclk() / 4);
285}
286
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200287#if defined(CONFIG_SYS_DRAM_TEST)
Dan Malek35171dc2007-01-05 09:15:34 +0100288int testdram (void)
289{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200290 uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
291 uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
Dan Malek35171dc2007-01-05 09:15:34 +0100292 uint *p;
293
294 printf("SDRAM test phase 1:\n");
295 for (p = pstart; p < pend; p++)
296 *p = 0xaaaaaaaa;
297
298 for (p = pstart; p < pend; p++) {
299 if (*p != 0xaaaaaaaa) {
300 printf ("SDRAM test fails at: %08x\n", (uint) p);
301 return 1;
302 }
303 }
304
305 printf("SDRAM test phase 2:\n");
306 for (p = pstart; p < pend; p++)
307 *p = 0x55555555;
308
309 for (p = pstart; p < pend; p++) {
310 if (*p != 0x55555555) {
311 printf ("SDRAM test fails at: %08x\n", (uint) p);
312 return 1;
313 }
314 }
315
316 printf("SDRAM test passed.\n");
317 return 0;
318}
319#endif
320
321#if defined(CONFIG_PCI)
322
323/*
324 * Initialize PCI Devices, report devices found.
325 */
326
327#ifndef CONFIG_PCI_PNP
328static struct pci_config_table pci_stxgp3_config_table[] = {
329 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
330 PCI_IDSEL_NUMBER, PCI_ANY_ID,
331 pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
332 PCI_ENET0_MEMADDR,
333 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
334 } },
335 { }
336};
337#endif
338
339
Grzegorz Bernacki38ad82d2007-09-11 15:42:11 +0200340static struct pci_controller hose[] = {
Dan Malek35171dc2007-01-05 09:15:34 +0100341#ifndef CONFIG_PCI_PNP
Grzegorz Bernacki38ad82d2007-09-11 15:42:11 +0200342 { config_table: pci_stxgp3_config_table,},
Wolfgang Denkf34024d2007-09-12 00:48:57 +0200343#else
Grzegorz Bernacki38ad82d2007-09-11 15:42:11 +0200344 {},
345#endif
Wolfgang Denkf34024d2007-09-12 00:48:57 +0200346#ifdef CONFIG_MPC85XX_PCI2
347 {},
Dan Malek35171dc2007-01-05 09:15:34 +0100348#endif
349};
350
351#endif /* CONFIG_PCI */
352
353
354void
355pci_init_board(void)
356{
357#ifdef CONFIG_PCI
358 extern void pci_mpc85xx_init(struct pci_controller *hose);
359
Grzegorz Bernacki38ad82d2007-09-11 15:42:11 +0200360 pci_mpc85xx_init(hose);
Dan Malek35171dc2007-01-05 09:15:34 +0100361#endif /* CONFIG_PCI */
362}
Ben Warren8ca0b3f2008-08-31 10:45:44 -0700363
364int board_eth_init(bd_t *bis)
365{
366 cpu_eth_init(bis); /* Initialize TSECs first */
367 return pci_eth_init(bis);
368}