blob: 76fa95ca370dfdc49859bfbd04e7f69fb80940b9 [file] [log] [blame]
Wolfgang Denk46263f22013-07-28 22:12:45 +02001/*
Wolfgang Denk1b387ef2013-09-17 11:24:06 +02002 * SPDX-License-Identifier: GPL-2.0 IBM-pibs
Wolfgang Denk46263f22013-07-28 22:12:45 +02003 */
wdenkba56f622004-02-06 23:19:44 +00004/*----------------------------------------------------------------------------+
5|
6| File Name: enetemac.h
7|
8| Function: Header file for the EMAC3 macro on the 405GP.
9|
10| Author: Mark Wisner
11|
12| Change Activity-
13|
14| Date Description of Change BY
15| --------- --------------------- ---
16| 29-Apr-99 Created MKW
17|
18+----------------------------------------------------------------------------*/
19/*----------------------------------------------------------------------------+
20| 19-Nov-03 Travis Sawyer, Sandburst Corporation, tsawyer@sandburst.com
21| ported to handle 440GP and 440GX multiple EMACs
22+----------------------------------------------------------------------------*/
23
Stefan Roesed6c61aa2005-08-16 18:18:00 +020024#ifndef _PPC4XX_ENET_H_
25#define _PPC4XX_ENET_H_
wdenkba56f622004-02-06 23:19:44 +000026
wdenkba56f622004-02-06 23:19:44 +000027#include <net.h>
Stefan Roeseb36df562010-09-09 19:18:00 +020028#include "asm/ppc4xx-mal.h"
wdenkba56f622004-02-06 23:19:44 +000029
30
31/*-----------------------------------------------------------------------------+
32| General enternet defines. 802 frames are not supported.
33+-----------------------------------------------------------------------------*/
34#define ENET_ADDR_LENGTH 6
35#define ENET_ARPTYPE 0x806
36#define ARP_REQUEST 1
37#define ARP_REPLY 2
38#define ENET_IPTYPE 0x800
39#define ARP_CACHE_SIZE 5
40
41#define NUM_TX_BUFF 1
42#define NUM_RX_BUFF PKTBUFSRX
43
44struct enet_frame {
45 unsigned char dest_addr[ENET_ADDR_LENGTH];
46 unsigned char source_addr[ENET_ADDR_LENGTH];
47 unsigned short type;
48 unsigned char enet_data[1];
49};
50
51struct arp_entry {
52 unsigned long inet_address;
53 unsigned char mac_address[ENET_ADDR_LENGTH];
54 unsigned long valid;
55 unsigned long sec;
56 unsigned long nsec;
57};
58
59
60/* Statistic Areas */
61#define MAX_ERR_LOG 10
62
63typedef struct emac_stats_st{ /* Statistic Block */
64 int data_len_err;
65 int rx_frames;
66 int rx;
67 int rx_prot_err;
68 int int_err;
Stefan Roesed6c61aa2005-08-16 18:18:00 +020069 int pkts_tx;
70 int pkts_rx;
71 int pkts_handled;
wdenkba56f622004-02-06 23:19:44 +000072 short tx_err_log[MAX_ERR_LOG];
73 short rx_err_log[MAX_ERR_LOG];
74} EMAC_STATS_ST, *EMAC_STATS_PST;
75
Stefan Roesed6c61aa2005-08-16 18:18:00 +020076/* Structure containing variables used by the shared code (4xx_enet.c) */
77typedef struct emac_4xx_hw_st {
wdenkba56f622004-02-06 23:19:44 +000078 uint32_t hw_addr; /* EMAC offset */
79 uint32_t tah_addr; /* TAH offset */
80 uint32_t phy_id;
81 uint32_t phy_addr;
82 uint32_t original_fc;
83 uint32_t txcw;
84 uint32_t autoneg_failed;
85 uint32_t emac_ier;
86 volatile mal_desc_t *tx;
87 volatile mal_desc_t *rx;
Stefan Roeseff768cb2007-10-31 18:01:24 +010088 u32 tx_phys;
89 u32 rx_phys;
wdenkba56f622004-02-06 23:19:44 +000090 bd_t *bis; /* for eth_init upon mal error */
91 mal_desc_t *alloc_tx_buf;
92 mal_desc_t *alloc_rx_buf;
93 char *txbuf_ptr;
94 uint16_t devnum;
95 int get_link_status;
96 int tbi_compatibility_en;
97 int tbi_compatibility_on;
98 int fc_send_xon;
99 int report_tx_early;
100 int first_init;
101 int tx_err_index;
102 int rx_err_index;
Niklaus Gigerdbcc3572009-10-04 20:04:22 +0200103 int rx_slot; /* MAL Receive Slot */
104 int rx_i_index; /* Receive Interrupt Queue Index */
105 int rx_u_index; /* Receive User Queue Index */
106 int tx_slot; /* MAL Transmit Slot */
107 int tx_i_index; /* Transmit Interrupt Queue Index */
wdenkba56f622004-02-06 23:19:44 +0000108 int tx_u_index; /* Transmit User Queue Index */
109 int rx_ready[NUM_RX_BUFF]; /* Receive Ready Queue */
110 int tx_run[NUM_TX_BUFF]; /* Transmit Running Queue */
111 int is_receiving; /* sync with eth interrupt */
112 int print_speed; /* print speed message upon start */
113 EMAC_STATS_ST stats;
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200114} EMAC_4XX_HW_ST, *EMAC_4XX_HW_PST;
wdenkba56f622004-02-06 23:19:44 +0000115
116
Stefan Roese6f2eb3f2008-03-11 15:11:18 +0100117#if defined(CONFIG_440GX) || defined(CONFIG_460GT)
Stefan Roesee01bd212007-03-21 13:38:59 +0100118#define EMAC_NUM_DEV 4
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100119#elif (defined(CONFIG_440) || defined(CONFIG_405EP)) && \
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200120 !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
Stefan Roesee01bd212007-03-21 13:38:59 +0100121#define EMAC_NUM_DEV 2
wdenkba56f622004-02-06 23:19:44 +0000122#else
Stefan Roesee01bd212007-03-21 13:38:59 +0100123#define EMAC_NUM_DEV 1
wdenkba56f622004-02-06 23:19:44 +0000124#endif
125
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200126#ifdef CONFIG_IBM_EMAC4_V4 /* EMAC4 V4 changed bit setting */
127#define EMAC_STACR_OC_MASK (0x00008000)
128#else
129#define EMAC_STACR_OC_MASK (0x00000000)
130#endif
131
Grant Erickson1740c1b2008-07-08 08:35:00 -0700132/*
133 * XMII bridge configurations for those systems (e.g. 405EX(r)) that do
134 * not have a pin function control (PFC) register to otherwise determine
135 * the bridge configuration.
136 */
137#define EMAC_PHY_MODE_NONE 0
138#define EMAC_PHY_MODE_NONE_RGMII 1
139#define EMAC_PHY_MODE_RGMII_NONE 2
140#define EMAC_PHY_MODE_RGMII_RGMII 3
141#define EMAC_PHY_MODE_NONE_GMII 4
142#define EMAC_PHY_MODE_GMII_NONE 5
143#define EMAC_PHY_MODE_NONE_MII 6
144#define EMAC_PHY_MODE_MII_NONE 7
145
Stefan Roesedbbd1252007-10-05 17:10:59 +0200146/* ZMII Bridge Register addresses */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200147#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
Stefan Roese6f2eb3f2008-03-11 15:11:18 +0100148 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
149 defined(CONFIG_460EX) || defined(CONFIG_460GT)
Niklaus Gigerf80e61d2009-10-04 20:04:19 +0200150#define ZMII0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0D00)
Stefan Roesec157d8e2005-08-01 16:41:48 +0200151#else
Niklaus Gigerf80e61d2009-10-04 20:04:19 +0200152#define ZMII0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0780)
Stefan Roesec157d8e2005-08-01 16:41:48 +0200153#endif
Niklaus Gigerf80e61d2009-10-04 20:04:19 +0200154#define ZMII0_FER (ZMII0_BASE)
155#define ZMII0_SSR (ZMII0_BASE + 4)
156#define ZMII0_SMIISR (ZMII0_BASE + 8)
wdenkba56f622004-02-06 23:19:44 +0000157
wdenkba56f622004-02-06 23:19:44 +0000158/* ZMII FER Register Bit Definitions */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200159#define ZMII_FER_DIS (0x0)
wdenkba56f622004-02-06 23:19:44 +0000160#define ZMII_FER_MDI (0x8)
161#define ZMII_FER_SMII (0x4)
162#define ZMII_FER_RMII (0x2)
163#define ZMII_FER_MII (0x1)
164
165#define ZMII_FER_RSVD11 (0x00200000)
166#define ZMII_FER_RSVD10 (0x00100000)
167#define ZMII_FER_RSVD14_31 (0x0003FFFF)
168
169#define ZMII_FER_V(__x) (((3 - __x) * 4) + 16)
170
171
172/* ZMII Speed Selection Register Bit Definitions */
Niklaus Gigerf80e61d2009-10-04 20:04:19 +0200173#define ZMII0_SSR_SCI (0x4)
174#define ZMII0_SSR_FSS (0x2)
175#define ZMII0_SSR_SP (0x1)
176#define ZMII0_SSR_RSVD16_31 (0x0000FFFF)
wdenkba56f622004-02-06 23:19:44 +0000177
Niklaus Gigerf80e61d2009-10-04 20:04:19 +0200178#define ZMII0_SSR_V(__x) (((3 - __x) * 4) + 16)
wdenkba56f622004-02-06 23:19:44 +0000179
180
181/* ZMII SMII Status Register Bit Definitions */
Niklaus Gigerf80e61d2009-10-04 20:04:19 +0200182#define ZMII0_SMIISR_E1 (0x80)
183#define ZMII0_SMIISR_EC (0x40)
184#define ZMII0_SMIISR_EN (0x20)
185#define ZMII0_SMIISR_EJ (0x10)
186#define ZMII0_SMIISR_EL (0x08)
187#define ZMII0_SMIISR_ED (0x04)
188#define ZMII0_SMIISR_ES (0x02)
189#define ZMII0_SMIISR_EF (0x01)
wdenkba56f622004-02-06 23:19:44 +0000190
Niklaus Gigerf80e61d2009-10-04 20:04:19 +0200191#define ZMII0_SMIISR_V(__x) ((3 - __x) * 8)
wdenkba56f622004-02-06 23:19:44 +0000192
193/* RGMII Register Addresses */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200194#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define RGMII_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x1000)
Stefan Roese6f2eb3f2008-03-11 15:11:18 +0100196#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197#define RGMII_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x1500)
Stefan Roesedbbd1252007-10-05 17:10:59 +0200198#elif defined(CONFIG_405EX)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#define RGMII_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0xB00)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200200#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201#define RGMII_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0790)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200202#endif
wdenkba56f622004-02-06 23:19:44 +0000203#define RGMII_FER (RGMII_BASE + 0x00)
204#define RGMII_SSR (RGMII_BASE + 0x04)
205
Stefan Roese4c9e8552008-03-19 16:20:49 +0100206#if defined(CONFIG_460GT)
207#define RGMII1_BASE_OFFSET 0x100
208#endif
209
wdenkba56f622004-02-06 23:19:44 +0000210/* RGMII Function Enable (FER) Register Bit Definitions */
wdenkba56f622004-02-06 23:19:44 +0000211#define RGMII_FER_DIS (0x00)
212#define RGMII_FER_RTBI (0x04)
213#define RGMII_FER_RGMII (0x05)
214#define RGMII_FER_TBI (0x06)
215#define RGMII_FER_GMII (0x07)
Grant Erickson1740c1b2008-07-08 08:35:00 -0700216#define RGMII_FER_MII (RGMII_FER_GMII)
wdenkba56f622004-02-06 23:19:44 +0000217
218#define RGMII_FER_V(__x) ((__x - 2) * 4)
219
Stefan Roese6f2eb3f2008-03-11 15:11:18 +0100220#define RGMII_FER_MDIO(__x) (1 << (19 - (__x)))
221
wdenkba56f622004-02-06 23:19:44 +0000222/* RGMII Speed Selection Register Bit Definitions */
223#define RGMII_SSR_SP_10MBPS (0x00)
224#define RGMII_SSR_SP_100MBPS (0x02)
225#define RGMII_SSR_SP_1000MBPS (0x04)
226
Stefan Roesedbbd1252007-10-05 17:10:59 +0200227#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
Stefan Roese6f2eb3f2008-03-11 15:11:18 +0100228 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
Stefan Roesedbbd1252007-10-05 17:10:59 +0200229 defined(CONFIG_405EX)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200230#define RGMII_SSR_V(__x) ((__x) * 8)
231#else
wdenkba56f622004-02-06 23:19:44 +0000232#define RGMII_SSR_V(__x) ((__x -2) * 8)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200233#endif
wdenkba56f622004-02-06 23:19:44 +0000234
wdenkba56f622004-02-06 23:19:44 +0000235/*---------------------------------------------------------------------------+
236| TCP/IP Acceleration Hardware (TAH) 440GX Only
237+---------------------------------------------------------------------------*/
Stefan Roese846b0dd2005-08-08 12:42:22 +0200238#if defined(CONFIG_440GX)
Niklaus Gigerdbcc3572009-10-04 20:04:22 +0200239#define TAH_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0B50)
240#define TAH_REVID (TAH_BASE + 0x0) /* Revision ID (RO)*/
241#define TAH_MR (TAH_BASE + 0x10) /* Mode Register (R/W) */
242#define TAH_SSR0 (TAH_BASE + 0x14) /* Segment Size Reg 0 (R/W) */
243#define TAH_SSR1 (TAH_BASE + 0x18) /* Segment Size Reg 1 (R/W) */
244#define TAH_SSR2 (TAH_BASE + 0x1C) /* Segment Size Reg 2 (R/W) */
245#define TAH_SSR3 (TAH_BASE + 0x20) /* Segment Size Reg 3 (R/W) */
246#define TAH_SSR4 (TAH_BASE + 0x24) /* Segment Size Reg 4 (R/W) */
247#define TAH_SSR5 (TAH_BASE + 0x28) /* Segment Size Reg 5 (R/W) */
248#define TAH_TSR (TAH_BASE + 0x2C) /* Transmit Status Register (RO) */
wdenkba56f622004-02-06 23:19:44 +0000249
wdenkba56f622004-02-06 23:19:44 +0000250/* TAH Revision */
251#define TAH_REV_RN_M (0x000FFF00) /* Revision Number */
252#define TAH_REV_BN_M (0x000000FF) /* Branch Revision Number */
253
254#define TAH_REV_RN_V (8)
255#define TAH_REV_BN_V (0)
256
257/* TAH Mode Register */
Niklaus Gigerdbcc3572009-10-04 20:04:22 +0200258#define TAH_MR_CVR (0x80000000) /* Checksum verification on RX */
259#define TAH_MR_SR (0x40000000) /* Software reset */
260#define TAH_MR_ST (0x3F000000) /* Send Threshold */
261#define TAH_MR_TFS (0x00E00000) /* Transmit FIFO size */
262#define TAH_MR_DTFP (0x00100000) /* Disable TX FIFO parity */
263#define TAH_MR_DIG (0x00080000) /* Disable interrupt generation */
264#define TAH_MR_RSVD (0x0007FFFF) /* Reserved */
wdenkba56f622004-02-06 23:19:44 +0000265
Niklaus Gigerdbcc3572009-10-04 20:04:22 +0200266#define TAH_MR_ST_V (20)
267#define TAH_MR_TFS_V (17)
wdenkba56f622004-02-06 23:19:44 +0000268
Niklaus Gigerdbcc3572009-10-04 20:04:22 +0200269#define TAH_MR_TFS_2K (0x1) /* Transmit FIFO size 2Kbyte */
270#define TAH_MR_TFS_4K (0x2) /* Transmit FIFO size 4Kbyte */
271#define TAH_MR_TFS_6K (0x3) /* Transmit FIFO size 6Kbyte */
272#define TAH_MR_TFS_8K (0x4) /* Transmit FIFO size 8Kbyte */
273#define TAH_MR_TFS_10K (0x5) /* Transmit FIFO size 10Kbyte (max)*/
wdenkba56f622004-02-06 23:19:44 +0000274
275
276/* TAH Segment Size Registers 0:5 */
Niklaus Gigerdbcc3572009-10-04 20:04:22 +0200277#define TAH_SSR_RSVD0 (0xC0000000) /* Reserved */
278#define TAH_SSR_SS (0x3FFE0000) /* Segment size in multiples of 2 */
279#define TAH_SSR_RSVD1 (0x0001FFFF) /* Reserved */
wdenkba56f622004-02-06 23:19:44 +0000280
281/* TAH Transmit Status Register */
Niklaus Gigerdbcc3572009-10-04 20:04:22 +0200282#define TAH_TSR_TFTS (0x80000000) /* Transmit FIFO too small */
283#define TAH_TSR_UH (0x40000000) /* Unrecognized header */
284#define TAH_TSR_NIPF (0x20000000) /* Not IPv4 */
285#define TAH_TSR_IPOP (0x10000000) /* IP option present */
286#define TAH_TSR_NISF (0x08000000) /* No IEEE SNAP format */
287#define TAH_TSR_ILTS (0x04000000) /* IP length too short */
288#define TAH_TSR_IPFP (0x02000000) /* IP fragment present */
289#define TAH_TSR_UP (0x01000000) /* Unsupported protocol */
290#define TAH_TSR_TFP (0x00800000) /* TCP flags present */
291#define TAH_TSR_SUDP (0x00400000) /* Segmentation for UDP */
292#define TAH_TSR_DLM (0x00200000) /* Data length mismatch */
293#define TAH_TSR_SIEEE (0x00100000) /* Segmentation for IEEE */
294#define TAH_TSR_TFPE (0x00080000) /* Transmit FIFO parity error */
295#define TAH_TSR_SSTS (0x00040000) /* Segment size too small */
296#define TAH_TSR_RSVD (0x0003FFFF) /* Reserved */
Stefan Roese846b0dd2005-08-08 12:42:22 +0200297#endif /* CONFIG_440GX */
wdenkba56f622004-02-06 23:19:44 +0000298
299
300/* Ethernet MAC Regsiter Addresses */
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200301#if defined(CONFIG_440)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200302#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
Stefan Roese6f2eb3f2008-03-11 15:11:18 +0100303 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
304 defined(CONFIG_460EX) || defined(CONFIG_460GT)
Niklaus Gigerf80e61d2009-10-04 20:04:19 +0200305#define EMAC0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0E00)
Stefan Roesec157d8e2005-08-01 16:41:48 +0200306#else
Niklaus Gigerf80e61d2009-10-04 20:04:19 +0200307#define EMAC0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0800)
Stefan Roesec157d8e2005-08-01 16:41:48 +0200308#endif
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200309#else
Stefan Roesedbbd1252007-10-05 17:10:59 +0200310#if defined(CONFIG_405EZ) || defined(CONFIG_405EX)
Niklaus Gigerf80e61d2009-10-04 20:04:19 +0200311#define EMAC0_BASE 0xEF600900
Stefan Roesee01bd212007-03-21 13:38:59 +0100312#else
Niklaus Gigerf80e61d2009-10-04 20:04:19 +0200313#define EMAC0_BASE 0xEF600800
Stefan Roesee01bd212007-03-21 13:38:59 +0100314#endif
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200315#endif
wdenkba56f622004-02-06 23:19:44 +0000316
Niklaus Gigerf80e61d2009-10-04 20:04:19 +0200317#if defined(CONFIG_440EPX)
318#define EMAC1_BASE 0xEF600F00
319#define EMAC1_MR1 (EMAC1_BASE + 0x04)
320#endif
321
322#define EMAC0_MR0 (EMAC0_BASE)
323#define EMAC0_MR1 (EMAC0_BASE + 0x04)
324#define EMAC0_TMR0 (EMAC0_BASE + 0x08)
325#define EMAC0_TMR1 (EMAC0_BASE + 0x0c)
326#define EMAC0_RXM (EMAC0_BASE + 0x10)
327#define EMAC0_ISR (EMAC0_BASE + 0x14)
328#define EMAC0_IER (EMAC0_BASE + 0x18)
329#define EMAC0_IAH (EMAC0_BASE + 0x1c)
330#define EMAC0_IAL (EMAC0_BASE + 0x20)
331#define EMAC0_PTR (EMAC0_BASE + 0x2c)
332#define EMAC0_PAUSE_TIME_REG EMAC0_PTR
333#define EMAC0_IPGVR (EMAC0_BASE + 0x58)
334#define EMAC0_I_FRAME_GAP_REG EMAC0_IPGVR
335#define EMAC0_STACR (EMAC0_BASE + 0x5c)
336#define EMAC0_TRTR (EMAC0_BASE + 0x60)
337#define EMAC0_RWMR (EMAC0_BASE + 0x64)
338#define EMAC0_RX_HI_LO_WMARK EMAC0_RWMR
wdenkba56f622004-02-06 23:19:44 +0000339
340/* bit definitions */
341/* MODE REG 0 */
Niklaus Gigerf80e61d2009-10-04 20:04:19 +0200342#define EMAC_MR0_RXI (0x80000000)
343#define EMAC_MR0_TXI (0x40000000)
344#define EMAC_MR0_SRST (0x20000000)
345#define EMAC_MR0_TXE (0x10000000)
346#define EMAC_MR0_RXE (0x08000000)
347#define EMAC_MR0_WKE (0x04000000)
wdenkba56f622004-02-06 23:19:44 +0000348
Stefan Roese17f50f222005-08-04 17:09:16 +0200349/* on 440GX EMAC_MR1 has a different layout! */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200350#if defined(CONFIG_440GX) || \
351 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
Stefan Roesedbbd1252007-10-05 17:10:59 +0200352 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
Stefan Roese6f2eb3f2008-03-11 15:11:18 +0100353 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
Stefan Roesedbbd1252007-10-05 17:10:59 +0200354 defined(CONFIG_405EX)
wdenkba56f622004-02-06 23:19:44 +0000355/* MODE Reg 1 */
Niklaus Gigerf80e61d2009-10-04 20:04:19 +0200356#define EMAC_MR1_FDE (0x80000000)
357#define EMAC_MR1_ILE (0x40000000)
358#define EMAC_MR1_VLE (0x20000000)
359#define EMAC_MR1_EIFC (0x10000000)
360#define EMAC_MR1_APP (0x08000000)
361#define EMAC_MR1_RSVD (0x06000000)
362#define EMAC_MR1_IST (0x01000000)
363#define EMAC_MR1_MF_1000GPCS (0x00C00000)
364#define EMAC_MR1_MF_1000MBPS (0x00800000) /* 0's for 10MBPS */
365#define EMAC_MR1_MF_100MBPS (0x00400000)
366#define EMAC_MR1_RFS_MASK (0x00380000)
367#define EMAC_MR1_RFS_16K (0x00280000)
368#define EMAC_MR1_RFS_8K (0x00200000)
369#define EMAC_MR1_RFS_4K (0x00180000)
370#define EMAC_MR1_RFS_2K (0x00100000)
371#define EMAC_MR1_RFS_1K (0x00080000)
372#define EMAC_MR1_TX_FIFO_MASK (0x00070000)
373#define EMAC_MR1_TX_FIFO_16K (0x00050000)
374#define EMAC_MR1_TX_FIFO_8K (0x00040000)
375#define EMAC_MR1_TX_FIFO_4K (0x00030000)
376#define EMAC_MR1_TX_FIFO_2K (0x00020000)
377#define EMAC_MR1_TX_FIFO_1K (0x00010000)
378#define EMAC_MR1_TR_MULTI (0x00008000) /* 0'x for single packet */
379#define EMAC_MR1_MWSW (0x00007000)
380#define EMAC_MR1_JUMBO_ENABLE (0x00000800)
381#define EMAC_MR1_IPPA (0x000007c0)
382#define EMAC_MR1_IPPA_SET(id) (((id) & 0x1f) << 6)
383#define EMAC_MR1_IPPA_GET(id) (((id) >> 6) & 0x1f)
384#define EMAC_MR1_OBCI_GT100 (0x00000020)
385#define EMAC_MR1_OBCI_100 (0x00000018)
386#define EMAC_MR1_OBCI_83 (0x00000010)
387#define EMAC_MR1_OBCI_66 (0x00000008)
388#define EMAC_MR1_RSVD1 (0x00000007)
Stefan Roese846b0dd2005-08-08 12:42:22 +0200389#else /* defined(CONFIG_440GX) */
Stefan Roese17f50f222005-08-04 17:09:16 +0200390/* EMAC_MR1 is the same on 405GP, 405GPr, 405EP, 440GP, 440EP */
Niklaus Gigerf80e61d2009-10-04 20:04:19 +0200391#define EMAC_MR1_FDE 0x80000000
392#define EMAC_MR1_ILE 0x40000000
393#define EMAC_MR1_VLE 0x20000000
394#define EMAC_MR1_EIFC 0x10000000
395#define EMAC_MR1_APP 0x08000000
396#define EMAC_MR1_AEMI 0x02000000
397#define EMAC_MR1_IST 0x01000000
398#define EMAC_MR1_MF_1000MBPS 0x00800000 /* 0's for 10MBPS */
399#define EMAC_MR1_MF_100MBPS 0x00400000
400#define EMAC_MR1_RFS_MASK 0x00300000
401#define EMAC_MR1_RFS_4K 0x00300000
402#define EMAC_MR1_RFS_2K 0x00200000
403#define EMAC_MR1_RFS_1K 0x00100000
404#define EMAC_MR1_RFS_512 0x00000000
405#define EMAC_MR1_TX_FIFO_MASK 0x000c0000
406#define EMAC_MR1_TX_FIFO_2K 0x00080000
407#define EMAC_MR1_TX_FIFO_1K 0x00040000
408#define EMAC_MR1_TX_FIFO_512 0x00000000
409#define EMAC_MR1_TR0_DEPEND 0x00010000 /* 0'x for single packet */
410#define EMAC_MR1_TR0_MULTI 0x00008000
411#define EMAC_MR1_TR1_DEPEND 0x00004000
412#define EMAC_MR1_TR1_MULTI 0x00002000
Stefan Roese846b0dd2005-08-08 12:42:22 +0200413#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
Niklaus Gigerf80e61d2009-10-04 20:04:19 +0200414#define EMAC_MR1_JUMBO_ENABLE 0x00001000
Stefan Roese846b0dd2005-08-08 12:42:22 +0200415#endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
416#endif /* defined(CONFIG_440GX) */
Stefan Roese17f50f222005-08-04 17:09:16 +0200417
Niklaus Gigerf80e61d2009-10-04 20:04:19 +0200418#define EMAC_MR1_FIFO_MASK (EMAC_MR1_RFS_MASK | EMAC_MR1_TX_FIFO_MASK)
Stefan Roese76957cb2008-03-01 12:11:40 +0100419#if defined(CONFIG_405EZ)
420/* 405EZ only supports 512 bytes fifos */
Niklaus Gigerf80e61d2009-10-04 20:04:19 +0200421#define EMAC_MR1_FIFO_SIZE (EMAC_MR1_RFS_512 | EMAC_MR1_TX_FIFO_512)
Stefan Roese76957cb2008-03-01 12:11:40 +0100422#else
423/* Set receive fifo to 4k and tx fifo to 2k */
Niklaus Gigerf80e61d2009-10-04 20:04:19 +0200424#define EMAC_MR1_FIFO_SIZE (EMAC_MR1_RFS_4K | EMAC_MR1_TX_FIFO_2K)
Stefan Roese76957cb2008-03-01 12:11:40 +0100425#endif
426
wdenkba56f622004-02-06 23:19:44 +0000427/* Transmit Mode Register 0 */
Niklaus Gigerf80e61d2009-10-04 20:04:19 +0200428#define EMAC_TMR0_GNP0 (0x80000000)
429#define EMAC_TMR0_GNP1 (0x40000000)
430#define EMAC_TMR0_GNPD (0x20000000)
431#define EMAC_TMR0_FC (0x10000000)
wdenkba56f622004-02-06 23:19:44 +0000432
433/* Receive Mode Register */
434#define EMAC_RMR_SP (0x80000000)
435#define EMAC_RMR_SFCS (0x40000000)
436#define EMAC_RMR_ARRP (0x20000000)
437#define EMAC_RMR_ARP (0x10000000)
438#define EMAC_RMR_AROP (0x08000000)
439#define EMAC_RMR_ARPI (0x04000000)
440#define EMAC_RMR_PPP (0x02000000)
441#define EMAC_RMR_PME (0x01000000)
442#define EMAC_RMR_PMME (0x00800000)
443#define EMAC_RMR_IAE (0x00400000)
444#define EMAC_RMR_MIAE (0x00200000)
445#define EMAC_RMR_BAE (0x00100000)
446#define EMAC_RMR_MAE (0x00080000)
447
448/* Interrupt Status & enable Regs */
449#define EMAC_ISR_OVR (0x02000000)
450#define EMAC_ISR_PP (0x01000000)
451#define EMAC_ISR_BP (0x00800000)
452#define EMAC_ISR_RP (0x00400000)
Stefan Roesee01bd212007-03-21 13:38:59 +0100453#define EMAC_ISR_SE (0x00200000)
454#define EMAC_ISR_SYE (0x00100000)
455#define EMAC_ISR_BFCS (0x00080000)
456#define EMAC_ISR_PTLE (0x00040000)
457#define EMAC_ISR_ORE (0x00020000)
458#define EMAC_ISR_IRE (0x00010000)
459#define EMAC_ISR_DBDM (0x00000200)
460#define EMAC_ISR_DB0 (0x00000100)
461#define EMAC_ISR_SE0 (0x00000080)
462#define EMAC_ISR_TE0 (0x00000040)
463#define EMAC_ISR_DB1 (0x00000020)
464#define EMAC_ISR_SE1 (0x00000010)
465#define EMAC_ISR_TE1 (0x00000008)
466#define EMAC_ISR_MOS (0x00000002)
467#define EMAC_ISR_MOF (0x00000001)
wdenkba56f622004-02-06 23:19:44 +0000468
469/* STA CONTROL REG */
Stefan Roesee01bd212007-03-21 13:38:59 +0100470#define EMAC_STACR_OC (0x00008000)
471#define EMAC_STACR_PHYE (0x00004000)
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200472
473#ifdef CONFIG_IBM_EMAC4_V4 /* EMAC4 V4 changed bit setting */
Stefan Roesee01bd212007-03-21 13:38:59 +0100474#define EMAC_STACR_INDIRECT_MODE (0x00002000)
475#define EMAC_STACR_WRITE (0x00000800) /* $BUC */
476#define EMAC_STACR_READ (0x00001000) /* $BUC */
477#define EMAC_STACR_OP_MASK (0x00001800)
478#define EMAC_STACR_MDIO_ADDR (0x00000000)
479#define EMAC_STACR_MDIO_WRITE (0x00000800)
480#define EMAC_STACR_MDIO_READ (0x00001800)
481#define EMAC_STACR_MDIO_READ_INC (0x00001000)
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200482#else
Stefan Roesee01bd212007-03-21 13:38:59 +0100483#define EMAC_STACR_WRITE (0x00002000)
484#define EMAC_STACR_READ (0x00001000)
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200485#endif
486
wdenkba56f622004-02-06 23:19:44 +0000487#define EMAC_STACR_CLK_83MHZ (0x00000800) /* 0's for 50Mhz */
488#define EMAC_STACR_CLK_66MHZ (0x00000400)
489#define EMAC_STACR_CLK_100MHZ (0x00000C00)
490
491/* Transmit Request Threshold Register */
Stefan Roesee01bd212007-03-21 13:38:59 +0100492#define EMAC_TRTR_256 (0x18000000) /* 0's for 64 Bytes */
493#define EMAC_TRTR_192 (0x10000000)
494#define EMAC_TRTR_128 (0x01000000)
wdenkba56f622004-02-06 23:19:44 +0000495
496/* the follwing defines are for the MadMAL status and control registers. */
497/* For bits 0..5 look at the mal.h file */
498#define EMAC_TX_CTRL_GFCS (0x0200)
499#define EMAC_TX_CTRL_GP (0x0100)
500#define EMAC_TX_CTRL_ISA (0x0080)
501#define EMAC_TX_CTRL_RSA (0x0040)
502#define EMAC_TX_CTRL_IVT (0x0020)
503#define EMAC_TX_CTRL_RVT (0x0010)
504
505#define EMAC_TX_CTRL_DEFAULT (EMAC_TX_CTRL_GFCS |EMAC_TX_CTRL_GP)
506
507#define EMAC_TX_ST_BFCS (0x0200)
508#define EMAC_TX_ST_BPP (0x0100)
509#define EMAC_TX_ST_LCS (0x0080)
510#define EMAC_TX_ST_ED (0x0040)
511#define EMAC_TX_ST_EC (0x0020)
512#define EMAC_TX_ST_LC (0x0010)
513#define EMAC_TX_ST_MC (0x0008)
514#define EMAC_TX_ST_SC (0x0004)
515#define EMAC_TX_ST_UR (0x0002)
516#define EMAC_TX_ST_SQE (0x0001)
517
518#define EMAC_TX_ST_DEFAULT (0x03F3)
519
520
521/* madmal receive status / Control bits */
522
523#define EMAC_RX_ST_OE (0x0200)
524#define EMAC_RX_ST_PP (0x0100)
525#define EMAC_RX_ST_BP (0x0080)
526#define EMAC_RX_ST_RP (0x0040)
527#define EMAC_RX_ST_SE (0x0020)
528#define EMAC_RX_ST_AE (0x0010)
529#define EMAC_RX_ST_BFCS (0x0008)
530#define EMAC_RX_ST_PTL (0x0004)
531#define EMAC_RX_ST_ORE (0x0002)
532#define EMAC_RX_ST_IRE (0x0001)
533/* all the errors we care about */
534#define EMAC_RX_ERRORS (0x03FF)
535
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200536#endif /* _PPC4XX_ENET_H_ */