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Kumar Galac916d7c2011-04-13 08:37:44 -05001/*
Roy Zang111fd192012-10-08 07:44:21 +00002 * Copyright 2009-2012 Freescale Semiconductor, Inc.
Kumar Galac916d7c2011-04-13 08:37:44 -05003 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Kumar Galac916d7c2011-04-13 08:37:44 -05005 */
6
7#ifndef __FM_ETH_H__
8#define __FM_ETH_H__
9
10#include <common.h>
11#include <asm/types.h>
12#include <asm/fsl_enet.h>
13
14enum fm_port {
15 FM1_DTSEC1,
16 FM1_DTSEC2,
17 FM1_DTSEC3,
18 FM1_DTSEC4,
19 FM1_DTSEC5,
York Sun9e758752012-10-08 07:44:19 +000020 FM1_DTSEC6,
21 FM1_DTSEC9,
22 FM1_DTSEC10,
Kumar Galac916d7c2011-04-13 08:37:44 -050023 FM1_10GEC1,
York Sun9e758752012-10-08 07:44:19 +000024 FM1_10GEC2,
Kumar Galac916d7c2011-04-13 08:37:44 -050025 FM2_DTSEC1,
26 FM2_DTSEC2,
27 FM2_DTSEC3,
28 FM2_DTSEC4,
Timur Tabi99abf7d2012-08-14 06:47:21 +000029 FM2_DTSEC5,
York Sun9e758752012-10-08 07:44:19 +000030 FM2_DTSEC6,
31 FM2_DTSEC9,
32 FM2_DTSEC10,
Kumar Galac916d7c2011-04-13 08:37:44 -050033 FM2_10GEC1,
York Sun9e758752012-10-08 07:44:19 +000034 FM2_10GEC2,
Kumar Galac916d7c2011-04-13 08:37:44 -050035 NUM_FM_PORTS,
36};
37
38enum fm_eth_type {
39 FM_ETH_1G_E,
40 FM_ETH_10G_E,
41};
42
Roy Zang111fd192012-10-08 07:44:21 +000043#ifdef CONFIG_SYS_FMAN_V3
44#define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfc000)
45#define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfd000)
46#define CONFIG_SYS_FM2_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM2_ADDR + 0xfc000)
47#define CONFIG_SYS_FM2_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM2_ADDR + 0xfd000)
48#else
Kumar Galac916d7c2011-04-13 08:37:44 -050049#define CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xe1120)
50#define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xf1000)
Roy Zang111fd192012-10-08 07:44:21 +000051#endif
Kumar Galac916d7c2011-04-13 08:37:44 -050052
53#define DEFAULT_FM_MDIO_NAME "FSL_MDIO0"
54#define DEFAULT_FM_TGEC_MDIO_NAME "FM_TGEC_MDIO"
55
56/* Fman ethernet info struct */
57#define FM_ETH_INFO_INITIALIZER(idx, pregs) \
58 .fm = idx, \
59 .phy_regs = (void *)pregs, \
60 .enet_if = PHY_INTERFACE_MODE_NONE, \
61
Roy Zang111fd192012-10-08 07:44:21 +000062#ifdef CONFIG_SYS_FMAN_V3
63#define FM_DTSEC_INFO_INITIALIZER(idx, n) \
64{ \
65 FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_DTSEC_MDIO_ADDR) \
66 .index = idx, \
67 .num = n - 1, \
68 .type = FM_ETH_1G_E, \
69 .port = FM##idx##_DTSEC##n, \
70 .rx_port_id = RX_PORT_1G_BASE + n - 1, \
71 .tx_port_id = TX_PORT_1G_BASE + n - 1, \
72 .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
73 offsetof(struct ccsr_fman, memac[n-1]),\
74}
75
76#define FM_TGEC_INFO_INITIALIZER(idx, n) \
77{ \
Shaohui Xie944b6cc2013-03-25 07:33:17 +000078 FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM2_TGEC_MDIO_ADDR) \
Roy Zang111fd192012-10-08 07:44:21 +000079 .index = idx, \
80 .num = n - 1, \
81 .type = FM_ETH_10G_E, \
82 .port = FM##idx##_10GEC##n, \
83 .rx_port_id = RX_PORT_10G_BASE + n - 1, \
84 .tx_port_id = TX_PORT_10G_BASE + n - 1, \
85 .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
Shaohui Xie944b6cc2013-03-25 07:33:17 +000086 offsetof(struct ccsr_fman, memac[n-1+8]),\
Roy Zang111fd192012-10-08 07:44:21 +000087}
88#else
Kumar Galac916d7c2011-04-13 08:37:44 -050089#define FM_DTSEC_INFO_INITIALIZER(idx, n) \
90{ \
91 FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR) \
92 .index = idx, \
93 .num = n - 1, \
94 .type = FM_ETH_1G_E, \
95 .port = FM##idx##_DTSEC##n, \
96 .rx_port_id = RX_PORT_1G_BASE + n - 1, \
97 .tx_port_id = TX_PORT_1G_BASE + n - 1, \
98 .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
99 offsetof(struct ccsr_fman, mac_1g[n-1]),\
100}
101
102#define FM_TGEC_INFO_INITIALIZER(idx, n) \
103{ \
104 FM_ETH_INFO_INITIALIZER(idx, CONFIG_SYS_FM1_TGEC_MDIO_ADDR) \
105 .index = idx, \
106 .num = n - 1, \
107 .type = FM_ETH_10G_E, \
108 .port = FM##idx##_10GEC##n, \
109 .rx_port_id = RX_PORT_10G_BASE + n - 1, \
110 .tx_port_id = TX_PORT_10G_BASE + n - 1, \
111 .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \
112 offsetof(struct ccsr_fman, mac_10g[n-1]),\
113}
Roy Zang111fd192012-10-08 07:44:21 +0000114#endif
Kumar Galac916d7c2011-04-13 08:37:44 -0500115struct fm_eth_info {
116 u8 enabled;
117 u8 fm;
118 u8 num;
119 u8 phy_addr;
120 int index;
121 u16 rx_port_id;
122 u16 tx_port_id;
123 enum fm_port port;
124 enum fm_eth_type type;
125 void *phy_regs;
126 phy_interface_t enet_if;
127 u32 compat_offset;
128 struct mii_dev *bus;
129};
130
131struct tgec_mdio_info {
132 struct tgec_mdio_controller *regs;
133 char *name;
134};
135
Roy Zang111fd192012-10-08 07:44:21 +0000136struct memac_mdio_info {
137 struct memac_mdio_controller *regs;
138 char *name;
139};
140
Kumar Galac916d7c2011-04-13 08:37:44 -0500141int fm_tgec_mdio_init(bd_t *bis, struct tgec_mdio_info *info);
Roy Zang111fd192012-10-08 07:44:21 +0000142int fm_memac_mdio_init(bd_t *bis, struct memac_mdio_info *info);
143
Kumar Galac916d7c2011-04-13 08:37:44 -0500144int fm_standard_init(bd_t *bis);
145void fman_enet_init(void);
146void fdt_fixup_fman_ethernet(void *fdt);
147phy_interface_t fm_info_get_enet_if(enum fm_port port);
148void fm_info_set_phy_address(enum fm_port port, int address);
Timur Tabiae2291f2012-08-14 06:47:22 +0000149int fm_info_get_phy_address(enum fm_port port);
Kumar Galac916d7c2011-04-13 08:37:44 -0500150void fm_info_set_mdio(enum fm_port port, struct mii_dev *bus);
Kumar Gala69a85242011-09-14 12:01:35 -0500151void fm_disable_port(enum fm_port port);
Valentin Longchampf51d3b72013-10-18 11:47:21 +0200152void fm_enable_port(enum fm_port port);
Zhao Qiangffee1dd2013-09-04 10:11:27 +0800153void set_sgmii_phy(struct mii_dev *bus, enum fm_port base_port,
154 unsigned int port_num, int phy_base_addr);
155int is_qsgmii_riser_card(struct mii_dev *bus, int phy_base_addr,
156 unsigned int port_num, unsigned regnum);
Kumar Galac916d7c2011-04-13 08:37:44 -0500157
158#endif