Gitiles
Code Review Sign In
gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / db81c0d27654ed18b12ba94f05f9578294cb62ed / . / include / configs / pcm030.h
blob: 8acf3c7469baee28dc95764caa7fe93d377d75ac [file] [log] [blame]
Jon Smirlc9969942009-06-14 18:21:28 -0400[diff] [blame]1/*
2 * (C) Copyright 2003-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2006
6 * Eric Schumann, Phytec Messatechnik GmbH
7 *
8 * (C) Copyright 2009
9 * Jon Smirl <jonsmirl@gmail.com>
10 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
30#ifndef __CONFIG_H
31#define __CONFIG_H
32
33#define CONFIG_BOARDINFO "phyCORE-MPC5200B-tiny"
34
35/*-----------------------------------------------------------------------------
36High Level Configuration Options
37(easy to change)
38-----------------------------------------------------------------------------*/
39#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
40#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
41#define CONFIG_MPC5200_DDR 1 /* (with DDR-SDRAM) */
42#define CONFIG_PHYCORE_MPC5200B_TINY 1 /* phyCORE-MPC5200B -> */
43 /* FEC configuration and IDE */
44#define CONFIG_SYS_MPC5XXX_CLKIN 33333333 /* ... running at 33.333333MHz */
45#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
46#define BOOTFLAG_WARM 0x02 /* Software reboot */
47
48/*-----------------------------------------------------------------------------
49Serial console configuration
50-----------------------------------------------------------------------------*/
51#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 -> */
52 /*define gps port conf. */
53 /* register later on to */
54 /*enable UART function! */
55#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
56#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
57
58/*
59 * Command line configuration.
60 */
61#include <config_cmd_default.h>
62
63#define CONFIG_CMD_DATE
64#define CONFIG_CMD_DHCP
65#define CONFIG_CMD_EEPROM
66#define CONFIG_CMD_I2C
67#define CONFIG_CMD_JFFS2
68#define CONFIG_CMD_MII
69#define CONFIG_CMD_NFS
70#define CONFIG_CMD_PCI
71
72#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
73
74#if (TEXT_BASE == 0xFF000000) /* Boot low */
75#define CONFIG_SYS_LOWBOOT 1
76#endif
77/* RAMBOOT will be defined automatically in memory section */
78
79#define CONFIG_JFFS2_CMDLINE
80#define MTDIDS_DEFAULT "nor0=physmap-flash.0"
81#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:256k(ubootl)," \
82 "1792k(kernel),13312k(jffs2),256k(uboot)ro,256k(oftree),-(space)"
83
84/*-----------------------------------------------------------------------------
85Autobooting
86-----------------------------------------------------------------------------*/
87#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
88#define CONFIG_ZERO_BOOTDELAY_CHECK /* allow stopping of boot process */
89 /* even with bootdelay=0 */
90#undef CONFIG_BOOTARGS
91
92
93#define CONFIG_PREBOOT "echo;" \
94 "echo Type \"run bootcmd_net\" to load Kernel over TFTP and to "\
95 "mount root filesystem over NFS;" \
96 "echo"
97
98#define CONFIG_EXTRA_ENV_SETTINGS \
99 "netdev=eth0\0" \
100 "uimage=uImage-pcm030\0" \
101 "oftree=oftree-pcm030.dtb\0" \
102 "jffs2=root-pcm030.jffs2\0" \
103 "uboot=u-boot-pcm030.bin\0" \
104 "bargs_base=setenv bootargs console=ttyPSC0,$(baudrate)" \
105 " $(mtdparts) rw\0" \
106 "bargs_flash=setenv bootargs $(bootargs) root=/dev/mtdblock2" \
107 " rootfstype=jffs2\0" \
108 "bargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs" \
109 " ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)::" \
110 "$(netdev):off nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
111 "bcmd_net=run bargs_base bargs_nfs; tftpboot 0x500000 $(uimage);" \
112 " tftp 0x400000 $(oftree); bootm 0x500000 - 0x400000\0" \
113 "bcmd_flash=run bargs_base bargs_flash; bootm 0xff040000 - " \
114 "0xfff40000\0" \
115 " cp.b 0x400000 0xff040000 $(filesize)\0" \
116 "prg_jffs2=tftp 0x400000 $(jffs2); erase 0xff200000 0xffefffff; " \
117 "cp.b 0x400000 0xff200000 $(filesize)\0" \
118 "prg_oftree=tftp 0x400000 $(oftree); erase 0xfff40000 0xfff5ffff;" \
119 " cp.b 0x400000 0xfff40000 $(filesize)\0" \
120 "update=tftpboot 0x400000 $(uboot);erase 0xFFF00000 0xfff3ffff;" \
121 " cp.b 0x400000 0xFFF00000 $(filesize)\0" \
122 "unlock=yes\0" \
123 ""
124
125#define CONFIG_BOOTCOMMAND "run bcmd_flash"
126
127/*--------------------------------------------------------------------------
128IPB Bus clocking configuration.
129 ---------------------------------------------------------------------------*/
130#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
131
132/*-------------------------------------------------------------------------
133 * PCI Mapping:
134 * 0x40000000 - 0x4fffffff - PCI Memory
135 * 0x50000000 - 0x50ffffff - PCI IO Space
136 * -----------------------------------------------------------------------*/
137#define CONFIG_PCI 1
138#define CONFIG_PCI_PNP 1
139#define CONFIG_PCI_SCAN_SHOW 1
140#define CONFIG_PCI_MEM_BUS 0x40000000
141#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
142#define CONFIG_PCI_MEM_SIZE 0x10000000
143#define CONFIG_PCI_IO_BUS 0x50000000
144#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
145#define CONFIG_PCI_IO_SIZE 0x01000000
146#define CONFIG_SYS_XLB_PIPELINING 1
147
148/*---------------------------------------------------------------------------
149 I2C configuration
150---------------------------------------------------------------------------*/
151#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
152#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
153#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
154#define CONFIG_SYS_I2C_SLAVE 0x7F
155
156/*---------------------------------------------------------------------------
157 EEPROM CAT24WC32 configuration
158---------------------------------------------------------------------------*/
159#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* 1010100x */
160#define CONFIG_SYS_I2C_FACT_ADDR 0x52 /* EEPROM CAT24WC32 */
161#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
162#define CONFIG_SYS_EEPROM_SIZE 2048
163#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
164#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 15
165
166/*---------------------------------------------------------------------------
167RTC configuration
168---------------------------------------------------------------------------*/
169#define RTC
170#define CONFIG_RTC_PCF8563 1
171#define CONFIG_SYS_I2C_RTC_ADDR 0x51
172
173/*---------------------------------------------------------------------------
174 Flash configuration
175---------------------------------------------------------------------------*/
176
177#define CONFIG_SYS_FLASH_BASE 0xff000000
178#define CONFIG_SYS_FLASH_SIZE 0x01000000
179#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
180
181#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
182#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
183#define CONFIG_SYS_FLASH_EMPTY_INFO
184#define CONFIG_SYS_MAX_FLASH_SECT 260 /* max num of sects on one chip */
185#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
186 /* (= chip selects) */
187#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
188
189/*
190 * Use also hardware protection. This seems required, as the BDI uses
191 * hardware protection. Without this, U-Boot can't work with this sectors,
192 * as its protection is software only by default
193 */
194#define CONFIG_SYS_FLASH_PROTECTION 1
195
196/*---------------------------------------------------------------------------
197 Environment settings
198---------------------------------------------------------------------------*/
199
200/* pcm030 ships with environment is EEPROM by default */
201#define CONFIG_ENV_IS_IN_EEPROM 1
202#define CONFIG_ENV_OFFSET 0x00 /* environment starts at the */
203 /*beginning of the EEPROM */
204#define CONFIG_ENV_SIZE CONFIG_SYS_EEPROM_SIZE
205
206#define CONFIG_ENV_OVERWRITE 1
207
208/*-----------------------------------------------------------------------------
209 Memory map
210-----------------------------------------------------------------------------*/
211#define CONFIG_SYS_MBAR 0xF0000000 /* MBAR has to be switched by other */
212 /* bootloader or debugger config */
213#define CONFIG_SYS_SDRAM_BASE 0x00000000
214#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
215/* Use SRAM until RAM will be available */
216#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
217#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used */
218 /* area in DPRAM */
219#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes */
220 /* reserved for initial data */
221#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
222 CONFIG_SYS_GBL_DATA_SIZE)
223#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
224
225#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
226#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
227# define CONFIG_SYS_RAMBOOT 1
228#endif
229
230#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
231#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
232#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
233
234/*-----------------------------------------------------------------------------
235 Ethernet configuration
236-----------------------------------------------------------------------------*/
237#define CONFIG_MPC5xxx_FEC 1
238#define CONFIG_MPC5xxx_FEC_MII100
239#define CONFIG_PHY_ADDR 0x01
240
241/*---------------------------------------------------------------------------
242 GPIO configuration
243 ---------------------------------------------------------------------------*/
244
245/* GPIO port configuration
246 *
247 * Pin mapping:
248 *
249 * [29:31] = 01x
250 * PSC1_0 -> AC97 SDATA out
251 * PSC1_1 -> AC97 SDTA in
252 * PSC1_2 -> AC97 SYNC out
253 * PSC1_3 -> AC97 bitclock out
254 * PSC1_4 -> AC97 reset out
255 *
256 * [25:27] = 001
257 * PSC2_0 -> CAN 1 Tx out
258 * PSC2_1 -> CAN 1 Rx in
259 * PSC2_2 -> CAN 2 Tx out
260 * PSC2_3 -> CAN 2 Rx in
261 * PSC2_4 -> GPIO (claimed for ATA reset, active low)
262 *
263 *
264 * [20:23] = 1100
265 * PSC3_0 -> UART Tx out
266 * PSC3_1 -> UART Rx in
267 * PSC3_2 -> UART RTS (in/out FIXME)
268 * PSC3_3 -> UART CTS (in/out FIXME)
269 * PSC3_4 -> LocalPlus Bus CS6 \
270 * PSC3_5 -> LocalPlus Bus CS7 / --> see [4] and [5]
271 * PSC3_6 -> dedicated SPI MOSI out (master case)
272 * PSC3_7 -> dedicated SPI MISO in (master case)
273 * PSC3_8 -> dedicated SPI SS out (master case)
274 * PSC3_9 -> dedicated SPI CLK out (master case)
275 *
276 * [18:19] = 01
277 * USB_0 -> USB OE out
278 * USB_1 -> USB Tx- out
279 * USB_2 -> USB Tx+ out
280 * USB_3 -> USB RxD (in/out FIXME)
281 * USB_4 -> USB Rx+ in
282 * USB_5 -> USB Rx- in
283 * USB_6 -> USB PortPower out
284 * USB_7 -> USB speed out
285 * USB_8 -> USB suspend (in/out FIXME)
286 * USB_9 -> USB overcurrent in
287 *
288 * [17] = 0
289 * USB differential mode
290 *
291 * [16] = 0
292 * PCI enabled
293 *
294 * [12:15] = 0101
295 * ETH_0 -> ETH Txen
296 * ETH_1 -> ETH TxD0
297 * ETH_2 -> ETH TxD1
298 * ETH_3 -> ETH TxD2
299 * ETH_4 -> ETH TxD3
300 * ETH_5 -> ETH Txerr
301 * ETH_6 -> ETH MDC
302 * ETH_7 -> ETH MDIO
303 * ETH_8 -> ETH RxDv
304 * ETH_9 -> ETH RxCLK
305 * ETH_10 -> ETH Collision
306 * ETH_11 -> ETH TxD
307 * ETH_12 -> ETH RxD0
308 * ETH_13 -> ETH RxD1
309 * ETH_14 -> ETH RxD2
310 * ETH_15 -> ETH RxD3
311 * ETH_16 -> ETH Rxerr
312 * ETH_17 -> ETH CRS
313 *
314 * [9:11] = 101
315 * PSC6_0 -> UART RxD in
316 * PSC6_1 -> UART CTS (in/out FIXME)
317 * PSC6_2 -> UART TxD out
318 * PSC6_3 -> UART RTS (in/out FIXME)
319 *
320 * [2:3/6:7] = 00/11
321 * TMR_0 -> ATA_CS0 out
322 * TMR_1 -> ATA_CS1 out
323 * TMR_2 -> GPIO
324 * TMR_3 -> GPIO
325 * TMR_4 -> GPIO
326 * TMR_5 -> GPIO
327 * TMR_6 -> GPIO
328 * TMR_7 -> GPIO
329 * I2C_0 -> I2C 1 Clock out
330 * I2C_1 -> I2C 1 IO in/out
331 * I2C_2 -> I2C 2 Clock out
332 * I2C_3 -> I2C 2 IO in/out
333 *
334 * [4] = 1
335 * PSC3_5 is used as CS7
336 *
337 * [5] = 1
338 * PSC3_4 is used as CS6
339 *
340 * [1] = 0
341 * gpio_wkup_7 is GPIO
342 *
343 * [0] = 0
344 * gpio_wkup_6 is GPIO
345 *
346 */
347#define CONFIG_SYS_GPS_PORT_CONFIG 0x0f551c12
348
349/*-----------------------------------------------------------------------------
350 Miscellaneous configurable options
351-------------------------------------------------------------------------------*/
352#define CONFIG_SYS_LONGHELP /* undef to save memory */
353#define CONFIG_SYS_PROMPT "uboot> " /* Monitor Command Prompt */
354
355#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
356
357#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
358#if defined(CONFIG_CMD_KGDB)
359#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
360#endif
361
362#if defined(CONFIG_CMD_KGDB)
363#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
364#else
365#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
366#endif
367#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
368 /* Print Buffer Size */
369#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
370#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
371
372#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
373#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
374
375#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
376#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
377
378#define CONFIG_DISPLAY_BOARDINFO 1
379
380/*-----------------------------------------------------------------------------
381 Various low-level settings
382-----------------------------------------------------------------------------*/
383#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
384#define CONFIG_SYS_HID0_FINAL HID0_ICE
385
386/* no burst access on the LPB */
387#define CONFIG_SYS_CS_BURST 0x00000000
388/* one deadcycle for the 33MHz statemachine */
389#define CONFIG_SYS_CS_DEADCYCLE 0x33333331
390/* one additional waitstate for the 33MHz statemachine */
391#define CONFIG_SYS_BOOTCS_CFG 0x0001dd00
392#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
393#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
394
395#define CONFIG_SYS_RESET_ADDRESS 0xff000000
396
397/*-----------------------------------------------------------------------
398 * USB stuff
399 *-----------------------------------------------------------------------
400 */
401#define CONFIG_USB_CLOCK 0x0001BBBB
402#define CONFIG_USB_CONFIG 0x00001000
403
404/*---------------------------------------------------------------------------
405 IDE/ATA stuff Supports IDE harddisk
406----------------------------------------------------------------------------*/
407
408#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
409#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
410#undef CONFIG_IDE_LED /* LED for ide not supported */
411#define CONFIG_SYS_ATA_CS_ON_TIMER01
412#define CONFIG_IDE_RESET 1 /* reset for ide supported */
413#define CONFIG_IDE_PREINIT
414#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
415#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
416#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
417#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
418/* Offset for data I/O */
419#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
420/* Offset for normal register accesses */
421#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
422/* Offset for alternate registers */
423#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
424/* Interval between registers */
425#define CONFIG_SYS_ATA_STRIDE 4
426#define CONFIG_ATAPI 1
427
428/* we enable IDE and FAT support, so we also need partition support */
429#define CONFIG_DOS_PARTITION 1
430
431/* USB */
432#define CONFIG_USB_OHCI
433#define CONFIG_USB_STORAGE
434
435/* pass open firmware flat tree */
436#define CONFIG_OF_LIBFDT 1
437#define CONFIG_OF_BOARD_SETUP 1
438
439#define OF_CPU "PowerPC,5200@0"
440#define OF_TBCLK CONFIG_SYS_MPC5XXX_CLKIN
441#define OF_SOC "soc5200@f0000000"
442#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2400"
443
444#endif /* __CONFIG_H */