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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Jens Scharsigea8fbba2010-02-03 22:46:16 +01002/*
Bo Shen39b787e2013-08-13 14:38:32 +08003 * Copyright (C) 2013 Bo Shen <voice.shen@atmel.com>
Jens Scharsigea8fbba2010-02-03 22:46:16 +01004 *
5 * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
6 *
7 * Copyright (C) 2005 HP Labs
Jens Scharsigea8fbba2010-02-03 22:46:16 +01008 */
9
10#include <config.h>
11#include <common.h>
Wenyou Yangf2f3c152017-03-23 12:46:21 +080012#include <clk.h>
Simon Glass918354b2014-10-29 13:08:57 -060013#include <dm.h>
Reinhard Meyer86592f62010-11-07 13:26:14 +010014#include <asm/io.h>
Alexey Brodkin1ace4022014-02-26 17:47:58 +040015#include <linux/sizes.h>
Simon Glass918354b2014-10-29 13:08:57 -060016#include <asm/gpio.h>
Jens Scharsigea8fbba2010-02-03 22:46:16 +010017#include <asm/arch/hardware.h>
Jens Scharsigea8fbba2010-02-03 22:46:16 +010018#include <asm/arch/at91_pio.h>
Simon Glass918354b2014-10-29 13:08:57 -060019
20#define GPIO_PER_BANK 32
Jens Scharsigea8fbba2010-02-03 22:46:16 +010021
Bo Shen4bc9b7a2013-08-22 15:24:40 +080022static struct at91_port *at91_pio_get_port(unsigned port)
23{
24 switch (port) {
25 case AT91_PIO_PORTA:
26 return (struct at91_port *)ATMEL_BASE_PIOA;
27 case AT91_PIO_PORTB:
28 return (struct at91_port *)ATMEL_BASE_PIOB;
29 case AT91_PIO_PORTC:
30 return (struct at91_port *)ATMEL_BASE_PIOC;
31#if (ATMEL_PIO_PORTS > 3)
32 case AT91_PIO_PORTD:
33 return (struct at91_port *)ATMEL_BASE_PIOD;
34#if (ATMEL_PIO_PORTS > 4)
35 case AT91_PIO_PORTE:
36 return (struct at91_port *)ATMEL_BASE_PIOE;
37#endif
38#endif
39 default:
Wu, Josh7d82d892014-05-07 16:50:45 +080040 printf("Error: at91_gpio: Fail to get PIO base!\n");
Bo Shen4bc9b7a2013-08-22 15:24:40 +080041 return NULL;
42 }
43}
44
Simon Glass918354b2014-10-29 13:08:57 -060045static void at91_set_port_pullup(struct at91_port *at91_port, unsigned offset,
46 int use_pullup)
47{
48 u32 mask;
49
50 mask = 1 << offset;
51 if (use_pullup)
52 writel(mask, &at91_port->puer);
53 else
54 writel(mask, &at91_port->pudr);
55 writel(mask, &at91_port->per);
56}
57
Jens Scharsigea8fbba2010-02-03 22:46:16 +010058int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup)
59{
Bo Shen4bc9b7a2013-08-22 15:24:40 +080060 struct at91_port *at91_port = at91_pio_get_port(port);
Jens Scharsigea8fbba2010-02-03 22:46:16 +010061
Simon Glass918354b2014-10-29 13:08:57 -060062 if (at91_port && (pin < GPIO_PER_BANK))
63 at91_set_port_pullup(at91_port, pin, use_pullup);
Bo Shen4bc9b7a2013-08-22 15:24:40 +080064
Jens Scharsigea8fbba2010-02-03 22:46:16 +010065 return 0;
66}
67
68/*
69 * mux the pin to the "GPIO" peripheral role.
70 */
71int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup)
72{
Bo Shen4bc9b7a2013-08-22 15:24:40 +080073 struct at91_port *at91_port = at91_pio_get_port(port);
74 u32 mask;
Jens Scharsigea8fbba2010-02-03 22:46:16 +010075
Simon Glass918354b2014-10-29 13:08:57 -060076 if (at91_port && (pin < GPIO_PER_BANK)) {
Jens Scharsigea8fbba2010-02-03 22:46:16 +010077 mask = 1 << pin;
Bo Shen4bc9b7a2013-08-22 15:24:40 +080078 writel(mask, &at91_port->idr);
Jens Scharsigea8fbba2010-02-03 22:46:16 +010079 at91_set_pio_pullup(port, pin, use_pullup);
Bo Shen4bc9b7a2013-08-22 15:24:40 +080080 writel(mask, &at91_port->per);
Jens Scharsigea8fbba2010-02-03 22:46:16 +010081 }
Bo Shen4bc9b7a2013-08-22 15:24:40 +080082
Jens Scharsigea8fbba2010-02-03 22:46:16 +010083 return 0;
84}
85
86/*
87 * mux the pin to the "A" internal peripheral role.
88 */
89int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup)
90{
Bo Shen4bc9b7a2013-08-22 15:24:40 +080091 struct at91_port *at91_port = at91_pio_get_port(port);
92 u32 mask;
Jens Scharsigea8fbba2010-02-03 22:46:16 +010093
Simon Glass918354b2014-10-29 13:08:57 -060094 if (at91_port && (pin < GPIO_PER_BANK)) {
Jens Scharsigea8fbba2010-02-03 22:46:16 +010095 mask = 1 << pin;
Bo Shen4bc9b7a2013-08-22 15:24:40 +080096 writel(mask, &at91_port->idr);
Jens Scharsigea8fbba2010-02-03 22:46:16 +010097 at91_set_pio_pullup(port, pin, use_pullup);
Wenyou Yang2dc63f72017-03-23 12:44:36 +080098 writel(mask, &at91_port->mux.pio2.asr);
Bo Shen4bc9b7a2013-08-22 15:24:40 +080099 writel(mask, &at91_port->pdr);
Jens Scharsigea8fbba2010-02-03 22:46:16 +0100100 }
Bo Shen4bc9b7a2013-08-22 15:24:40 +0800101
Jens Scharsigea8fbba2010-02-03 22:46:16 +0100102 return 0;
103}
104
105/*
106 * mux the pin to the "B" internal peripheral role.
107 */
108int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup)
109{
Bo Shen4bc9b7a2013-08-22 15:24:40 +0800110 struct at91_port *at91_port = at91_pio_get_port(port);
111 u32 mask;
Jens Scharsigea8fbba2010-02-03 22:46:16 +0100112
Simon Glass918354b2014-10-29 13:08:57 -0600113 if (at91_port && (pin < GPIO_PER_BANK)) {
Jens Scharsigea8fbba2010-02-03 22:46:16 +0100114 mask = 1 << pin;
Bo Shen4bc9b7a2013-08-22 15:24:40 +0800115 writel(mask, &at91_port->idr);
Jens Scharsigea8fbba2010-02-03 22:46:16 +0100116 at91_set_pio_pullup(port, pin, use_pullup);
Wenyou Yang2dc63f72017-03-23 12:44:36 +0800117 writel(mask, &at91_port->mux.pio2.bsr);
Bo Shen4bc9b7a2013-08-22 15:24:40 +0800118 writel(mask, &at91_port->pdr);
Jens Scharsigea8fbba2010-02-03 22:46:16 +0100119 }
Bo Shen4bc9b7a2013-08-22 15:24:40 +0800120
Jens Scharsigea8fbba2010-02-03 22:46:16 +0100121 return 0;
122}
123
Bo Shen2b3b1c62012-05-20 15:50:00 +0000124/*
Wenyou Yang2dc63f72017-03-23 12:44:36 +0800125 * mux the pin to the "A" internal peripheral role.
Bo Shen2b3b1c62012-05-20 15:50:00 +0000126 */
Wenyou Yang2dc63f72017-03-23 12:44:36 +0800127int at91_pio3_set_a_periph(unsigned port, unsigned pin, int use_pullup)
Bo Shen2b3b1c62012-05-20 15:50:00 +0000128{
Bo Shen4bc9b7a2013-08-22 15:24:40 +0800129 struct at91_port *at91_port = at91_pio_get_port(port);
130 u32 mask;
Bo Shen2b3b1c62012-05-20 15:50:00 +0000131
Simon Glass918354b2014-10-29 13:08:57 -0600132 if (at91_port && (pin < GPIO_PER_BANK)) {
Bo Shen2b3b1c62012-05-20 15:50:00 +0000133 mask = 1 << pin;
Bo Shen4bc9b7a2013-08-22 15:24:40 +0800134 writel(mask, &at91_port->idr);
Bo Shen2b3b1c62012-05-20 15:50:00 +0000135 at91_set_pio_pullup(port, pin, use_pullup);
Wenyou Yang2dc63f72017-03-23 12:44:36 +0800136 writel(readl(&at91_port->mux.pio3.abcdsr1) & ~mask,
137 &at91_port->mux.pio3.abcdsr1);
138 writel(readl(&at91_port->mux.pio3.abcdsr2) & ~mask,
139 &at91_port->mux.pio3.abcdsr2);
140
141 writel(mask, &at91_port->pdr);
142 }
143
144 return 0;
145}
146
147/*
148 * mux the pin to the "B" internal peripheral role.
149 */
150int at91_pio3_set_b_periph(unsigned port, unsigned pin, int use_pullup)
151{
152 struct at91_port *at91_port = at91_pio_get_port(port);
153 u32 mask;
154
155 if (at91_port && (pin < GPIO_PER_BANK)) {
156 mask = 1 << pin;
157 writel(mask, &at91_port->idr);
158 at91_set_pio_pullup(port, pin, use_pullup);
159 writel(readl(&at91_port->mux.pio3.abcdsr1) | mask,
160 &at91_port->mux.pio3.abcdsr1);
161 writel(readl(&at91_port->mux.pio3.abcdsr2) & ~mask,
162 &at91_port->mux.pio3.abcdsr2);
163
164 writel(mask, &at91_port->pdr);
165 }
166
167 return 0;
168}
169/*
170 * mux the pin to the "C" internal peripheral role.
171 */
172int at91_pio3_set_c_periph(unsigned port, unsigned pin, int use_pullup)
173{
174 struct at91_port *at91_port = at91_pio_get_port(port);
175 u32 mask;
176
177 if (at91_port && (pin < GPIO_PER_BANK)) {
178 mask = 1 << pin;
179 writel(mask, &at91_port->idr);
180 at91_set_pio_pullup(port, pin, use_pullup);
181 writel(readl(&at91_port->mux.pio3.abcdsr1) & ~mask,
182 &at91_port->mux.pio3.abcdsr1);
183 writel(readl(&at91_port->mux.pio3.abcdsr2) | mask,
184 &at91_port->mux.pio3.abcdsr2);
Bo Shen4bc9b7a2013-08-22 15:24:40 +0800185 writel(mask, &at91_port->pdr);
Bo Shen2b3b1c62012-05-20 15:50:00 +0000186 }
Bo Shen4bc9b7a2013-08-22 15:24:40 +0800187
Bo Shen2b3b1c62012-05-20 15:50:00 +0000188 return 0;
189}
190
191/*
192 * mux the pin to the "D" internal peripheral role.
193 */
Wenyou Yang2dc63f72017-03-23 12:44:36 +0800194int at91_pio3_set_d_periph(unsigned port, unsigned pin, int use_pullup)
Bo Shen2b3b1c62012-05-20 15:50:00 +0000195{
Bo Shen4bc9b7a2013-08-22 15:24:40 +0800196 struct at91_port *at91_port = at91_pio_get_port(port);
197 u32 mask;
Bo Shen2b3b1c62012-05-20 15:50:00 +0000198
Simon Glass918354b2014-10-29 13:08:57 -0600199 if (at91_port && (pin < GPIO_PER_BANK)) {
Bo Shen2b3b1c62012-05-20 15:50:00 +0000200 mask = 1 << pin;
Bo Shen4bc9b7a2013-08-22 15:24:40 +0800201 writel(mask, &at91_port->idr);
Bo Shen2b3b1c62012-05-20 15:50:00 +0000202 at91_set_pio_pullup(port, pin, use_pullup);
Wenyou Yang2dc63f72017-03-23 12:44:36 +0800203 writel(readl(&at91_port->mux.pio3.abcdsr1) | mask,
204 &at91_port->mux.pio3.abcdsr1);
205 writel(readl(&at91_port->mux.pio3.abcdsr2) | mask,
206 &at91_port->mux.pio3.abcdsr2);
Bo Shen4bc9b7a2013-08-22 15:24:40 +0800207 writel(mask, &at91_port->pdr);
Bo Shen2b3b1c62012-05-20 15:50:00 +0000208 }
Bo Shen4bc9b7a2013-08-22 15:24:40 +0800209
Bo Shen2b3b1c62012-05-20 15:50:00 +0000210 return 0;
211}
Bo Shen2b3b1c62012-05-20 15:50:00 +0000212
Simon Glass918354b2014-10-29 13:08:57 -0600213#ifdef CONFIG_DM_GPIO
214static bool at91_get_port_output(struct at91_port *at91_port, int offset)
215{
216 u32 mask, val;
217
218 mask = 1 << offset;
219 val = readl(&at91_port->osr);
220 return val & mask;
221}
222#endif
223
224static void at91_set_port_input(struct at91_port *at91_port, int offset,
225 int use_pullup)
226{
227 u32 mask;
228
229 mask = 1 << offset;
230 writel(mask, &at91_port->idr);
231 at91_set_port_pullup(at91_port, offset, use_pullup);
232 writel(mask, &at91_port->odr);
233 writel(mask, &at91_port->per);
234}
235
Jens Scharsigea8fbba2010-02-03 22:46:16 +0100236/*
237 * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and
238 * configure it for an input.
239 */
240int at91_set_pio_input(unsigned port, u32 pin, int use_pullup)
241{
Bo Shen4bc9b7a2013-08-22 15:24:40 +0800242 struct at91_port *at91_port = at91_pio_get_port(port);
Jens Scharsigea8fbba2010-02-03 22:46:16 +0100243
Simon Glass918354b2014-10-29 13:08:57 -0600244 if (at91_port && (pin < GPIO_PER_BANK))
245 at91_set_port_input(at91_port, pin, use_pullup);
Bo Shen4bc9b7a2013-08-22 15:24:40 +0800246
Jens Scharsigea8fbba2010-02-03 22:46:16 +0100247 return 0;
248}
249
Simon Glass918354b2014-10-29 13:08:57 -0600250static void at91_set_port_output(struct at91_port *at91_port, int offset,
251 int value)
252{
253 u32 mask;
254
255 mask = 1 << offset;
256 writel(mask, &at91_port->idr);
257 writel(mask, &at91_port->pudr);
258 if (value)
259 writel(mask, &at91_port->sodr);
260 else
261 writel(mask, &at91_port->codr);
262 writel(mask, &at91_port->oer);
263 writel(mask, &at91_port->per);
264}
265
Jens Scharsigea8fbba2010-02-03 22:46:16 +0100266/*
267 * mux the pin to the gpio controller (instead of "A" or "B" peripheral),
268 * and configure it for an output.
269 */
270int at91_set_pio_output(unsigned port, u32 pin, int value)
271{
Bo Shen4bc9b7a2013-08-22 15:24:40 +0800272 struct at91_port *at91_port = at91_pio_get_port(port);
Jens Scharsigea8fbba2010-02-03 22:46:16 +0100273
Simon Glass918354b2014-10-29 13:08:57 -0600274 if (at91_port && (pin < GPIO_PER_BANK))
275 at91_set_port_output(at91_port, pin, value);
Bo Shen4bc9b7a2013-08-22 15:24:40 +0800276
Jens Scharsigea8fbba2010-02-03 22:46:16 +0100277 return 0;
278}
279
280/*
281 * enable/disable the glitch filter. mostly used with IRQ handling.
282 */
283int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on)
284{
Bo Shen4bc9b7a2013-08-22 15:24:40 +0800285 struct at91_port *at91_port = at91_pio_get_port(port);
286 u32 mask;
Jens Scharsigea8fbba2010-02-03 22:46:16 +0100287
Simon Glass918354b2014-10-29 13:08:57 -0600288 if (at91_port && (pin < GPIO_PER_BANK)) {
Jens Scharsigea8fbba2010-02-03 22:46:16 +0100289 mask = 1 << pin;
Wenyou Yang2dc63f72017-03-23 12:44:36 +0800290 if (is_on)
291 writel(mask, &at91_port->ifer);
292 else
293 writel(mask, &at91_port->ifdr);
294 }
295
296 return 0;
297}
298
299/*
300 * enable/disable the glitch filter. mostly used with IRQ handling.
301 */
302int at91_pio3_set_pio_deglitch(unsigned port, unsigned pin, int is_on)
303{
304 struct at91_port *at91_port = at91_pio_get_port(port);
305 u32 mask;
306
307 if (at91_port && (pin < GPIO_PER_BANK)) {
308 mask = 1 << pin;
Bo Shen2b3b1c62012-05-20 15:50:00 +0000309 if (is_on) {
Wenyou Yang2dc63f72017-03-23 12:44:36 +0800310 writel(mask, &at91_port->mux.pio3.ifscdr);
Bo Shen4bc9b7a2013-08-22 15:24:40 +0800311 writel(mask, &at91_port->ifer);
Bo Shen2b3b1c62012-05-20 15:50:00 +0000312 } else {
Bo Shen4bc9b7a2013-08-22 15:24:40 +0800313 writel(mask, &at91_port->ifdr);
Bo Shen2b3b1c62012-05-20 15:50:00 +0000314 }
Jens Scharsigea8fbba2010-02-03 22:46:16 +0100315 }
Bo Shen4bc9b7a2013-08-22 15:24:40 +0800316
Jens Scharsigea8fbba2010-02-03 22:46:16 +0100317 return 0;
318}
319
Bo Shen2b3b1c62012-05-20 15:50:00 +0000320/*
321 * enable/disable the debounce filter.
322 */
Wenyou Yang2dc63f72017-03-23 12:44:36 +0800323int at91_pio3_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div)
Bo Shen2b3b1c62012-05-20 15:50:00 +0000324{
Bo Shen4bc9b7a2013-08-22 15:24:40 +0800325 struct at91_port *at91_port = at91_pio_get_port(port);
326 u32 mask;
Bo Shen2b3b1c62012-05-20 15:50:00 +0000327
Simon Glass918354b2014-10-29 13:08:57 -0600328 if (at91_port && (pin < GPIO_PER_BANK)) {
Bo Shen2b3b1c62012-05-20 15:50:00 +0000329 mask = 1 << pin;
330 if (is_on) {
Wenyou Yang2dc63f72017-03-23 12:44:36 +0800331 writel(mask, &at91_port->mux.pio3.ifscer);
332 writel(div & PIO_SCDR_DIV, &at91_port->mux.pio3.scdr);
Bo Shen4bc9b7a2013-08-22 15:24:40 +0800333 writel(mask, &at91_port->ifer);
Bo Shen2b3b1c62012-05-20 15:50:00 +0000334 } else {
Bo Shen4bc9b7a2013-08-22 15:24:40 +0800335 writel(mask, &at91_port->ifdr);
Bo Shen2b3b1c62012-05-20 15:50:00 +0000336 }
337 }
Bo Shen4bc9b7a2013-08-22 15:24:40 +0800338
Bo Shen2b3b1c62012-05-20 15:50:00 +0000339 return 0;
340}
341
342/*
343 * enable/disable the pull-down.
344 * If pull-up already enabled while calling the function, we disable it.
345 */
Wenyou Yang2dc63f72017-03-23 12:44:36 +0800346int at91_pio3_set_pio_pulldown(unsigned port, unsigned pin, int is_on)
Bo Shen2b3b1c62012-05-20 15:50:00 +0000347{
Bo Shen4bc9b7a2013-08-22 15:24:40 +0800348 struct at91_port *at91_port = at91_pio_get_port(port);
349 u32 mask;
Bo Shen2b3b1c62012-05-20 15:50:00 +0000350
Simon Glass918354b2014-10-29 13:08:57 -0600351 if (at91_port && (pin < GPIO_PER_BANK)) {
Bo Shen2b3b1c62012-05-20 15:50:00 +0000352 mask = 1 << pin;
Marek Vasut152ac5f2016-05-04 23:05:23 +0200353 if (is_on) {
354 at91_set_pio_pullup(port, pin, 0);
Wenyou Yang2dc63f72017-03-23 12:44:36 +0800355 writel(mask, &at91_port->mux.pio3.ppder);
Marek Vasut152ac5f2016-05-04 23:05:23 +0200356 } else
Wenyou Yang2dc63f72017-03-23 12:44:36 +0800357 writel(mask, &at91_port->mux.pio3.ppddr);
Bo Shen2b3b1c62012-05-20 15:50:00 +0000358 }
Bo Shen4bc9b7a2013-08-22 15:24:40 +0800359
Bo Shen2b3b1c62012-05-20 15:50:00 +0000360 return 0;
361}
362
Wenyou Yang2dc63f72017-03-23 12:44:36 +0800363int at91_pio3_set_pio_pullup(unsigned port, unsigned pin, int use_pullup)
364{
365 struct at91_port *at91_port = at91_pio_get_port(port);
366
367 if (use_pullup)
368 at91_pio3_set_pio_pulldown(port, pin, 0);
369
370 if (at91_port && (pin < GPIO_PER_BANK))
371 at91_set_port_pullup(at91_port, pin, use_pullup);
372
373 return 0;
374}
375
Bo Shen2b3b1c62012-05-20 15:50:00 +0000376/*
377 * disable Schmitt trigger
378 */
Wenyou Yang2dc63f72017-03-23 12:44:36 +0800379int at91_pio3_set_pio_disable_schmitt_trig(unsigned port, unsigned pin)
Bo Shen2b3b1c62012-05-20 15:50:00 +0000380{
Bo Shen4bc9b7a2013-08-22 15:24:40 +0800381 struct at91_port *at91_port = at91_pio_get_port(port);
382 u32 mask;
Bo Shen2b3b1c62012-05-20 15:50:00 +0000383
Simon Glass918354b2014-10-29 13:08:57 -0600384 if (at91_port && (pin < GPIO_PER_BANK)) {
Bo Shen2b3b1c62012-05-20 15:50:00 +0000385 mask = 1 << pin;
Bo Shen4bc9b7a2013-08-22 15:24:40 +0800386 writel(readl(&at91_port->schmitt) | mask,
387 &at91_port->schmitt);
Bo Shen2b3b1c62012-05-20 15:50:00 +0000388 }
Bo Shen4bc9b7a2013-08-22 15:24:40 +0800389
Bo Shen2b3b1c62012-05-20 15:50:00 +0000390 return 0;
391}
Bo Shen2b3b1c62012-05-20 15:50:00 +0000392
Jens Scharsigea8fbba2010-02-03 22:46:16 +0100393/*
394 * enable/disable the multi-driver. This is only valid for output and
395 * allows the output pin to run as an open collector output.
396 */
397int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on)
398{
Bo Shen4bc9b7a2013-08-22 15:24:40 +0800399 struct at91_port *at91_port = at91_pio_get_port(port);
400 u32 mask;
Jens Scharsigea8fbba2010-02-03 22:46:16 +0100401
Simon Glass918354b2014-10-29 13:08:57 -0600402 if (at91_port && (pin < GPIO_PER_BANK)) {
Jens Scharsigea8fbba2010-02-03 22:46:16 +0100403 mask = 1 << pin;
404 if (is_on)
Bo Shen4bc9b7a2013-08-22 15:24:40 +0800405 writel(mask, &at91_port->mder);
Jens Scharsigea8fbba2010-02-03 22:46:16 +0100406 else
Bo Shen4bc9b7a2013-08-22 15:24:40 +0800407 writel(mask, &at91_port->mddr);
Jens Scharsigea8fbba2010-02-03 22:46:16 +0100408 }
Bo Shen4bc9b7a2013-08-22 15:24:40 +0800409
Jens Scharsigea8fbba2010-02-03 22:46:16 +0100410 return 0;
411}
412
Simon Glass918354b2014-10-29 13:08:57 -0600413static void at91_set_port_value(struct at91_port *at91_port, int offset,
414 int value)
415{
416 u32 mask;
417
418 mask = 1 << offset;
419 if (value)
420 writel(mask, &at91_port->sodr);
421 else
422 writel(mask, &at91_port->codr);
423}
424
Jens Scharsigea8fbba2010-02-03 22:46:16 +0100425/*
426 * assuming the pin is muxed as a gpio output, set its value.
427 */
428int at91_set_pio_value(unsigned port, unsigned pin, int value)
429{
Bo Shen4bc9b7a2013-08-22 15:24:40 +0800430 struct at91_port *at91_port = at91_pio_get_port(port);
Jens Scharsigea8fbba2010-02-03 22:46:16 +0100431
Simon Glass918354b2014-10-29 13:08:57 -0600432 if (at91_port && (pin < GPIO_PER_BANK))
433 at91_set_port_value(at91_port, pin, value);
Bo Shen4bc9b7a2013-08-22 15:24:40 +0800434
Jens Scharsigea8fbba2010-02-03 22:46:16 +0100435 return 0;
436}
437
Simon Glass918354b2014-10-29 13:08:57 -0600438static int at91_get_port_value(struct at91_port *at91_port, int offset)
439{
440 u32 pdsr = 0, mask;
441
442 mask = 1 << offset;
443 pdsr = readl(&at91_port->pdsr) & mask;
444
445 return pdsr != 0;
446}
Jens Scharsigea8fbba2010-02-03 22:46:16 +0100447/*
448 * read the pin's value (works even if it's not muxed as a gpio).
449 */
450int at91_get_pio_value(unsigned port, unsigned pin)
451{
Bo Shen4bc9b7a2013-08-22 15:24:40 +0800452 struct at91_port *at91_port = at91_pio_get_port(port);
Jens Scharsigea8fbba2010-02-03 22:46:16 +0100453
Simon Glass918354b2014-10-29 13:08:57 -0600454 if (at91_port && (pin < GPIO_PER_BANK))
455 return at91_get_port_value(at91_port, pin);
Bo Shen4bc9b7a2013-08-22 15:24:40 +0800456
Simon Glass918354b2014-10-29 13:08:57 -0600457 return 0;
Jens Scharsigea8fbba2010-02-03 22:46:16 +0100458}
Bo Shen6edaea82013-08-13 14:38:31 +0800459
Simon Glass918354b2014-10-29 13:08:57 -0600460#ifndef CONFIG_DM_GPIO
Bo Shen6edaea82013-08-13 14:38:31 +0800461/* Common GPIO API */
462
Bo Shen6edaea82013-08-13 14:38:31 +0800463int gpio_request(unsigned gpio, const char *label)
464{
465 return 0;
466}
467
468int gpio_free(unsigned gpio)
469{
470 return 0;
471}
472
473int gpio_direction_input(unsigned gpio)
474{
475 at91_set_pio_input(at91_gpio_to_port(gpio),
476 at91_gpio_to_pin(gpio), 0);
477 return 0;
478}
479
480int gpio_direction_output(unsigned gpio, int value)
481{
482 at91_set_pio_output(at91_gpio_to_port(gpio),
483 at91_gpio_to_pin(gpio), value);
484 return 0;
485}
486
487int gpio_get_value(unsigned gpio)
488{
489 return at91_get_pio_value(at91_gpio_to_port(gpio),
490 at91_gpio_to_pin(gpio));
491}
492
493int gpio_set_value(unsigned gpio, int value)
494{
495 at91_set_pio_value(at91_gpio_to_port(gpio),
496 at91_gpio_to_pin(gpio), value);
497
498 return 0;
499}
Simon Glass918354b2014-10-29 13:08:57 -0600500#endif
501
502#ifdef CONFIG_DM_GPIO
503
504struct at91_port_priv {
505 struct at91_port *regs;
506};
507
508/* set GPIO pin 'gpio' as an input */
509static int at91_gpio_direction_input(struct udevice *dev, unsigned offset)
510{
Axel Lind8958212015-01-31 14:47:34 +0800511 struct at91_port_priv *port = dev_get_priv(dev);
Simon Glass918354b2014-10-29 13:08:57 -0600512
513 at91_set_port_input(port->regs, offset, 0);
514
515 return 0;
516}
517
518/* set GPIO pin 'gpio' as an output, with polarity 'value' */
519static int at91_gpio_direction_output(struct udevice *dev, unsigned offset,
520 int value)
521{
Axel Lind8958212015-01-31 14:47:34 +0800522 struct at91_port_priv *port = dev_get_priv(dev);
Simon Glass918354b2014-10-29 13:08:57 -0600523
524 at91_set_port_output(port->regs, offset, value);
525
526 return 0;
527}
528
529/* read GPIO IN value of pin 'gpio' */
530static int at91_gpio_get_value(struct udevice *dev, unsigned offset)
531{
Axel Lind8958212015-01-31 14:47:34 +0800532 struct at91_port_priv *port = dev_get_priv(dev);
Simon Glass918354b2014-10-29 13:08:57 -0600533
534 return at91_get_port_value(port->regs, offset);
535}
536
537/* write GPIO OUT value to pin 'gpio' */
538static int at91_gpio_set_value(struct udevice *dev, unsigned offset,
539 int value)
540{
Axel Lind8958212015-01-31 14:47:34 +0800541 struct at91_port_priv *port = dev_get_priv(dev);
Simon Glass918354b2014-10-29 13:08:57 -0600542
543 at91_set_port_value(port->regs, offset, value);
544
545 return 0;
546}
547
548static int at91_gpio_get_function(struct udevice *dev, unsigned offset)
549{
Axel Lind8958212015-01-31 14:47:34 +0800550 struct at91_port_priv *port = dev_get_priv(dev);
Simon Glass918354b2014-10-29 13:08:57 -0600551
552 /* GPIOF_FUNC is not implemented yet */
553 if (at91_get_port_output(port->regs, offset))
554 return GPIOF_OUTPUT;
555 else
556 return GPIOF_INPUT;
557}
558
James Byrnef3510e92019-11-26 11:52:04 +0000559static const char *at91_get_bank_name(uint32_t base_addr)
560{
561 switch (base_addr) {
562 case ATMEL_BASE_PIOA:
563 return "PIOA";
564 case ATMEL_BASE_PIOB:
565 return "PIOB";
566 case ATMEL_BASE_PIOC:
567 return "PIOC";
568#if (ATMEL_PIO_PORTS > 3)
569 case ATMEL_BASE_PIOD:
570 return "PIOD";
571#if (ATMEL_PIO_PORTS > 4)
572 case ATMEL_BASE_PIOE:
573 return "PIOE";
574#endif
575#endif
576 }
577
578 return "undefined";
579}
580
Simon Glass918354b2014-10-29 13:08:57 -0600581static const struct dm_gpio_ops gpio_at91_ops = {
582 .direction_input = at91_gpio_direction_input,
583 .direction_output = at91_gpio_direction_output,
584 .get_value = at91_gpio_get_value,
585 .set_value = at91_gpio_set_value,
586 .get_function = at91_gpio_get_function,
587};
588
589static int at91_gpio_probe(struct udevice *dev)
590{
591 struct at91_port_priv *port = dev_get_priv(dev);
592 struct at91_port_platdata *plat = dev_get_platdata(dev);
Simon Glasse564f052015-03-05 12:25:20 -0700593 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
Wenyou Yangf2f3c152017-03-23 12:46:21 +0800594 struct clk clk;
595 int ret;
596
597 ret = clk_get_by_index(dev, 0, &clk);
598 if (ret)
599 return ret;
600
601 ret = clk_enable(&clk);
602 if (ret)
603 return ret;
604
605 clk_free(&clk);
Simon Glass918354b2014-10-29 13:08:57 -0600606
Wenyou Yangcf468882017-03-23 12:46:20 +0800607#if CONFIG_IS_ENABLED(OF_CONTROL)
Simon Glassa821c4a2017-05-17 17:18:05 -0600608 plat->base_addr = (uint32_t)devfdt_get_addr_ptr(dev);
Wenyou Yangcf468882017-03-23 12:46:20 +0800609#endif
James Byrnef3510e92019-11-26 11:52:04 +0000610 plat->bank_name = at91_get_bank_name(plat->base_addr);
Simon Glass918354b2014-10-29 13:08:57 -0600611 port->regs = (struct at91_port *)plat->base_addr;
612
James Byrnef3510e92019-11-26 11:52:04 +0000613 uc_priv->bank_name = plat->bank_name;
614 uc_priv->gpio_count = GPIO_PER_BANK;
615
Simon Glass918354b2014-10-29 13:08:57 -0600616 return 0;
617}
618
Wenyou Yangcf468882017-03-23 12:46:20 +0800619#if CONFIG_IS_ENABLED(OF_CONTROL)
620static const struct udevice_id at91_gpio_ids[] = {
621 { .compatible = "atmel,at91rm9200-gpio" },
622 { }
623};
624#endif
625
Simon Glass918354b2014-10-29 13:08:57 -0600626U_BOOT_DRIVER(gpio_at91) = {
627 .name = "gpio_at91",
628 .id = UCLASS_GPIO,
Wenyou Yangcf468882017-03-23 12:46:20 +0800629#if CONFIG_IS_ENABLED(OF_CONTROL)
630 .of_match = at91_gpio_ids,
631 .platdata_auto_alloc_size = sizeof(struct at91_port_platdata),
632#endif
Simon Glass918354b2014-10-29 13:08:57 -0600633 .ops = &gpio_at91_ops,
634 .probe = at91_gpio_probe,
635 .priv_auto_alloc_size = sizeof(struct at91_port_priv),
636};
637#endif