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Tom Rini4ee73b02021-07-07 22:55:41 -04001// SPDX-License-Identifier: GPL-2.0+
2/*
Tony Dinhdbd2a382022-04-17 13:42:42 -07003 * Copyright (C) 2015, 2021-2022 Tony Dinh <mibodhi@gmail.com>
Tony Dinh5c151bf2021-07-07 02:06:47 -07004 * Copyright (C) 2015 Gerald Kerma <dreagle@doukki.net>
Tom Rini4ee73b02021-07-07 22:55:41 -04005 */
6
7#include <common.h>
8#include <init.h>
Tony Dinhdbd2a382022-04-17 13:42:42 -07009#include <netdev.h>
Tom Rini4ee73b02021-07-07 22:55:41 -040010#include <asm/arch/cpu.h>
11#include <asm/arch/soc.h>
12#include <asm/arch/mpp.h>
13#include <asm/global_data.h>
14#include <asm/io.h>
Tony Dinhdbd2a382022-04-17 13:42:42 -070015#include <linux/bitops.h>
Tom Rini4ee73b02021-07-07 22:55:41 -040016
17DECLARE_GLOBAL_DATA_PTR;
18
Tony Dinhdbd2a382022-04-17 13:42:42 -070019/*
20 * low GPIO's
21 */
22#define HDD1_GREEN_LED BIT(16)
23#define HDD1_RED_LED BIT(13)
24#define USB_GREEN_LED BIT(15)
25#define USB_POWER BIT(21)
26#define SYS_GREEN_LED BIT(28)
27#define SYS_ORANGE_LED BIT(29)
28
29#define COPY_GREEN_LED BIT(22)
30#define COPY_RED_LED BIT(23)
31
32#define PIN_USB_GREEN_LED 15
33#define PIN_USB_POWER 21
34
35#define NSA310S_OE_LOW (~(0))
36#define NSA310S_VAL_LOW (SYS_GREEN_LED | USB_POWER)
37
38/*
39 * high GPIO's
40 */
41#define HDD2_GREEN_LED BIT(2)
42#define HDD2_POWER BIT(1)
43
44#define NSA310S_OE_HIGH (~(0))
45#define NSA310S_VAL_HIGH (HDD2_POWER)
46
Tom Rini4ee73b02021-07-07 22:55:41 -040047int board_early_init_f(void)
48{
49 /*
50 * default gpio configuration
51 * There are maximum 64 gpios controlled through 2 sets of registers
52 * the below configuration configures mainly initial LED status
53 */
54 mvebu_config_gpio(NSA310S_VAL_LOW, NSA310S_VAL_HIGH,
55 NSA310S_OE_LOW, NSA310S_OE_HIGH);
56
57 /* (all LEDs & power off active high) */
58 /* Multi-Purpose Pins Functionality configuration */
59 static const u32 kwmpp_config[] = {
60 MPP0_NF_IO2,
61 MPP1_NF_IO3,
62 MPP2_NF_IO4,
63 MPP3_NF_IO5,
64 MPP4_NF_IO6,
65 MPP5_NF_IO7,
66 MPP6_SYSRST_OUTn,
67 MPP7_GPO,
68 MPP8_TW_SDA,
69 MPP9_TW_SCK,
70 MPP10_UART0_TXD,
71 MPP11_UART0_RXD,
72 MPP12_GPO,
73 MPP13_GPIO,
74 MPP14_GPIO,
75 MPP15_GPIO,
76 MPP16_GPIO,
77 MPP17_GPIO,
78 MPP18_NF_IO0,
79 MPP19_NF_IO1,
80 MPP20_GPIO,
81 MPP21_GPIO,
82 MPP22_GPIO,
83 MPP23_GPIO,
84 MPP24_GPIO,
85 MPP25_GPIO,
86 MPP26_GPIO,
87 MPP27_GPIO,
88 MPP28_GPIO,
89 MPP29_GPIO,
90 MPP30_GPIO,
91 MPP31_GPIO,
92 MPP32_GPIO,
93 MPP33_GPIO,
94 MPP34_GPIO,
95 MPP35_GPIO,
96 0
97 };
98 kirkwood_mpp_conf(kwmpp_config, NULL);
99 return 0;
100}
101
102int board_init(void)
103{
104 /* address of boot parameters */
105 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
106
107 return 0;
108}
109
Tony Dinhdbd2a382022-04-17 13:42:42 -0700110int board_eth_init(struct bd_info *bis)
Tony Dinh5c151bf2021-07-07 02:06:47 -0700111{
Tony Dinhdbd2a382022-04-17 13:42:42 -0700112 return cpu_eth_init(bis);
Tony Dinh5c151bf2021-07-07 02:06:47 -0700113}