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wdenk074cff02004-02-24 00:16:43 +00001/*
2 * (C) Copyright 2004
3 * DAVE Srl
4 *
5 * http://www.dave-tech.it
6 * http://www.wawnet.biz
7 * mailto:info@wawnet.biz
8 *
9 * Configuation settings for the B2 board.
10 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
30#ifndef __CONFIG_H
31#define __CONFIG_H
32
33/*
wdenk074cff02004-02-24 00:16:43 +000034 * High Level Configuration Options
35 * (easy to change)
36 */
37#define CONFIG_ARM7 1 /* This is a ARM7 CPU */
38#define CONFIG_B2 1 /* on an B2 Board */
39#define CONFIG_ARM_THUMB 1 /* this is an ARM7TDMI */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020040#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */
wdenk074cff02004-02-24 00:16:43 +000041
42#define CONFIG_S3C44B0_CLOCK_SPEED 75 /* we have a 75Mhz S3C44B0*/
43
44
45#undef CONFIG_USE_IRQ /* don't need them anymore */
46
47
48/*
49 * Size of malloc() pool
50 */
51#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
52#define CFG_ENV_SIZE 1024 /* 1024 bytes may be used for env vars*/
53#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024 )
54#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
55
56/*
57 * Hardware drivers
58 */
59#define CONFIG_DRIVER_LAN91C96
60#define CONFIG_LAN91C96_BASE 0x04000300 /* base address */
61#define CONFIG_SMC_USE_32_BIT
62#undef CONFIG_SHOW_ACTIVITY
63#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */
64
65/*
66 * select serial console configuration
67 */
68#define CONFIG_SERIAL1 1 /* we use Serial line 1 */
69
70/* allow to overwrite serial and ethaddr */
71#define CONFIG_ENV_OVERWRITE
72
73#define CONFIG_BAUDRATE 115200
74
Jon Loeliger5d2ebe12007-07-09 21:16:53 -050075/*
76 * BOOTP options
77 */
78#define CONFIG_BOOTP_SUBNETMASK
79#define CONFIG_BOOTP_GATEWAY
80#define CONFIG_BOOTP_HOSTNAME
81#define CONFIG_BOOTP_BOOTPATH
82#define CONFIG_BOOTP_BOOTFILESIZE
wdenk074cff02004-02-24 00:16:43 +000083
wdenk074cff02004-02-24 00:16:43 +000084
Jon Loeligerde8b2a62007-07-05 19:32:07 -050085/*
86 * Command line configuration.
87 */
88#include <config_cmd_default.h>
89
90#define CONFIG_CMD_DATE
91#define CONFIG_CMD_ELF
92#define CONFIG_CMD_EEPROM
93#define CONFIG_CMD_I2C
94
wdenk074cff02004-02-24 00:16:43 +000095
96#define CONFIG_BOOTDELAY 5
97#define CONFIG_ETHADDR 00:50:c2:1e:af:fb
98#define CONFIG_BOOTARGS "setenv bootargs root=/dev/ram ip=192.168.0.70:::::eth0:off \
99 ether=25,0,0,0,eth0 ethaddr=00:50:c2:1e:af:fb"
100#define CONFIG_NETMASK 255.255.0.0
101#define CONFIG_IPADDR 192.168.0.70
102#define CONFIG_SERVERIP 192.168.0.23
103#define CONFIG_BOOTFILE "B2-rootfs/usr/B2-zImage.u-boot"
104#define CONFIG_BOOTCOMMAND "bootm 20000 f0000"
105
106/*
107 * Miscellaneous configurable options
108 */
109#define CFG_LONGHELP /* undef to save memory */
110#define CFG_PROMPT "=> " /* Monitor Command Prompt */
111#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
112#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
113#define CFG_MAXARGS 16 /* max number of command args */
114#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
115
116#define CFG_MEMTEST_START 0x0C400000 /* memtest works on */
117#define CFG_MEMTEST_END 0x0C800000 /* 4 ... 8 MB in DRAM */
118
119#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
120
121#define CFG_LOAD_ADDR 0x0c700000 /* default load address */
122
123#define CFG_HZ 1000 /* 1 kHz */
124
125 /* valid baudrates */
126#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
127
128/*-----------------------------------------------------------------------
129 * Stack sizes
130 *
131 * The stack sizes are set up in start.S using the settings below
132 */
133#define CONFIG_STACKSIZE (128*1024) /* regular stack */
134#ifdef CONFIG_USE_IRQ
135#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
136#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
137#endif
138
139/*-----------------------------------------------------------------------
140 * Physical Memory Map
141 */
142#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 banks of DRAM */
143#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */
144#define PHYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */
145
146#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
147#define PHYS_FLASH_SIZE 0x00400000 /* 4 MB */
148
149#define CFG_FLASH_BASE PHYS_FLASH_1
150
151/*-----------------------------------------------------------------------
152 * FLASH and environment organization
153 */
154/*-----------------------------------------------------------------------
155 * FLASH organization
156 */
157#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
158#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
159
160#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
161#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
162
163#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
164#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
165#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
166/*
167 * The following defines are added for buggy IOP480 byte interface.
168 * All other boards should use the standard values (CPCI405 etc.)
169 */
170#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
171#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
172#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
173
174#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
175
176/*-----------------------------------------------------------------------
177 * Environment Variable setup
178 */
179#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
180#define CFG_ENV_OFFSET 0x0 /* environment starts at the beginning of the EEPROM */
181
182/*-----------------------------------------------------------------------
183 * I2C EEPROM (STM24C02W6) for environment
184 */
185#define CONFIG_HARD_I2C /* I2c with hardware support */
186#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
187#define CFG_I2C_SLAVE 0xFE
188
189#define CFG_I2C_EEPROM_ADDR 0xA8 /* EEPROM STM24C02W6 */
190#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
191/* mask of address bits that overflow into the "EEPROM chip address" */
192/*#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07*/
193#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
194 /* 16 byte page write mode using*/
195 /* last 4 bits of the address */
196#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
197#define CFG_EEPROM_PAGE_WRITE_ENABLE
198
199/* Flash banks JFFS2 should use */
200/*
201#define CFG_JFFS2_FIRST_BANK 0
202#define CFG_JFFS2_FIRST_SECTOR 2
203#define CFG_JFFS2_NUM_BANKS 1
204*/
205
206/*
207 Linux TAGs (see lib_arm/armlinux.c)
208*/
209#define CONFIG_CMDLINE_TAG
210#undef CONFIG_SETUP_MEMORY_TAGS
211#define CONFIG_INITRD_TAG
212
213#endif /* __CONFIG_H */