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stroesea20b27a2004-12-16 18:05:42 +00001/*
2 * (C) Copyright 2004
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
Stefan Roese82f4c6a2005-08-12 16:52:47 +020035#define CONFIG_IDENT_STRING " $Name: $"
stroesea20b27a2004-12-16 18:05:42 +000036
37#define CONFIG_405EP 1 /* This is a PPC405 CPU */
38#define CONFIG_4xx 1 /* ...member of PPC4xx family */
39#define CONFIG_WUH405 1 /* ...on a WUH405 board */
40
41#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
42#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
43
44#define CONFIG_SYS_CLK_FREQ 33333300 /* external frequency to pll */
45
46#define CONFIG_BAUDRATE 9600
47#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
48
49#undef CONFIG_BOOTARGS
50#undef CONFIG_BOOTCOMMAND
51
52#define CONFIG_PREBOOT /* enable preboot variable */
53
54#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
55#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
56
57#define CONFIG_MII 1 /* MII PHY management */
58#define CONFIG_PHY_ADDR 0 /* PHY address */
59#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
60
61#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
62
stroesea20b27a2004-12-16 18:05:42 +000063
Jon Loeligera5562902007-07-08 15:31:57 -050064/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -050065 * BOOTP options
66 */
67#define CONFIG_BOOTP_BOOTFILESIZE
68#define CONFIG_BOOTP_BOOTPATH
69#define CONFIG_BOOTP_GATEWAY
70#define CONFIG_BOOTP_HOSTNAME
71
72
73/*
Jon Loeligera5562902007-07-08 15:31:57 -050074 * Command line configuration.
75 */
76#include <config_cmd_default.h>
77
78#define CONFIG_CMD_DHCP
79#define CONFIG_CMD_IRQ
80#define CONFIG_CMD_ELF
81#define CONFIG_CMD_NAND
82#define CONFIG_CMD_DATE
83#define CONFIG_CMD_I2C
84#define CONFIG_CMD_MII
85#define CONFIG_CMD_PING
86#define CONFIG_CMD_EEPROM
87
stroesea20b27a2004-12-16 18:05:42 +000088
89#undef CONFIG_WATCHDOG /* watchdog disabled */
90
91#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
92#define CFG_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
93
94#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
95
96/*
97 * Miscellaneous configurable options
98 */
99#define CFG_LONGHELP /* undef to save memory */
100#define CFG_PROMPT "=> " /* Monitor Command Prompt */
101
102#undef CFG_HUSH_PARSER /* use "hush" command parser */
103#ifdef CFG_HUSH_PARSER
104#define CFG_PROMPT_HUSH_PS2 "> "
105#endif
106
Jon Loeligera5562902007-07-08 15:31:57 -0500107#if defined(CONFIG_CMD_KGDB)
stroesea20b27a2004-12-16 18:05:42 +0000108#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
109#else
110#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
111#endif
112#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
113#define CFG_MAXARGS 16 /* max number of command args */
114#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
115
116#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
117
118#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
119
120#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
121#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
122
123#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
124#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
125#define CFG_BASE_BAUD 691200
126#define CONFIG_UART1_CONSOLE /* define for uart1 as console */
127
128/* The following table includes the supported baudrates */
129#define CFG_BAUDRATE_TABLE \
130 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
131 57600, 115200, 230400, 460800, 921600 }
132
133#define CFG_LOAD_ADDR 0x100000 /* default load address */
134#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
135
136#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
137
138#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
139
140#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
141
142#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
143
144/*-----------------------------------------------------------------------
145 * NAND-FLASH stuff
146 *-----------------------------------------------------------------------
147 */
Matthias Fuchsbd84ee42007-07-09 10:10:06 +0200148#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
149#define NAND_MAX_CHIPS 1
150#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
151#define NAND_BIG_DELAY_US 25
Bartlomiej Siekaaddb2e12006-03-05 18:57:33 +0100152
Matthias Fuchsbd84ee42007-07-09 10:10:06 +0200153#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
154#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
155#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
156#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
stroesea20b27a2004-12-16 18:05:42 +0000157
stroesea20b27a2004-12-16 18:05:42 +0000158#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
159
160/*-----------------------------------------------------------------------
161 * PCI stuff
162 *-----------------------------------------------------------------------
163 */
164#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
165#define PCI_HOST_FORCE 1 /* configure as pci host */
166#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
167
168#define CONFIG_PCI /* include pci support */
169#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */
170#undef CONFIG_PCI_PNP /* do pci plug-and-play */
171 /* resource configuration */
172
173#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
174
175#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
176#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
177#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
178#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
179#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
180#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
181#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
182#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
183#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
184
185/*-----------------------------------------------------------------------
186 * Start addresses for the final memory configuration
187 * (Set up by the startup code)
188 * Please note that CFG_SDRAM_BASE _must_ start at 0
189 */
190#define CFG_SDRAM_BASE 0x00000000
191#define CFG_FLASH_BASE 0xFFFC0000
192#define CFG_MONITOR_BASE CFG_FLASH_BASE
193#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
194#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
195
196/*
197 * For booting Linux, the board info and command line data
198 * have to be in the first 8 MB of memory, since this is
199 * the maximum mapped by the Linux kernel during initialization.
200 */
201#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
202/*-----------------------------------------------------------------------
203 * FLASH organization
204 */
205#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
206#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
207
208#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
209#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
210
211#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
212#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
213#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
214/*
215 * The following defines are added for buggy IOP480 byte interface.
216 * All other boards should use the standard values (CPCI405 etc.)
217 */
218#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
219#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
220#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
221
222#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
223
224#if 0 /* test-only */
225#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
226#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
227#endif
228
229/*-----------------------------------------------------------------------
230 * Environment Variable setup
231 */
232#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
233#define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
234#define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
235 /* total size of a CAT24WC16 is 2048 bytes */
236
237#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
238#define CFG_NVRAM_SIZE 242 /* NVRAM size */
239
240/*-----------------------------------------------------------------------
241 * I2C EEPROM (CAT24WC16) for environment
242 */
243#define CONFIG_HARD_I2C /* I2c with hardware support */
244#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
245#define CFG_I2C_SLAVE 0x7F
246
247#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
248#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
249/* mask of address bits that overflow into the "EEPROM chip address" */
250#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
251#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
252 /* 16 byte page write mode using*/
253 /* last 4 bits of the address */
254#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
255#define CFG_EEPROM_PAGE_WRITE_ENABLE
256
stroesea20b27a2004-12-16 18:05:42 +0000257/*
258 * Init Memory Controller:
259 *
260 * BR0/1 and OR0/1 (FLASH)
261 */
262
263#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
264
265/*-----------------------------------------------------------------------
266 * External Bus Controller (EBC) Setup
267 */
268
269/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
270#define CFG_EBC_PB0AP 0x92015480
271/*#define CFG_EBC_PB0AP 0x08055880 /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
272#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
273
274/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
275#define CFG_EBC_PB1AP 0x92015480
276#define CFG_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
277
278/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
279#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
280#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
281
282/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */
283#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
284#define CFG_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
285
286#define CAN_BA 0xF0000000 /* CAN Base Address */
287#define DUART0_BA 0xF0000400 /* DUART Base Address */
288#define DUART1_BA 0xF0000408 /* DUART Base Address */
289#define DUART2_BA 0xF0000410 /* DUART Base Address */
290#define DUART3_BA 0xF0000418 /* DUART Base Address */
291#define RTC_BA 0xF0000500 /* RTC Base Address */
292#define CFG_NAND_BASE 0xF4000000
293
294/*-----------------------------------------------------------------------
295 * FPGA stuff
296 */
297#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
298#define CFG_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
299
300/* FPGA program pin configuration */
301#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
302#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
303#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
304#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
305#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
306
307/*-----------------------------------------------------------------------
308 * Definitions for initial stack pointer and data area (in data cache)
309 */
310/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
311#define CFG_TEMP_STACK_OCM 1
312
313/* On Chip Memory location */
314#define CFG_OCM_DATA_ADDR 0xF8000000
315#define CFG_OCM_DATA_SIZE 0x1000
316#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
317#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
318
319#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
320#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
321#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
322
323/*-----------------------------------------------------------------------
324 * Definitions for GPIO setup (PPC405EP specific)
325 *
326 * GPIO0[0] - External Bus Controller BLAST output
327 * GPIO0[1-9] - Instruction trace outputs -> GPIO
328 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
329 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
330 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
331 * GPIO0[24-27] - UART0 control signal inputs/outputs
332 * GPIO0[28-29] - UART1 data signal input/output
333 * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
334 */
335#define CFG_GPIO0_OSRH 0x40000550
336#define CFG_GPIO0_OSRL 0x00000110
337#define CFG_GPIO0_ISR1H 0x00000000
338#define CFG_GPIO0_ISR1L 0x15555445
339#define CFG_GPIO0_TSRH 0x00000000
340#define CFG_GPIO0_TSRL 0x00000000
341#define CFG_GPIO0_TCR 0xF7FE0014
342
343#define CFG_DUART_RST (0x80000000 >> 14)
344
345/*
346 * Internal Definitions
347 *
348 * Boot Flags
349 */
350#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
351#define BOOTFLAG_WARM 0x02 /* Software reboot */
352
353/*
354 * Default speed selection (cpu_plb_opb_ebc) in mhz.
355 * This value will be set if iic boot eprom is disabled.
356 */
357#if 0
358#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
359#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
360#endif
361#if 1
362#define PLLMR0_DEFAULT PLLMR0_200_100_50_33
363#define PLLMR1_DEFAULT PLLMR1_200_100_50_33
364#endif
365#if 0
366#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
367#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
368#endif
369
370#endif /* __CONFIG_H */