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wdenk507bbe32004-04-18 21:13:41 +00001/*
2 * (C) Copyright 2004 Atmark Techno, Inc.
3 *
4 * Yasushi SHOJI <yashi@atmark-techno.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#ifndef __CONFIG_H
26#define __CONFIG_H
27
28/*
wdenk507bbe32004-04-18 21:13:41 +000029 * High Level Configuration Options
30 * (easy to change)
31 */
32
wdenk857cad32004-07-10 23:48:41 +000033#define CONFIG_MICROBLAZE 1 /* This is an MicroBlaze CPU */
wdenk507bbe32004-04-18 21:13:41 +000034#define CONFIG_SUZAKU 1 /* on an SUZAKU Board */
35
36/*-----------------------------------------------------------------------
37 * Start addresses for the final memory configuration
38 * (Set up by the startup code)
39 * Please note that CFG_SDRAM_BASE _must_ start at 0
40 */
41#define CFG_SDRAM_BASE 0x80000000
42#define CFG_SDRAM_SIZE 0x01000000
43#define CFG_FLASH_BASE 0xfff00000
wdenk857cad32004-07-10 23:48:41 +000044#define CFG_FLASH_SIZE 0x00400000
wdenk507bbe32004-04-18 21:13:41 +000045#define CFG_RESET_ADDRESS 0xfff00100
46#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
Michal Simek17980492007-03-26 01:39:07 +020047#define CFG_MONITOR_BASE (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - (1024 * 1024))
wdenk507bbe32004-04-18 21:13:41 +000048#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */
Michal Simek17980492007-03-26 01:39:07 +020049#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - (1024 * 1024))
wdenk507bbe32004-04-18 21:13:41 +000050
Michal Simek0731cba2007-09-24 00:25:11 +020051#define CONFIG_XILINX_UARTLITE
wdenk507bbe32004-04-18 21:13:41 +000052#define CONFIG_BAUDRATE 115200
53#define CFG_BAUDRATE_TABLE { 115200 }
54
Michal Simek6f934212007-03-30 22:42:45 +020055/* System Register (GPIO) */
56#define MICROBLAZE_SYSREG_BASE_ADDR 0xFFFFA000
57#define MICROBLAZE_SYSREG_RECONFIGURE (1 << 0)
58
Jon Loeliger079a1362007-07-10 10:12:10 -050059/*
Jon Loeliger46da1e92007-07-04 22:33:30 -050060 * Command line configuration.
61 */
62#include <config_cmd_default.h>
63
Michal Simekf2403562007-09-24 00:36:06 +020064#undef CONFIG_CMD_BDI
65#undef CONFIG_CMD_ENV
66#undef CONFIG_CMD_MEMORY
67#undef CONFIG_CMD_NET
68#undef CONFIG_CMD_MISC
wdenk507bbe32004-04-18 21:13:41 +000069
70#define CFG_UART1_BASE (0xFFFF2000)
71#define CONFIG_SERIAL_BASE CFG_UART1_BASE
72
73/*
74 * Miscellaneous configurable options
75 */
76#define CFG_LONGHELP /* undef to save memory */
77#define CFG_PROMPT "SUZAKU> " /* Monitor Command Prompt */
78#define CFG_CBSIZE 256
79#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
80#define CFG_MAXARGS 16 /* max number of command args */
81
82#define CFG_LOAD_ADDR CFG_SDRAM_BASE /* default load address */
83
84/*-----------------------------------------------------------------------
85 * FLASH organization
86 */
87#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
88#define CFG_MAX_FLASH_SECT 1 /* max number of sectors on one chip */
89
90/*-----------------------------------------------------------------------
91 * NVRAM organization
92 */
93#define CFG_ENV_IS_NOWHERE 1
94#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
95#define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */
96
wdenk857cad32004-07-10 23:48:41 +000097/*-----------------------------------------------------------------------
98 * Definitions for initial stack pointer and data area (in DPRAM)
99 */
100
101#define CFG_INIT_RAM_ADDR 0x80000000 /* inside of SDRAM */
102#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
103#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
104#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
105#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
106
Michal Simekf2403562007-09-24 00:36:06 +0200107#define XILINX_CLOCK_FREQ 50000000
108#define CONFIG_XILINX_CLOCK_FREQ XILINX_CLOCK_FREQ
109
wdenk507bbe32004-04-18 21:13:41 +0000110#endif /* __CONFIG_H */