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Kumar Gala3b558e22008-01-17 02:02:10 -06001/*
2 * Copyright 2008 Freescale Semiconductor, Inc.
3 *
4 * (C) Copyright 2000
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#include <common.h>
27#include <asm/mmu.h>
28
29struct fsl_e_tlb_entry tlb_table[] = {
30 /* TLB 0 - for temp stack in cache */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020031 SET_TLB_ENTRY (0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +020032 MAS3_SX | MAS3_SW | MAS3_SR, 0,
33 0, 0, BOOKE_PAGESZ_4K, 0),
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020034 SET_TLB_ENTRY (0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
35 CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +020036 MAS3_SX | MAS3_SW | MAS3_SR, 0,
37 0, 0, BOOKE_PAGESZ_4K, 0),
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020038 SET_TLB_ENTRY (0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
39 CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +020040 MAS3_SX | MAS3_SW | MAS3_SR, 0,
41 0, 0, BOOKE_PAGESZ_4K, 0),
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020042 SET_TLB_ENTRY (0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
43 CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +020044 MAS3_SX | MAS3_SW | MAS3_SR, 0,
45 0, 0, BOOKE_PAGESZ_4K, 0),
Kumar Gala3b558e22008-01-17 02:02:10 -060046
Wolfgang Grandeggere8cc3f02008-06-05 13:12:10 +020047#ifndef CONFIG_TQM_BIGFLASH
Kumar Gala3b558e22008-01-17 02:02:10 -060048 /*
49 * TLB 0, 1: 128M Non-cacheable, guarded
50 * 0xf8000000 128M FLASH
51 * Out of reset this entry is only 4K.
52 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020053 SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +020054 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
55 0, 1, BOOKE_PAGESZ_64M, 1),
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020056 SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE + 0x4000000,
57 CONFIG_SYS_FLASH_BASE + 0x4000000,
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +020058 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
59 0, 0, BOOKE_PAGESZ_64M, 1),
Kumar Gala3b558e22008-01-17 02:02:10 -060060
61 /*
62 * TLB 2: 256M Non-cacheable, guarded
63 * 0x80000000 256M PCI1 MEM First half
64 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020065 SET_TLB_ENTRY (1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +020066 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
67 0, 2, BOOKE_PAGESZ_256M, 1),
Kumar Gala3b558e22008-01-17 02:02:10 -060068
69 /*
70 * TLB 3: 256M Non-cacheable, guarded
71 * 0x90000000 256M PCI1 MEM Second half
72 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020073 SET_TLB_ENTRY (1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
74 CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +020075 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
76 0, 3, BOOKE_PAGESZ_256M, 1),
Kumar Gala3b558e22008-01-17 02:02:10 -060077
Wolfgang Grandeggerb9e80782008-06-05 13:12:08 +020078#ifdef CONFIG_PCIE1
79 /*
80 * TLB 4: 256M Non-cacheable, guarded
81 * 0xc0000000 256M PCI express MEM First half
82 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020083 SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BASE, CONFIG_SYS_PCIE1_MEM_BASE,
Wolfgang Grandeggerb9e80782008-06-05 13:12:08 +020084 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
85 0, 4, BOOKE_PAGESZ_256M, 1),
86
87 /*
88 * TLB 5: 256M Non-cacheable, guarded
89 * 0xd0000000 256M PCI express MEM Second half
90 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091 SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BASE + 0x10000000,
92 CONFIG_SYS_PCIE1_MEM_BASE + 0x10000000,
Wolfgang Grandeggerb9e80782008-06-05 13:12:08 +020093 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
94 0, 5, BOOKE_PAGESZ_256M, 1),
95#else /* !CONFIG_PCIE */
Kumar Gala3b558e22008-01-17 02:02:10 -060096 /*
97 * TLB 4: 256M Non-cacheable, guarded
98 * 0xc0000000 256M Rapid IO MEM First half
99 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200100 SET_TLB_ENTRY (1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE,
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200101 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
102 0, 4, BOOKE_PAGESZ_256M, 1),
Kumar Gala3b558e22008-01-17 02:02:10 -0600103
104 /*
105 * TLB 5: 256M Non-cacheable, guarded
106 * 0xd0000000 256M Rapid IO MEM Second half
107 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108 SET_TLB_ENTRY (1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
109 CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200110 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
111 0, 5, BOOKE_PAGESZ_256M, 1),
Wolfgang Grandeggerb9e80782008-06-05 13:12:08 +0200112#endif /* CONFIG_PCIE */
Kumar Gala3b558e22008-01-17 02:02:10 -0600113
114 /*
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200115 * TLB 6: 64M Non-cacheable, guarded
116 * 0xe0000000 1M CCSRBAR
117 * 0xe2000000 16M PCI1 IO
Wolfgang Grandegger1c2deff2008-06-05 13:12:09 +0200118 * 0xe3000000 16M CAN and NAND Flash
Kumar Gala3b558e22008-01-17 02:02:10 -0600119 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120 SET_TLB_ENTRY (1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200121 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
122 0, 6, BOOKE_PAGESZ_64M, 1),
Kumar Gala3b558e22008-01-17 02:02:10 -0600123
Wolfgang Grandeggerdc5f55d2009-02-11 18:38:24 +0100124#if defined(CONFIG_TQM8548_AG) || defined (CONFIG_TQM8548_BE)
125 /*
126 * TLB 7+8: 2G DDR, cache enabled
127 * 0x00000000 2G DDR System memory
128 * Without SPD EEPROM configured DDR, this must be setup manually.
129 */
130 SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
131 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
132 0, 7, BOOKE_PAGESZ_1G, 1),
133
134 SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
135 CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
136 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
137 0, 8, BOOKE_PAGESZ_1G, 1),
138#else
Kumar Gala3b558e22008-01-17 02:02:10 -0600139 /*
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200140 * TLB 7+8: 512M DDR, cache disabled (needed for memory test)
141 * 0x00000000 512M DDR System memory
Kumar Gala3b558e22008-01-17 02:02:10 -0600142 * Without SPD EEPROM configured DDR, this must be setup manually.
Kumar Gala3b558e22008-01-17 02:02:10 -0600143 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144 SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200145 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
146 0, 7, BOOKE_PAGESZ_256M, 1),
Kumar Gala3b558e22008-01-17 02:02:10 -0600147
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148 SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
149 CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200150 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
151 0, 8, BOOKE_PAGESZ_256M, 1),
Wolfgang Grandeggerdc5f55d2009-02-11 18:38:24 +0100152#endif
Wolfgang Grandeggerb9e80782008-06-05 13:12:08 +0200153#ifdef CONFIG_PCIE1
154 /*
155 * TLB 9: 16M Non-cacheable, guarded
156 * 0xef000000 16M PCI express IO
157 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158 SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_IO_BASE, CONFIG_SYS_PCIE1_IO_BASE,
Wolfgang Grandeggerb9e80782008-06-05 13:12:08 +0200159 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
160 0, 9, BOOKE_PAGESZ_16M, 1),
161#endif /* CONFIG_PCIE */
162
Wolfgang Grandeggere8cc3f02008-06-05 13:12:10 +0200163#else /* CONFIG_TQM_BIGFLASH */
164
165 /*
166 * TLB 0,1,2,3: 1G Non-cacheable, guarded
167 * 0xc0000000 1G FLASH
168 * Out of reset this entry is only 4K.
169 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170 SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
Wolfgang Grandeggere8cc3f02008-06-05 13:12:10 +0200171 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
172 0, 3, BOOKE_PAGESZ_256M, 1),
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173 SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE + 0x10000000,
174 CONFIG_SYS_FLASH_BASE + 0x10000000,
Wolfgang Grandeggere8cc3f02008-06-05 13:12:10 +0200175 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
176 0, 2, BOOKE_PAGESZ_256M, 1),
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177 SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE + 0x20000000,
178 CONFIG_SYS_FLASH_BASE + 0x20000000,
Wolfgang Grandeggere8cc3f02008-06-05 13:12:10 +0200179 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
180 0, 1, BOOKE_PAGESZ_256M, 1),
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181 SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE + 0x30000000,
182 CONFIG_SYS_FLASH_BASE + 0x30000000,
Wolfgang Grandeggere8cc3f02008-06-05 13:12:10 +0200183 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
184 0, 0, BOOKE_PAGESZ_256M, 1),
185
186 /*
187 * TLB 4: 256M Non-cacheable, guarded
188 * 0x80000000 256M PCI1 MEM First half
189 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190 SET_TLB_ENTRY (1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
Wolfgang Grandeggere8cc3f02008-06-05 13:12:10 +0200191 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
192 0, 4, BOOKE_PAGESZ_256M, 1),
193
194 /*
195 * TLB 5: 256M Non-cacheable, guarded
196 * 0x90000000 256M PCI1 MEM Second half
197 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198 SET_TLB_ENTRY (1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
199 CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
Wolfgang Grandeggere8cc3f02008-06-05 13:12:10 +0200200 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
201 0, 5, BOOKE_PAGESZ_256M, 1),
202
203#ifdef CONFIG_PCIE1
204 /*
205 * TLB 6: 256M Non-cacheable, guarded
206 * 0xc0000000 256M PCI express MEM First half
207 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208 SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BASE, CONFIG_SYS_PCIE1_MEM_BASE,
Wolfgang Grandeggere8cc3f02008-06-05 13:12:10 +0200209 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
210 0, 6, BOOKE_PAGESZ_256M, 1),
211#else /* !CONFIG_PCIE */
212 /*
213 * TLB 6: 256M Non-cacheable, guarded
214 * 0xb0000000 256M Rapid IO MEM First half
215 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216 SET_TLB_ENTRY (1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE,
Wolfgang Grandeggere8cc3f02008-06-05 13:12:10 +0200217 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
218 0, 6, BOOKE_PAGESZ_256M, 1),
219
220#endif /* CONFIG_PCIE */
221
222 /*
223 * TLB 7: 64M Non-cacheable, guarded
224 * 0xa0000000 1M CCSRBAR
225 * 0xa2000000 16M PCI1 IO
226 * 0xa3000000 16M CAN and NAND Flash
227 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228 SET_TLB_ENTRY (1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
Wolfgang Grandeggere8cc3f02008-06-05 13:12:10 +0200229 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
230 0, 7, BOOKE_PAGESZ_64M, 1),
231
232 /*
233 * TLB 8+9: 512M DDR, cache disabled (needed for memory test)
234 * 0x00000000 512M DDR System memory
235 * Without SPD EEPROM configured DDR, this must be setup manually.
236 * Make sure the TLB count at the top of this table is correct.
237 * Likely it needs to be increased by two for these entries.
238 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239 SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
Wolfgang Grandeggere8cc3f02008-06-05 13:12:10 +0200240 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
241 0, 8, BOOKE_PAGESZ_256M, 1),
242
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243 SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
244 CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
Wolfgang Grandeggere8cc3f02008-06-05 13:12:10 +0200245 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
246 0, 9, BOOKE_PAGESZ_256M, 1),
247
248#ifdef CONFIG_PCIE1
249 /*
250 * TLB 10: 16M Non-cacheable, guarded
251 * 0xaf000000 16M PCI express IO
252 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200253 SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_IO_BASE, CONFIG_SYS_PCIE1_IO_BASE,
Wolfgang Grandeggere8cc3f02008-06-05 13:12:10 +0200254 MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
255 0, 10, BOOKE_PAGESZ_16M, 1),
256#endif /* CONFIG_PCIE */
257
258#endif /* CONFIG_TQM_BIGFLASH */
Kumar Gala3b558e22008-01-17 02:02:10 -0600259};
260
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200261int num_tlb_entries = ARRAY_SIZE (tlb_table);