Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Ben Whitten | b2e01ff | 2017-11-23 13:47:48 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Configuation settings for the WB50N CPU Module. |
Ben Whitten | b2e01ff | 2017-11-23 13:47:48 +0000 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef __CONFIG_H |
| 7 | #define __CONFIG_H |
| 8 | |
| 9 | #include <asm/hardware.h> |
| 10 | |
Ben Whitten | b2e01ff | 2017-11-23 13:47:48 +0000 | [diff] [blame] | 11 | /* ARM asynchronous clock */ |
| 12 | #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 |
| 13 | #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ |
| 14 | |
Ben Whitten | b2e01ff | 2017-11-23 13:47:48 +0000 | [diff] [blame] | 15 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ |
| 16 | #define CONFIG_SETUP_MEMORY_TAGS |
| 17 | #define CONFIG_INITRD_TAG |
| 18 | |
| 19 | #ifndef CONFIG_SPL_BUILD |
| 20 | #define CONFIG_SKIP_LOWLEVEL_INIT |
| 21 | #endif |
| 22 | |
Ben Whitten | b2e01ff | 2017-11-23 13:47:48 +0000 | [diff] [blame] | 23 | /* general purpose I/O */ |
| 24 | #define CONFIG_AT91_GPIO |
| 25 | |
| 26 | /* serial console */ |
| 27 | #define CONFIG_ATMEL_USART |
| 28 | #define CONFIG_USART_BASE ATMEL_BASE_DBGU |
| 29 | #define CONFIG_USART_ID ATMEL_ID_DBGU |
| 30 | |
| 31 | /* |
| 32 | * BOOTP options |
| 33 | */ |
| 34 | #define CONFIG_BOOTP_BOOTFILESIZE |
Ben Whitten | b2e01ff | 2017-11-23 13:47:48 +0000 | [diff] [blame] | 35 | |
| 36 | /* SDRAM */ |
Ben Whitten | b2e01ff | 2017-11-23 13:47:48 +0000 | [diff] [blame] | 37 | #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS |
| 38 | #define CONFIG_SYS_SDRAM_SIZE 0x04000000 |
| 39 | |
| 40 | #ifdef CONFIG_SPL_BUILD |
| 41 | #define CONFIG_SYS_INIT_SP_ADDR 0x310000 |
| 42 | #else |
| 43 | #define CONFIG_SYS_INIT_SP_ADDR \ |
| 44 | (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) |
| 45 | #endif |
| 46 | |
| 47 | #define CONFIG_SYS_MEMTEST_START 0x21000000 |
| 48 | #define CONFIG_SYS_MEMTEST_END 0x22000000 |
Ben Whitten | b2e01ff | 2017-11-23 13:47:48 +0000 | [diff] [blame] | 49 | |
| 50 | /* NAND flash */ |
Ben Whitten | b2e01ff | 2017-11-23 13:47:48 +0000 | [diff] [blame] | 51 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
| 52 | #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 |
| 53 | /* our ALE is AD21 */ |
| 54 | #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) |
| 55 | /* our CLE is AD22 */ |
| 56 | #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) |
| 57 | #define CONFIG_SYS_NAND_ONFI_DETECTION |
Ben Whitten | b2e01ff | 2017-11-23 13:47:48 +0000 | [diff] [blame] | 58 | |
| 59 | /* Ethernet Hardware */ |
| 60 | #define CONFIG_MACB |
| 61 | #define CONFIG_RMII |
| 62 | #define CONFIG_NET_RETRY_COUNT 20 |
| 63 | #define CONFIG_MACB_SEARCH_PHY |
| 64 | #define CONFIG_RGMII |
| 65 | #define CONFIG_ETHADDR C0:EE:40:00:00:00 |
| 66 | #define CONFIG_ENV_OVERWRITE 1 |
| 67 | |
| 68 | #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ |
| 69 | |
| 70 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 71 | "autoload=no\0" \ |
| 72 | "autostart=no\0" |
| 73 | |
| 74 | /* bootstrap + u-boot + env in nandflash */ |
Ben Whitten | b2e01ff | 2017-11-23 13:47:48 +0000 | [diff] [blame] | 75 | #define CONFIG_ENV_OFFSET_REDUND 0xC0000 |
Ben Whitten | b2e01ff | 2017-11-23 13:47:48 +0000 | [diff] [blame] | 76 | #define CONFIG_BOOTCOMMAND \ |
| 77 | "nand read 0x22000000 0x000e0000 0x500000; " \ |
| 78 | "bootm" |
| 79 | |
| 80 | #define CONFIG_BOOTARGS \ |
| 81 | "rw rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs" |
| 82 | |
| 83 | #define CONFIG_BAUDRATE 115200 |
| 84 | |
| 85 | #define CONFIG_SYS_CBSIZE 1024 |
| 86 | #define CONFIG_SYS_MAXARGS 16 |
| 87 | #define CONFIG_SYS_PBSIZE \ |
| 88 | (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
Ben Whitten | b2e01ff | 2017-11-23 13:47:48 +0000 | [diff] [blame] | 89 | |
| 90 | /* Size of malloc() pool */ |
| 91 | #define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) |
| 92 | |
| 93 | /* SPL */ |
Ben Whitten | b2e01ff | 2017-11-23 13:47:48 +0000 | [diff] [blame] | 94 | #define CONFIG_SPL_MAX_SIZE 0x10000 |
| 95 | #define CONFIG_SPL_BSS_START_ADDR 0x20000000 |
| 96 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 |
| 97 | #define CONFIG_SYS_SPL_MALLOC_START 0x20080000 |
| 98 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 |
| 99 | |
| 100 | #define CONFIG_SYS_MONITOR_LEN (512 << 10) |
| 101 | |
| 102 | #define CONFIG_SPL_NAND_DRIVERS |
| 103 | #define CONFIG_SPL_NAND_BASE |
| 104 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 |
| 105 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE |
| 106 | #define CONFIG_SYS_NAND_PAGE_SIZE 0x800 |
| 107 | #define CONFIG_SYS_NAND_PAGE_COUNT 64 |
| 108 | #define CONFIG_SYS_NAND_OOBSIZE 64 |
| 109 | #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 |
| 110 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 |
Ben Whitten | b2e01ff | 2017-11-23 13:47:48 +0000 | [diff] [blame] | 111 | |
| 112 | #endif |